Make the firmware of the right keyboard half work on the UHK PCB by using the IRC48MCLK of the K22. This fix was implemented by Santiago.
This commit is contained in:
László Monda
@@ -28,147 +28,10 @@
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include "fsl_common.h"
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#include "fsl_smc.h"
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#include "fsl_smc.h"
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#include "clock_config.h"
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#include "clock_config.h"
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#include "fsl_rtc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Clock configuration structure. */
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typedef struct _clock_config
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{
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mcg_config_t mcgConfig; /*!< MCG configuration. */
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sim_clock_config_t simConfig; /*!< SIM configuration. */
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osc_config_t oscConfig; /*!< OSC configuration. */
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uint32_t coreClock; /*!< core clock frequency. */
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} clock_config_t;
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/* Configuration for enter VLPR mode. Core clock = 4MHz. */
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const clock_config_t g_defaultClockConfigVlpr = {
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.mcgConfig =
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{
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.mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
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.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
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.ircs = kMCG_IrcFast, /* Select IRC4M. */
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.fcrdiv = 0U, /* FCRDIV is 0. */
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.frdiv = 0U,
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.drs = kMCG_DrsLow, /* Low frequency range. */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
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.oscsel = kMCG_OscselOsc, /* Select OSC. */
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.pll0Config =
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{
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.enableMode = 0U, /* Don't eanble PLL. */
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.prdiv = 0U,
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.vdiv = 0U,
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},
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},
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.simConfig =
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{
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.pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
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.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
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.clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
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},
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.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
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.capLoad = 0,
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.workMode = kOSC_ModeOscLowPower,
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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}},
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.coreClock = 4000000U, /* Core clock frequency */
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};
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/* Configuration for enter RUN mode. Core clock = 80MHz. */
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const clock_config_t g_defaultClockConfigRun = {
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.mcgConfig =
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{
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.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
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.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
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.ircs = kMCG_IrcSlow, /* Select IRC32k.*/
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.fcrdiv = 0U, /* FCRDIV is 0. */
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.frdiv = 3U,
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.drs = kMCG_DrsLow, /* Low frequency range. */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
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.oscsel = kMCG_OscselOsc, /* Select OSC. */
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.pll0Config =
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{
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.enableMode = 0U, .prdiv = 0x3U, .vdiv = 0x10U,
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},
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},
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.simConfig =
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{
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.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
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.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
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.clkdiv1 = 0x01230000U, /* SIM_CLKDIV1. */
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},
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.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
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.capLoad = 0,
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.workMode = kOSC_ModeOscLowPower,
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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}},
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.coreClock = 80000000U, /* Core clock frequency */
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};
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/* Configuration for HSRUN mode. Core clock = 120MHz. */
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const clock_config_t g_defaultClockConfigHsrun = {
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.mcgConfig =
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{
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.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
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.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
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.ircs = kMCG_IrcSlow, /* Select IRC32k. */
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.fcrdiv = 0U, /* FCRDIV is 0. */
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.frdiv = 3U,
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.drs = kMCG_DrsLow, /* Low frequency range. */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
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.oscsel = kMCG_OscselOsc, /* Select OSC. */
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.pll0Config =
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{
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.enableMode = 0U, .prdiv = 0x1U, .vdiv = 0x6U,
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},
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},
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.simConfig =
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{
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.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
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.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
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.clkdiv1 = 0x01340000U, /* SIM_CLKDIV1. */
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},
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.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
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.capLoad = 0,
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.workMode = kOSC_ModeOscLowPower,
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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}},
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.coreClock = 120000000U, /* Core clock frequency */
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};
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*
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/*
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* How to setup clock using clock driver functions:
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* How to setup clock using clock driver functions:
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*
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*
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@@ -197,62 +60,232 @@ const clock_config_t g_defaultClockConfigHsrun = {
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* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
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* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
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*/
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*/
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void BOARD_BootClockVLPR(void)
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
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#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
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#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
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#define RTC_OSC_CAP_LOAD_12PF 0x1800U /*!< RTC oscillator capacity load: 12pF */
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#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */
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#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U /*!< CLKOUT pin clock select: FlexBus clock */
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#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
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#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
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#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
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#define SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK 0U /*!< RTC clock output select: RTC1HzCLK clock */
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#define SIM_RTC_CLKOUT_SEL_RTC32KCLK_CLK 1U /*!< RTC clock output select: RTC32KCLK clock (32.768kHz) */
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#define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK 1U /*!< Trace clock select: Core/system clock */
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#define SIM_USB_CLK_120000000HZ 120000000U /*!< Input SIM frequency for USB: 120000000Hz */
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#define SIM_USB_CLK_48000000HZ 48000000U /*!< Input SIM frequency for USB: 48000000Hz */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetRtcClock
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* Description : This function is used to configuring RTC clock including
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* enabling RTC oscillator.
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* Param capLoad : RTC oscillator capacity load
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* Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph)
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{
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{
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CLOCK_SetSimSafeDivs();
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/* RTC clock gate enable */
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CLOCK_EnableClock(kCLOCK_Rtc0);
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CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
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if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */
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g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
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/* Set the specified capacitor configuration for the RTC oscillator */
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RTC_SetOscCapLoad(RTC, capLoad);
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CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
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/* Enable the RTC 32KHz oscillator */
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RTC->CR |= RTC_CR_OSCE_MASK;
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SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
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}
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/* Output to other peripherals */
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SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
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if (enableOutPeriph) {
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SMC_SetPowerModeVlpr(SMC);
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RTC->CR &= ~RTC_CR_CLKO_MASK;
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while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
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}
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{
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else {
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}
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RTC->CR |= RTC_CR_CLKO_MASK;
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}
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/* Set the XTAL32/RTC_CLKIN frequency based on board setting. */
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CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
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/* Set RTC_TSR if there is fault value in RTC */
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if (RTC->SR & RTC_SR_TIF_MASK) {
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RTC -> TSR = RTC -> TSR;
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}
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/* RTC clock gate disable */
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CLOCK_DisableClock(kCLOCK_Rtc0);
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}
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
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* Description : Configure FLL external reference divider (FRDIV).
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* Param frdiv : The value to set FRDIV.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
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{
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MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const mcg_config_t mcgConfig_BOARD_BootClockRUN =
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{
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.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
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.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
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.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
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.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
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.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
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.drs = kMCG_DrsLow, /* Low frequency range */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
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.oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */
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.pll0Config =
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{
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.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
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.prdiv = 0xbU, /* PLL Reference divider: divided by 12 */
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.vdiv = 0x6U, /* VCO divider: multiplied by 30 */
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},
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};
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const sim_clock_config_t simConfig_BOARD_BootClockRUN =
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{
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.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
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.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
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.clkdiv1 = 0x1340000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /5 */
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};
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const osc_config_t oscConfig_BOARD_BootClockRUN =
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{
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.freq = 0U, /* Oscillator frequency: 0Hz */
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.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
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.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
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.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
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}
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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void BOARD_BootClockRUN(void)
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{
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{
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CLOCK_SetSimSafeDivs();
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/* Set HSRUN power mode */
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CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
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CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
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CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
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&g_defaultClockConfigRun.mcgConfig.pll0Config);
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CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
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g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
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CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
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SystemCoreClock = g_defaultClockConfigRun.coreClock;
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}
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void BOARD_BootClockHSRUN(void)
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{
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SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
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SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
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SMC_SetPowerModeHsrun(SMC);
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SMC_SetPowerModeHsrun(SMC);
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while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
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while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
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{
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{
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}
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}
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/* Set the system clock dividers in SIM to safe value. */
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CLOCK_SetSimSafeDivs();
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CLOCK_SetSimSafeDivs();
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/* Configure RTC clock including enabling RTC oscillator. */
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CLOCK_InitOsc0(&g_defaultClockConfigHsrun.oscConfig);
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CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_12PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED);
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CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
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/* Configure the Internal Reference clock (MCGIRCLK). */
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CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
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CLOCK_BootToPeeMode(g_defaultClockConfigHsrun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
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mcgConfig_BOARD_BootClockRUN.ircs,
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&g_defaultClockConfigHsrun.mcgConfig.pll0Config);
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mcgConfig_BOARD_BootClockRUN.fcrdiv);
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/* Configure FLL external reference divider (FRDIV). */
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CLOCK_SetInternalRefClkConfig(g_defaultClockConfigHsrun.mcgConfig.irclkEnableMode,
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CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
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g_defaultClockConfigHsrun.mcgConfig.ircs, g_defaultClockConfigHsrun.mcgConfig.fcrdiv);
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/* Set MCG to PEE mode. */
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CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
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CLOCK_SetSimConfig(&g_defaultClockConfigHsrun.simConfig);
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kMCG_PllClkSelPll0,
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&mcgConfig_BOARD_BootClockRUN.pll0Config);
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SystemCoreClock = g_defaultClockConfigHsrun.coreClock;
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/* Set the clock configuration in SIM module. */
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CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
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/* Set SystemCoreClock variable. */
|
||||||
|
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||||
|
/* Set RTC_CLKOUT source. */
|
||||||
|
CLOCK_SetRtcClkOutClock(SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK);
|
||||||
|
/* Enable USB FS clock. */
|
||||||
|
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcExt, SIM_USB_CLK_48000000HZ);
|
||||||
|
/* Set CLKOUT source. */
|
||||||
|
CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
|
||||||
|
/* Set debug trace clock source. */
|
||||||
|
CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables for BOARD_BootClockVLPR configuration
|
||||||
|
******************************************************************************/
|
||||||
|
const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
|
||||||
|
{
|
||||||
|
.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
|
||||||
|
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||||
|
.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
|
||||||
|
.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
|
||||||
|
.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
|
||||||
|
.drs = kMCG_DrsLow, /* Low frequency range */
|
||||||
|
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
|
||||||
|
.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
|
||||||
|
.pll0Config =
|
||||||
|
{
|
||||||
|
.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
|
||||||
|
.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
|
||||||
|
.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
|
||||||
|
},
|
||||||
|
};
|
||||||
|
const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
|
||||||
|
{
|
||||||
|
.pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
|
||||||
|
.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
|
||||||
|
.clkdiv1 = 0x140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /5 */
|
||||||
|
};
|
||||||
|
const osc_config_t oscConfig_BOARD_BootClockVLPR =
|
||||||
|
{
|
||||||
|
.freq = 0U, /* Oscillator frequency: 0Hz */
|
||||||
|
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||||
|
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
|
||||||
|
.oscerConfig =
|
||||||
|
{
|
||||||
|
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
|
||||||
|
.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code for BOARD_BootClockVLPR configuration
|
||||||
|
******************************************************************************/
|
||||||
|
void BOARD_BootClockVLPR(void)
|
||||||
|
{
|
||||||
|
/* Note: This function expects that the SLOW_IRCLK is trimmed to non-default
|
||||||
|
frequency 0Hz (default frequency: 32768Hz). */
|
||||||
|
/* Set the system clock dividers in SIM to safe value. */
|
||||||
|
CLOCK_SetSimSafeDivs();
|
||||||
|
/* Set MCG to BLPI mode. */
|
||||||
|
CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
|
||||||
|
mcgConfig_BOARD_BootClockVLPR.ircs,
|
||||||
|
mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
|
||||||
|
/* Set the clock configuration in SIM module. */
|
||||||
|
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
|
||||||
|
/* Set VLPR power mode. */
|
||||||
|
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||||
|
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
|
||||||
|
SMC_SetPowerModeVlpr(SMC, false);
|
||||||
|
#else
|
||||||
|
SMC_SetPowerModeVlpr(SMC);
|
||||||
|
#endif
|
||||||
|
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* Set SystemCoreClock variable. */
|
||||||
|
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||||||
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -27,24 +27,115 @@
|
|||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef _CLOCK_CONFIG_H_
|
#ifndef _CLOCK_CONFIG_H_
|
||||||
#define _CLOCK_CONFIG_H_
|
#define _CLOCK_CONFIG_H_
|
||||||
|
#include "fsl_common.h"
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Definitions
|
* Definitions
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
#define BOARD_XTAL0_CLK_HZ 8000000U
|
#define BOARD_XTAL0_CLK_HZ 8000000U /*!< Board xtal0 frequency in Hz */
|
||||||
#define BOARD_XTAL32K_CLK_HZ 32768U
|
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board RTC xtal frequency in Hz */
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* API
|
********************** Configuration BOARD_BootClockRUN ***********************
|
||||||
|
******************************************************************************/
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions for BOARD_BootClockRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */
|
||||||
|
|
||||||
|
/*! @brief MCG set for BOARD_BootClockRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
|
||||||
|
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
|
||||||
|
/*! @brief OSC set for BOARD_BootClockRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API for BOARD_BootClockRUN configuration
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
#if defined(__cplusplus)
|
#if defined(__cplusplus)
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif /* __cplusplus*/
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
void BOARD_BootClockVLPR(void);
|
/*!
|
||||||
|
* @brief This function executes configuration of clocks.
|
||||||
|
*
|
||||||
|
*/
|
||||||
void BOARD_BootClockRUN(void);
|
void BOARD_BootClockRUN(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||||
|
******************************************************************************/
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions for BOARD_BootClockVLPR configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
|
||||||
|
|
||||||
|
/*! @brief MCG set for BOARD_BootClockVLPR configuration.
|
||||||
|
*/
|
||||||
|
extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
|
||||||
|
/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
|
||||||
|
*/
|
||||||
|
extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
|
||||||
|
/*! @brief OSC set for BOARD_BootClockVLPR configuration.
|
||||||
|
*/
|
||||||
|
extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API for BOARD_BootClockVLPR configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief This function executes configuration of clocks.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void BOARD_BootClockVLPR(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
********************* Configuration BOARD_BootClockHSRUN **********************
|
||||||
|
******************************************************************************/
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions for BOARD_BootClockHSRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */
|
||||||
|
|
||||||
|
/*! @brief MCG set for BOARD_BootClockHSRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN;
|
||||||
|
/*! @brief SIM module set for BOARD_BootClockHSRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN;
|
||||||
|
/*! @brief OSC set for BOARD_BootClockHSRUN configuration.
|
||||||
|
*/
|
||||||
|
extern const osc_config_t oscConfig_BOARD_BootClockHSRUN;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API for BOARD_BootClockHSRUN configuration
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief This function executes configuration of clocks.
|
||||||
|
*
|
||||||
|
*/
|
||||||
void BOARD_BootClockHSRUN(void);
|
void BOARD_BootClockHSRUN(void);
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
#if defined(__cplusplus)
|
||||||
@@ -52,3 +143,4 @@ void BOARD_BootClockHSRUN(void);
|
|||||||
#endif /* __cplusplus*/
|
#endif /* __cplusplus*/
|
||||||
|
|
||||||
#endif /* _CLOCK_CONFIG_H_ */
|
#endif /* _CLOCK_CONFIG_H_ */
|
||||||
|
|
||||||
|
|||||||
@@ -8,7 +8,7 @@
|
|||||||
void main(void)
|
void main(void)
|
||||||
{
|
{
|
||||||
BOARD_InitPins();
|
BOARD_InitPins();
|
||||||
BOARD_BootClockHSRUN();
|
BOARD_BootClockRUN();
|
||||||
BOARD_InitDebugConsole();
|
BOARD_InitDebugConsole();
|
||||||
|
|
||||||
i2c_master_config_t masterConfig;
|
i2c_master_config_t masterConfig;
|
||||||
|
|||||||
Reference in New Issue
Block a user