diff --git a/right/include/board/clock_config.c b/right/include/board/clock_config.c index feda869..25d0cdd 100644 --- a/right/include/board/clock_config.c +++ b/right/include/board/clock_config.c @@ -1,258 +1,291 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -#include "fsl_smc.h" -#include "clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Clock configuration structure. */ -typedef struct _clock_config -{ - mcg_config_t mcgConfig; /*!< MCG configuration. */ - sim_clock_config_t simConfig; /*!< SIM configuration. */ - osc_config_t oscConfig; /*!< OSC configuration. */ - uint32_t coreClock; /*!< core clock frequency. */ -} clock_config_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/* Configuration for enter VLPR mode. Core clock = 4MHz. */ -const clock_config_t g_defaultClockConfigVlpr = { - .mcgConfig = - { - .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ - .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ - .ircs = kMCG_IrcFast, /* Select IRC4M. */ - .fcrdiv = 0U, /* FCRDIV is 0. */ - - .frdiv = 0U, - .drs = kMCG_DrsLow, /* Low frequency range. */ - .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ - .oscsel = kMCG_OscselOsc, /* Select OSC. */ - - .pll0Config = - { - .enableMode = 0U, /* Don't eanble PLL. */ - .prdiv = 0U, - .vdiv = 0U, - }, - }, - .simConfig = - { - .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */ - .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ - .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ - }, - .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, - .capLoad = 0, - .workMode = kOSC_ModeOscLowPower, - .oscerConfig = - { - .enableMode = kOSC_ErClkEnable, -#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) - .erclkDiv = 0U, -#endif - }}, - .coreClock = 4000000U, /* Core clock frequency */ -}; - -/* Configuration for enter RUN mode. Core clock = 80MHz. */ -const clock_config_t g_defaultClockConfigRun = { - .mcgConfig = - { - .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ - .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ - .ircs = kMCG_IrcSlow, /* Select IRC32k.*/ - .fcrdiv = 0U, /* FCRDIV is 0. */ - - .frdiv = 3U, - .drs = kMCG_DrsLow, /* Low frequency range. */ - .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ - .oscsel = kMCG_OscselOsc, /* Select OSC. */ - - .pll0Config = - { - .enableMode = 0U, .prdiv = 0x3U, .vdiv = 0x10U, - }, - }, - .simConfig = - { - .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ - .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ - .clkdiv1 = 0x01230000U, /* SIM_CLKDIV1. */ - }, - .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, - .capLoad = 0, - .workMode = kOSC_ModeOscLowPower, - .oscerConfig = - { - .enableMode = kOSC_ErClkEnable, -#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) - .erclkDiv = 0U, -#endif - }}, - .coreClock = 80000000U, /* Core clock frequency */ -}; - -/* Configuration for HSRUN mode. Core clock = 120MHz. */ -const clock_config_t g_defaultClockConfigHsrun = { - .mcgConfig = - { - .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ - .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ - .ircs = kMCG_IrcSlow, /* Select IRC32k. */ - .fcrdiv = 0U, /* FCRDIV is 0. */ - - .frdiv = 3U, - .drs = kMCG_DrsLow, /* Low frequency range. */ - .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ - .oscsel = kMCG_OscselOsc, /* Select OSC. */ - - .pll0Config = - { - .enableMode = 0U, .prdiv = 0x1U, .vdiv = 0x6U, - }, - }, - .simConfig = - { - .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ - .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ - .clkdiv1 = 0x01340000U, /* SIM_CLKDIV1. */ - }, - .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, - .capLoad = 0, - .workMode = kOSC_ModeOscLowPower, - .oscerConfig = - { - .enableMode = kOSC_ErClkEnable, -#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) - .erclkDiv = 0U, -#endif - }}, - .coreClock = 120000000U, /* Core clock frequency */ -}; - -/******************************************************************************* - * Code - ******************************************************************************/ -/* - * How to setup clock using clock driver functions: - * - * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock - * and flash clock are in allowed range during clock mode switch. - * - * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. - * - * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and - * internal reference clock(MCGIRCLK). Follow the steps to setup: - * - * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. - * - * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured - * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig - * explicitly to setup MCGIRCLK. - * - * 3). Don't need to configure FLL explicitly, because if target mode is FLL - * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, - * if the target mode is not FLL mode, the FLL is disabled. - * - * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been - * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could - * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. - * - * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. - */ - -void BOARD_BootClockVLPR(void) -{ - CLOCK_SetSimSafeDivs(); - - CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, - g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); - - CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); - - SystemCoreClock = g_defaultClockConfigVlpr.coreClock; - - SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); - SMC_SetPowerModeVlpr(SMC); - while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) - { - } -} - -void BOARD_BootClockRUN(void) -{ - CLOCK_SetSimSafeDivs(); - - CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig); - CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); - - CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0, - &g_defaultClockConfigRun.mcgConfig.pll0Config); - - CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode, - g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv); - - CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); - - SystemCoreClock = g_defaultClockConfigRun.coreClock; -} - -void BOARD_BootClockHSRUN(void) -{ - SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); - SMC_SetPowerModeHsrun(SMC); - while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) - { - } - - CLOCK_SetSimSafeDivs(); - - CLOCK_InitOsc0(&g_defaultClockConfigHsrun.oscConfig); - CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); - - CLOCK_BootToPeeMode(g_defaultClockConfigHsrun.mcgConfig.oscsel, kMCG_PllClkSelPll0, - &g_defaultClockConfigHsrun.mcgConfig.pll0Config); - - CLOCK_SetInternalRefClkConfig(g_defaultClockConfigHsrun.mcgConfig.irclkEnableMode, - g_defaultClockConfigHsrun.mcgConfig.ircs, g_defaultClockConfigHsrun.mcgConfig.fcrdiv); - - CLOCK_SetSimConfig(&g_defaultClockConfigHsrun.simConfig); - - SystemCoreClock = g_defaultClockConfigHsrun.coreClock; -} +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "fsl_smc.h" +#include "clock_config.h" +#include "fsl_rtc.h" +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ +#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ +#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ +#define RTC_OSC_CAP_LOAD_12PF 0x1800U /*!< RTC oscillator capacity load: 12pF */ +#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */ +#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U /*!< CLKOUT pin clock select: FlexBus clock */ +#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ +#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */ +#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ +#define SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK 0U /*!< RTC clock output select: RTC1HzCLK clock */ +#define SIM_RTC_CLKOUT_SEL_RTC32KCLK_CLK 1U /*!< RTC clock output select: RTC32KCLK clock (32.768kHz) */ +#define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK 1U /*!< Trace clock select: Core/system clock */ +#define SIM_USB_CLK_120000000HZ 120000000U /*!< Input SIM frequency for USB: 120000000Hz */ +#define SIM_USB_CLK_48000000HZ 48000000U /*!< Input SIM frequency for USB: 48000000Hz */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_CONFIG_SetRtcClock + * Description : This function is used to configuring RTC clock including + * enabling RTC oscillator. + * Param capLoad : RTC oscillator capacity load + * Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals + * + *END**************************************************************************/ +static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph) +{ + /* RTC clock gate enable */ + CLOCK_EnableClock(kCLOCK_Rtc0); + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */ + /* Set the specified capacitor configuration for the RTC oscillator */ + RTC_SetOscCapLoad(RTC, capLoad); + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + } + /* Output to other peripherals */ + if (enableOutPeriph) { + RTC->CR &= ~RTC_CR_CLKO_MASK; + } + else { + RTC->CR |= RTC_CR_CLKO_MASK; + } + /* Set the XTAL32/RTC_CLKIN frequency based on board setting. */ + CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ); + /* Set RTC_TSR if there is fault value in RTC */ + if (RTC->SR & RTC_SR_TIF_MASK) { + RTC -> TSR = RTC -> TSR; + } + /* RTC clock gate disable */ + CLOCK_DisableClock(kCLOCK_Rtc0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_CONFIG_SetFllExtRefDiv + * Description : Configure FLL external reference divider (FRDIV). + * Param frdiv : The value to set FRDIV. + * + *END**************************************************************************/ +static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) +{ + MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ + + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const mcg_config_t mcgConfig_BOARD_BootClockRUN = + { + .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ + .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ + .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ + .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ + .drs = kMCG_DrsLow, /* Low frequency range */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ + .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ + .pll0Config = + { + .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ + .prdiv = 0xbU, /* PLL Reference divider: divided by 12 */ + .vdiv = 0x6U, /* VCO divider: multiplied by 30 */ + }, + }; +const sim_clock_config_t simConfig_BOARD_BootClockRUN = + { + .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ + .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ + .clkdiv1 = 0x1340000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /5 */ + }; +const osc_config_t oscConfig_BOARD_BootClockRUN = + { + .freq = 0U, /* Oscillator frequency: 0Hz */ + .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ + .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */ + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */ + .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ + } + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Set HSRUN power mode */ + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeHsrun(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) + { + } + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Configure RTC clock including enabling RTC oscillator. */ + CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_12PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); + /* Configure the Internal Reference clock (MCGIRCLK). */ + CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, + mcgConfig_BOARD_BootClockRUN.ircs, + mcgConfig_BOARD_BootClockRUN.fcrdiv); + /* Configure FLL external reference divider (FRDIV). */ + CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); + /* Set MCG to PEE mode. */ + CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, + kMCG_PllClkSelPll0, + &mcgConfig_BOARD_BootClockRUN.pll0Config); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; + /* Set RTC_CLKOUT source. */ + CLOCK_SetRtcClkOutClock(SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK); + /* Enable USB FS clock. */ + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcExt, SIM_USB_CLK_48000000HZ); + /* Set CLKOUT source. */ + CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK); + /* Set debug trace clock source. */ + CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK); +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockVLPR *********************** + ******************************************************************************/ + +/******************************************************************************* + * Variables for BOARD_BootClockVLPR configuration + ******************************************************************************/ +const mcg_config_t mcgConfig_BOARD_BootClockVLPR = + { + .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ + .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ + .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ + .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ + .drs = kMCG_DrsLow, /* Low frequency range */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ + .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ + .pll0Config = + { + .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ + .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */ + .vdiv = 0x0U, /* VCO divider: multiplied by 24 */ + }, + }; +const sim_clock_config_t simConfig_BOARD_BootClockVLPR = + { + .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */ + .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ + .clkdiv1 = 0x140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /5 */ + }; +const osc_config_t oscConfig_BOARD_BootClockVLPR = + { + .freq = 0U, /* Oscillator frequency: 0Hz */ + .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ + .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */ + .oscerConfig = + { + .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ + .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ + } + }; + +/******************************************************************************* + * Code for BOARD_BootClockVLPR configuration + ******************************************************************************/ +void BOARD_BootClockVLPR(void) +{ + /* Note: This function expects that the SLOW_IRCLK is trimmed to non-default + frequency 0Hz (default frequency: 32768Hz). */ + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Set MCG to BLPI mode. */ + CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, + mcgConfig_BOARD_BootClockVLPR.ircs, + mcgConfig_BOARD_BootClockVLPR.irclkEnableMode); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR); + /* Set VLPR power mode. */ + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + SMC_SetPowerModeVlpr(SMC, false); +#else + SMC_SetPowerModeVlpr(SMC); +#endif + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK; +} + diff --git a/right/include/board/clock_config.h b/right/include/board/clock_config.h index 7b1ca99..5e03fd4 100644 --- a/right/include/board/clock_config.h +++ b/right/include/board/clock_config.h @@ -1,54 +1,146 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 8000000U -#define BOARD_XTAL32K_CLK_HZ 32768U - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -void BOARD_BootClockVLPR(void); -void BOARD_BootClockRUN(void); -void BOARD_BootClockHSRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 8000000U /*!< Board xtal0 frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board RTC xtal frequency in Hz */ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */ + +/*! @brief MCG set for BOARD_BootClockRUN configuration. + */ +extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; +/*! @brief SIM module set for BOARD_BootClockRUN configuration. + */ +extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; +/*! @brief OSC set for BOARD_BootClockRUN configuration. + */ +extern const osc_config_t oscConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockVLPR *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockVLPR configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */ + +/*! @brief MCG set for BOARD_BootClockVLPR configuration. + */ +extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR; +/*! @brief SIM module set for BOARD_BootClockVLPR configuration. + */ +extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR; +/*! @brief OSC set for BOARD_BootClockVLPR configuration. + */ +extern const osc_config_t oscConfig_BOARD_BootClockVLPR; + +/******************************************************************************* + * API for BOARD_BootClockVLPR configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockVLPR(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockHSRUN ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */ + +/*! @brief MCG set for BOARD_BootClockHSRUN configuration. + */ +extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN; +/*! @brief SIM module set for BOARD_BootClockHSRUN configuration. + */ +extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN; +/*! @brief OSC set for BOARD_BootClockHSRUN configuration. + */ +extern const osc_config_t oscConfig_BOARD_BootClockHSRUN; + +/******************************************************************************* + * API for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockHSRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/right/main.c b/right/main.c index 029cff8..d650b67 100644 --- a/right/main.c +++ b/right/main.c @@ -8,7 +8,7 @@ void main(void) { BOARD_InitPins(); - BOARD_BootClockHSRUN(); + BOARD_BootClockRUN(); BOARD_InitDebugConsole(); i2c_master_config_t masterConfig;