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László Monda
2016-08-10 01:45:15 +02:00
commit e6c1fce5b4
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139
targets/MKS22F25612/src/bootloader_config.h Normal file
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/*
* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BOOTLOADER_CONFIG_H__
#define __BOOTLOADER_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//
// Bootloader configuration options
//
//! @name Peripheral configuration macros
//@{
#if !defined(BL_CONFIG_SCUART)
#define BL_CONFIG_SCUART (1)
#endif
#if !defined(BL_CONFIG_LPI2C)
#define BL_CONFIG_LPI2C (1)
#endif
#if !defined(BL_CONFIG_DSPI)
#define BL_CONFIG_DSPI (1)
#endif
#if !defined(BL_CONFIG_CAN)
#define BL_CONFIG_CAN (1)
#endif
#if !defined(BL_CONFIG_USB_HID)
#define BL_CONFIG_USB_HID (1)
#endif
#if !defined(BL_CONFIG_USB_MSC)
#define BL_CONFIG_USB_MSC (1)
#endif
//@}
#if !defined(BL_TARGET_FLASH) && !defined(BL_TARGET_RAM)
#define BL_TARGET_FLASH (1)
#endif
#if defined(BL_TARGET_RAM)
#define BL_FEATURE_FLASH_SECURITY (0)
#else
#define BL_FEATURE_FLASH_SECURITY (1)
#endif
#define BL_FEATURE_QSPI_MODULE (0)
#define BL_FEATURE_ENCRYPTION (0)
#define BL_FEATURE_CAN (BL_CONFIG_CAN)
// Bootloader peripheral detection default timeout in milliseconds
// After coming out of reset the bootloader will spin in a peripheral detection
// loop for this amount of time. A zero value means no time out.
#if DEBUG
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 0
#else
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 5000
#endif // DEBUG
#define BL_FEATURE_POWERDOWN (0)
// Bootloader powerdown timeout in milliseconds
// The bootloader enters a low power mode after waiting for this amount of time. A zero value means // no time out. Only
// applicable if BL_FEATURE_POWERDOWN is enabled.
#if DEBUG
#define BL_DEFAULT_POWERDOWN_TIMEOUT 10000
#else
#define BL_DEFAULT_POWERDOWN_TIMEOUT 600000
#endif // DEBUG
#if !defined(BL_TARGET_RAM)
#define BL_FEATURE_CRC_CHECK (1)
#endif
#define BL_FEATURE_UART_AUTOBAUD_IRQ (1)
// The bootloader will check this address for the application vector table upon startup.
#if !defined(BL_APP_VECTOR_TABLE_ADDRESS)
#define BL_APP_VECTOR_TABLE_ADDRESS 0xa000
#endif
/* Serial Port Info */
/**************************************************************************
* Note:
*
* Because of the changes to the UART modules, we can no longer define
* the TERM_PORT as a base pointer. The uart functions have been modified
* accommodate this change. Now, TERM_PORT_NUM must be defined as the
* number of the UART port desired to use
*
* TERM_PORT_NUM = 0 -- This allows you to use UART0; default pins are
* PTA14 and PTA15
*
* TERM_PORT_NUM = 1 -- This allows you to use UART1; default pins are
* PTC3 and PTC4
*
* TERM_PORT_NUM = 2 -- This allows you to use UART2; default pins are
* PTD2 and PTD3
*
*************************************************************************/
#define TERM_PORT_NUM 0
#define TERMINAL_BAUD 19200
#undef HW_FLOW_CONTROL
#endif // __BOOTLOADER_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKS22F25612/src/clock_config_KS22F25612.c Normal file
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/*
* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h"
#include "bootloader/bl_context.h"
#include "property/property.h"
#include "fsl_device_registers.h"
#include "utilities/fsl_assert.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
// Clock mode types
typedef enum _target_clock_mode
{
kClockMode_FEI = 0,
kClockMode_FEE = 1,
kClockMode_Default = kClockMode_FEI,
} target_clock_mode_t;
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
// This function implements clock mode switch between FEI and PEE mode used in this bootloader
void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode);
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
// See bootloader_common.h for documentation on this function.
void configure_clocks(bootloader_clock_option_t option)
{
#if defined(BL_TARGET_FLASH)
static target_clock_mode_t s_currentClockMode = kClockMode_FEI;
static uint32_t s_defaultClockDivider;
if (option == kClockOption_EnterBootloader)
{
s_defaultClockDivider = SIM->CLKDIV1;
// General procedure to be implemented:
// 1. Read clock flags and divider from bootloader config in property store
bootloader_configuration_data_t *config = &g_bootloaderContext.propertyInterface->store->configurationData;
uint8_t options = config->clockFlags;
// Check if the USB HID or CAN peripheral is enabled. If it is enabled, we always
// use the 48MHz IRC.
bool isUsbEnabled = config->enabledPeripherals & kPeripheralType_USB_HID;
bool isCanEnabled = config->enabledPeripherals & kPeripheralType_CAN;
// 2. Keep default clock if CAN, USB and HighSpeed Flag are not enabled.
if ((options & kClockFlag_HighSpeed) && (!isUsbEnabled) && (!isCanEnabled))
{
// Get actual Core clock.
SystemCoreClock =
kDefaultClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1);
// High speed flag is set (meaning disabled), so just use default clocks.
return;
}
// 3. Set OUTDIV1 based on divider in config. OUTDIV4 starts out at /1.
// The divider values are masked by the maximum bits per divider.
uint32_t div1 = ((~config->clockDivider) & (SIM_CLKDIV1_OUTDIV1_MASK >> SIM_CLKDIV1_OUTDIV1_SHIFT)) + 1;
// 4. Get MCGOUTCLK
uint32_t McgOutClk = kHIRC;
// If USB is enabled, the CPU clock must not be allowed to go below 20 MHz
if (isUsbEnabled || isCanEnabled)
{
div1 = 1;
}
uint32_t div2 = div1;
uint32_t div4 = (div1 < 2) ? 2 : div1;
// 6. Now set the dividers
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(div1 - 1) | SIM_CLKDIV1_OUTDIV2(div2 - 1) |
SIM_CLKDIV1_OUTDIV4(div4 - 1); /* Update system prescalers */
// 7. Update SystemCoreClock global.
SystemCoreClock = McgOutClk / div1;
clock_mode_switch(s_currentClockMode, kClockMode_FEE);
s_currentClockMode = kClockMode_FEE;
}
else if (option == kClockOption_ExitBootloader)
{
// Restore from FEE mode to FEI mode
clock_mode_switch(s_currentClockMode, kClockMode_FEI);
// Restore clock divider
SIM->CLKDIV1 = s_defaultClockDivider;
}
#endif // BL_TARGET_FLASH
}
void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode)
{
// Note: here only implements clock switch between FEI and FEE,
// The other modes are not supported.
assert(currentMode == kClockMode_FEE || currentMode == kClockMode_FEI);
assert(expectedMode == kClockMode_FEE || expectedMode == kClockMode_FEI);
if (currentMode == expectedMode)
{
return;
}
if (expectedMode == kClockMode_FEE)
{
/* Switch to FEE mode */
MCG->C7 = 2; // Select IRC48M as OSC
// Wait about 50us until the OSCSEL switch completes.
for (volatile uint32_t delayCnt = 0; delayCnt < 2000; delayCnt++)
{
__ASM("nop");
}
/* CLKS=0, FRDIV=6, IREFS=0, IRCLKEN=0, IREFSTEN=0 */
MCG->C1 = 0x30u;
// Wait until external reference clock is ready.
while ((MCG->S & MCG_S_IREFST_MASK) == MCG_S_IREFST_MASK)
{
}
// Multiply with 1280, MCGOUTCLK is 48Mhz
uint8_t c4_val;
c4_val = MCG->C4;
c4_val &= (uint8_t) ~(MCG_C4_DRST_DRS_MASK | MCG_C4_DMX32_MASK);
c4_val |= MCG_C4_DRST_DRS(1);
MCG->C4 = c4_val;
// Wait about 1ms until the clock frequency is stable.
for (volatile uint32_t delayCnt = 0; delayCnt < 16000; delayCnt++)
{
__ASM("nop");
}
}
else if (expectedMode == kClockMode_FEI)
{
MCG->C1 |= MCG_C1_IREFS_MASK; // Switch to internal reference clock.
// Wait until Internal reference clock is ready.
while ((MCG->S & MCG_S_IREFST_MASK) != MCG_S_IREFST_MASK)
{
}
// Restore C7 to default
MCG->C7 = 0;
// Wait about 50us until the OSCSEL switch completes.
for (volatile uint32_t delayCnt = 0; delayCnt < 2000; delayCnt++)
{
__ASM("nop");
}
// Restore Registers to default.
MCG->C1 = 0x04;
MCG->C4 &= (uint8_t) ~(MCG_C4_DRST_DRS_MASK);
// Wait about 1ms until the clock frequency is stable.
for (volatile uint32_t delayCnt = 0; delayCnt < 16000; delayCnt++)
{
__ASM("nop");
}
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKS22F25612/src/hardware_init_KS22F25612.c Normal file
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/*
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h"
#include "bootloader/bl_context.h"
#include "fsl_device_registers.h"
#include "utilities/kinetis_family.h"
#include "smc/smc.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
#define BOOT_PIN_NUMBER 12
#define BOOT_PIN_PORT PORTC
#define BOOT_PIN_GPIO GPIOC
#define BOOT_PIN_ALT_MODE 1
#define BOOT_PIN_DEBOUNCE_READ_COUNT 500
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void init_hardware(void)
{
exit_vlpr();
// Enable all the ports
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
SIM_SCGC5_PORTE_MASK);
// set PLLFLLSEL to select the IRC48M for this clock source
// set LPI2C0SRC to select the IRC48M for LPI2C0 clock source
uint32_t sopt2_val;
sopt2_val = SIM->SOPT2;
sopt2_val &= (uint32_t) ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_LPI2C0SRC_MASK);
sopt2_val |= (SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_LPI2C0SRC(1));
SIM->SOPT2 = sopt2_val;
}
void deinit_hardware(void)
{
SIM->SCGC5 &= (uint32_t) ~(SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
// Restore SIM_SOPTx related bits being changed
SIM->SOPT2 &= (uint32_t) ~(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_LPI2C0SRC_MASK);
}
bool usb_clock_init(void)
{
// Enable USB-OTG IP clocking
SIM->SCGC4 |= (SIM_SCGC4_USBOTG_MASK);
// If clock of usb module cannot be enabled, return false
if (!(SIM->SCGC4 & SIM_SCGC4_USBOTG_MASK))
{
return false;
}
// Reset the USB peripheral, this must be done here instead of USB driver due to silicon errata
// for at least KL25 and K22
USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
while (USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK)
;
// Select IRC48M clock, SIM_SOPT2_USBSRC_MASK selects internal clock,
// 0x30000 = SIM_SOPT2_PLLFLLSEL_MASK, selects IRC48MHz clock
SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
// need to set the clock_recover_en and irc_en register
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
return true;
}
uint32_t get_bus_clock(void)
{
uint32_t busClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1;
return (SystemCoreClock / busClockDivider);
}
uint32_t get_uart_clock(uint32_t instance)
{
switch (instance)
{
case 0:
case 1:
// UART0 and UART1 always use the system clock
return SystemCoreClock;
default:
return 0;
}
}
bool is_boot_pin_asserted(void)
{
#ifdef BL_TARGET_FLASH
// Initialize boot pin for GPIO
BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= PORT_PCR_MUX(BOOT_PIN_ALT_MODE);
// Set boot pin as an input
BOOT_PIN_GPIO->PDDR &= (uint32_t) ~(1 << BOOT_PIN_NUMBER);
// Set boot pin pullup enabled, pullup select, filter enable
BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_PFE_MASK);
uint32_t readCount = 0;
// Sample the pin a number of times
for (uint32_t i = 0; i < BOOT_PIN_DEBOUNCE_READ_COUNT; i++)
{
readCount += ((BOOT_PIN_GPIO->PDIR) >> BOOT_PIN_NUMBER) & 1;
}
// boot pin is pulled high so we are measuring lows, make sure most of our measurements
// registered as low
return (readCount < (BOOT_PIN_DEBOUNCE_READ_COUNT / 2));
#else
// Boot pin for Flash only target
return false;
#endif
}
void debug_init(void)
{
}
#if __ICCARM__
size_t __write(int handle, const unsigned char *buf, size_t size)
{
return size;
}
#endif // __ICCARM__
void update_available_peripherals()
{
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKS22F25612/src/memory_map_KS22F25612.c Normal file
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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "memory/memory.h"
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
//! @brief Memory map for KS22F256
//!
//! This map is not const because it is updated at runtime with the actual sizes of
//! flash and RAM for the chip we're running on.
memory_map_entry_t g_memoryMap[] = {
{ 0x00000000, 0x0003ffff, kMemoryIsExecutable, &g_flashMemoryInterface }, // Flash array (256KB)
{ 0x1fffc000, 0x2000bfff, kMemoryIsExecutable, &g_normalMemoryInterface }, // SRAM (64KB)
{ 0x40000000, 0x4007ffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS peripherals
{ 0x400ff000, 0x400fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // GPIO
{ 0xe0000000, 0xe00fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // M4 private peripherals
{ 0 } // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKS22F25612/src/peripherals_KS22F25612.c Normal file
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/*
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "bootloader/bl_peripheral_interface.h"
#include "packet/serial_packet.h"
extern void uart_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void i2c_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void spi_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void can_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
#if !BL_CONFIG_SCUART && !BL_CONFIG_LPI2C && !BL_CONFIG_DSPI && !BL_CONFIG_CAN && !BL_CONFIG_USB_HID
#error At least one peripheral must be enabled!
#endif
//! @brief Peripheral array for KS22F5256.
const peripheral_descriptor_t g_peripherals[] = {
#if BL_CONFIG_SCUART
// UART1
{.typeMask = kPeripheralType_UART,
.instance = 1,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_scuartControlInterface,
.byteInterface = &g_scuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_SCUART
#if BL_CONFIG_LPI2C
// LPI2C0
{.typeMask = kPeripheralType_I2CSlave,
.instance = 0,
.pinmuxConfig = i2c_pinmux_config,
.controlInterface = &g_lpi2cControlInterface,
.byteInterface = &g_lpi2cByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPI2C
#if BL_CONFIG_DSPI
// SPI1
{.typeMask = kPeripheralType_SPISlave,
.instance = 1,
.pinmuxConfig = spi_pinmux_config,
.controlInterface = &g_dspiControlInterface,
.byteInterface = &g_dspiByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_DSPI
#if BL_CONFIG_CAN
// CAN0
{.typeMask = kPeripheralType_CAN,
.instance = 0,
.pinmuxConfig = can_pinmux_config,
.controlInterface = &g_flexcanControlInterface,
.byteInterface = &g_flexcanByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_CAN
#if BL_CONFIG_USB_HID
// USB HID
{.typeMask = kPeripheralType_USB_HID,
.instance = 0,
.pinmuxConfig = NULL,
.controlInterface = &g_usbHidControlInterface,
.byteInterface = NULL,
.packetInterface = &g_usbHidPacketInterface },
#endif // BL_CONFIG_USB_HID
{ 0 } // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKS22F25612/src/peripherals_pinmux.h Normal file
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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! peripheral enable configurations
#define BL_ENABLE_PINMUX_UART1 (BL_CONFIG_SCUART)
#define BL_ENABLE_PINMUX_SPI1 (BL_CONFIG_DSPI)
#define BL_ENABLE_PINMUX_I2C0 (BL_CONFIG_LPI2C)
#define BL_ENABLE_PINMUX_CAN0 (BL_CONFIG_CAN)
//! UART pinmux configurations
#define UART1_RX_PORT_BASE PORTE
#define UART1_RX_GPIO_BASE GPIOE
#define UART1_RX_GPIO_PIN_NUM 1 // PTE1
#define UART1_RX_FUNC_ALT_MODE 3 // ALT mode for UART1 RX functionality
#define UART1_RX_GPIO_ALT_MODE 1 // ALT mdoe for GPIO functionality
#define UART1_RX_GPIO_IRQn PORTE_IRQn
#define UART1_RX_GPIO_IRQHandler PORTE_IRQHandler
#define UART1_TX_PORT_BASE PORTE
#define UART1_TX_GPIO_PIN_NUM 0 // PTE0
#define UART1_TX_FUNC_ALT_MODE 3 // ALT mode for UART1 TX functionality
//! I2C pinmux configurations
#define I2C0_SCL_PORT_BASE PORTB
#define I2C0_SCL_GPIO_PIN_NUM 0 // PTB0
#define I2C0_SCL_FUNC_ALT_MODE 2 // ALT mode for I2C0 SCL functionality
#define I2C0_SDA_PORT_BASE PORTB
#define I2C0_SDA_GPIO_PIN_NUM 1 // PTB1
#define I2C0_SDA_FUNC_ALT_MODE 2 // ALT mode for I2C0 SDA functionality
//! SPI pinmux configurations
#define SPI1_PCS_PORT_BASE PORTD
#define SPI1_PCS_GPIO_PIN_NUM 4 // PTD4
#define SPI1_PCS_FUNC_ALT_MODE 7 // ALT mode for SPI1 PCS functionality
#define SPI1_SCK_PORT_BASE PORTD
#define SPI1_SCK_GPIO_PIN_NUM 5 // PTD5
#define SPI1_SCK_FUNC_ALT_MODE 7 // ALT mode for SPI1 SCK functionality
#define SPI1_SOUT_PORT_BASE PORTD
#define SPI1_SOUT_GPIO_PIN_NUM 6 // PTD6
#define SPI1_SOUT_FUNC_ALT_MODE 7 // ALT mode for SPI1 SOUT functionality
#define SPI1_SIN_PORT_BASE PORTD
#define SPI1_SIN_GPIO_PIN_NUM 7 // PTD7
#define SPI1_SIN_FUNC_ALT_MODE 7 // ALT mode for SPI1 SIN functionality
//! CAN pinmux configurations
#define CAN0_RX_PORT_BASE PORTB
#define CAN0_RX_GPIO_PIN_NUM 19 // PIN 19 in the GPIOB group
#define CAN0_RX_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for CAN0 RX
#define CAN0_TX_PORT_BASE PORTB
#define CAN0_TX_GPIO_PIN_NUM 18 // PIN 18 in the GPIOB group
#define CAN0_TX_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for CAN0 TX
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/* ---------------------------------------------------------------------------------------*/
/* @file: startup_MKS22F25612.s */
/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
/* MKS22F25612 */
/* @version: 1.0 */
/* @date: 2015-6-23 */
/* @build: b150820 */
/* ---------------------------------------------------------------------------------------*/
/* */
/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without modification, */
/* are permitted provided that the following conditions are met: */
/* */
/* o Redistributions of source code must retain the above copyright notice, this list */
/* of conditions and the following disclaimer. */
/* */
/* o Redistributions in binary form must reproduce the above copyright notice, this */
/* list of conditions and the following disclaimer in the documentation and/or */
/* other materials provided with the distribution. */
/* */
/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
/* contributors may be used to endorse or promote products derived from this */
/* software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */
/*****************************************************************************/
/* Vector Table */
.section ".cs3.interrupt_vector"
.globl __cs3_interrupt_vector_cortex_m
.type __cs3_interrupt_vector_cortex_m, %object
__cs3_interrupt_vector_cortex_m:
.long __cs3_stack /* Top of Stack */
.long __cs3_reset /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/
.long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/
.long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/
.long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/
.long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/
.long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/
.long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/
.long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/
.long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/
.long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/
.long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/
.long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/
.long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/
.long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/
.long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/
.long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/
.long DMA_Error_IRQHandler /* DMA Error Interrupt*/
.long MCM_IRQHandler /* Normal Interrupt*/
.long FTF_IRQHandler /* FTFA Command complete interrupt*/
.long Read_Collision_IRQHandler /* Read Collision Interrupt*/
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
.long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/
.long WDOG_EWM_IRQHandler /* WDOG Interrupt*/
.long RNG_IRQHandler /* RNG Interrupt*/
.long LPI2C0_IRQHandler /* LPI2C0 interrupt*/
.long LPI2C1_IRQHandler /* LPI2C1 interrupt*/
.long SPI0_IRQHandler /* SPI0 Interrupt*/
.long SPI1_IRQHandler /* SPI1 Interrupt*/
.long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
.long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
.long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/
.long UART0_RX_TX_IRQHandler /* UART0 Status Sources interrupt*/
.long UART0_ERR_IRQHandler /* UART0 Error Sources interrupt*/
.long UART1_RX_TX_IRQHandler /* UART1 Status Sources interrupt*/
.long UART1_ERR_IRQHandler /* UART1 Error Sources interrupt*/
.long UART2_RX_TX_IRQHandler /* UART2 Status Sources interrupt*/
.long UART2_ERR_IRQHandler /* UART2 Error Sources interrupt*/
.long Reserved53_IRQHandler /* Reserved interrupt 53*/
.long Reserved54_IRQHandler /* Reserved interrupt 54*/
.long ADC0_IRQHandler /* ADC0 interrupt*/
.long CMP0_IRQHandler /* CMP0 interrupt*/
.long Reserved57_IRQHandler /* Reserved interrupt 57*/
.long TPM0_IRQHandler /* TPM0 Timer Overflow and Channels interrupt*/
.long TPM1_IRQHandler /* TPM1 Timer Overflow and Channels interrupt*/
.long TPM2_IRQHandler /* TPM2 Timer Overflow and Channels interrupt*/
.long Reserved61_IRQHandler /* Reserved interrupt 61*/
.long RTC_IRQHandler /* RTC alarm interrupt*/
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
.long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
.long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
.long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
.long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
.long PDB0_IRQHandler /* PDB0 Interrupt*/
.long USB0_IRQHandler /* USB0 interrupt*/
.long Reserved70_IRQHandler /* Reserved interrupt 70*/
.long Reserved71_IRQHandler /* Reserved interrupt 71*/
.long DAC0_IRQHandler /* DAC0 interrupt*/
.long MCG_IRQHandler /* MCG Interrupt*/
.long LPTMR0_IRQHandler /* LPTimer interrupt*/
.long PORTA_IRQHandler /* Port A interrupt*/
.long PORTB_IRQHandler /* Port B interrupt*/
.long PORTC_IRQHandler /* Port C interrupt*/
.long PORTD_IRQHandler /* Port D interrupt*/
.long PORTE_IRQHandler /* Port E interrupt*/
.long SWI_IRQHandler /* Software interrupt*/
.long Reserved81_IRQHandler /* Reserved interrupt 81*/
.long Reserved82_IRQHandler /* Reserved interrupt 82*/
.long Reserved83_IRQHandler /* Reserved interrupt 83*/
.long Reserved84_IRQHandler /* Reserved interrupt 84*/
.long Reserved85_IRQHandler /* Reserved interrupt 85*/
.long FLEXIO_IRQHandler /* Flexible IO interrupt*/
.long Reserved87_IRQHandler /* Reserved interrupt 87*/
.long Reserved88_IRQHandler /* Reserved interrupt 88*/
.long Reserved89_IRQHandler /* Reserved interrupt 89*/
.long Reserved90_IRQHandler /* Reserved Interrupt 90*/
.long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/
.long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/
.long CAN0_Error_IRQHandler /* CAN0 error interrupt*/
.long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/
.long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/
.long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/
.long Reserved97_IRQHandler /* Reserved Interrupt 97*/
.long Reserved98_IRQHandler /* Reserved Interrupt 98*/
.long Reserved99_IRQHandler /* Reserved Interrupt 99*/
.long Reserved100_IRQHandler /* Reserved Interrupt 100*/
.long Reserved101_IRQHandler /* Reserved Interrupt 101*/
.long Reserved102_IRQHandler /* Reserved Interrupt 102*/
.long Reserved103_IRQHandler /* Reserved Interrupt 103*/
.long I2S1_Tx_IRQHandler /* I2S1 transmit interrupt*/
.long I2S1_Rx_IRQHandler /* I2S1 receive interrupt*/
.long Reserved106_IRQHandler /* Reserved Interrupt 106*/
.long Reserved107_IRQHandler /* Reserved Interrupt 107*/
.long Reserved108_IRQHandler /* Reserved Interrupt 108*/
.long Reserved109_IRQHandler /* Reserved Interrupt 109*/
.long CAN1_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/
.long CAN1_Bus_Off_IRQHandler /* CAN1 bus off interrupt*/
.long CAN1_Error_IRQHandler /* CAN1 error interrupt*/
.long CAN1_Tx_Warning_IRQHandler /* CAN1 Tx warning interrupt*/
.long CAN1_Rx_Warning_IRQHandler /* CAN1 Rx warning interrupt*/
.long CAN1_Wake_Up_IRQHandler /* CAN1 wake up interrupt*/
.long DefaultISR /* 116*/
.long DefaultISR /* 117*/
.long DefaultISR /* 118*/
.long DefaultISR /* 119*/
.long DefaultISR /* 120*/
.long DefaultISR /* 121*/
.long DefaultISR /* 122*/
.long DefaultISR /* 123*/
.long DefaultISR /* 124*/
.long DefaultISR /* 125*/
.long DefaultISR /* 126*/
.long DefaultISR /* 127*/
.long DefaultISR /* 128*/
.long DefaultISR /* 129*/
.long DefaultISR /* 130*/
.long DefaultISR /* 131*/
.long DefaultISR /* 132*/
.long DefaultISR /* 133*/
.long DefaultISR /* 134*/
.long DefaultISR /* 135*/
.long DefaultISR /* 136*/
.long DefaultISR /* 137*/
.long DefaultISR /* 138*/
.long DefaultISR /* 139*/
.long DefaultISR /* 140*/
.long DefaultISR /* 141*/
.long DefaultISR /* 142*/
.long DefaultISR /* 143*/
.long DefaultISR /* 144*/
.long DefaultISR /* 145*/
.long DefaultISR /* 146*/
.long DefaultISR /* 147*/
.long DefaultISR /* 148*/
.long DefaultISR /* 149*/
.long DefaultISR /* 150*/
.long DefaultISR /* 151*/
.long DefaultISR /* 152*/
.long DefaultISR /* 153*/
.long DefaultISR /* 154*/
.long DefaultISR /* 155*/
.long DefaultISR /* 156*/
.long DefaultISR /* 157*/
.long DefaultISR /* 158*/
.long DefaultISR /* 159*/
.long DefaultISR /* 160*/
.long DefaultISR /* 161*/
.long DefaultISR /* 162*/
.long DefaultISR /* 163*/
.long DefaultISR /* 164*/
.long DefaultISR /* 165*/
.long DefaultISR /* 166*/
.long DefaultISR /* 167*/
.long DefaultISR /* 168*/
.long DefaultISR /* 169*/
.long DefaultISR /* 170*/
.long DefaultISR /* 171*/
.long DefaultISR /* 172*/
.long DefaultISR /* 173*/
.long DefaultISR /* 174*/
.long DefaultISR /* 175*/
.long DefaultISR /* 176*/
.long DefaultISR /* 177*/
.long DefaultISR /* 178*/
.long DefaultISR /* 179*/
.long DefaultISR /* 180*/
.long DefaultISR /* 181*/
.long DefaultISR /* 182*/
.long DefaultISR /* 183*/
.long DefaultISR /* 184*/
.long DefaultISR /* 185*/
.long DefaultISR /* 186*/
.long DefaultISR /* 187*/
.long DefaultISR /* 188*/
.long DefaultISR /* 189*/
.long DefaultISR /* 190*/
.long DefaultISR /* 191*/
.long DefaultISR /* 192*/
.long DefaultISR /* 193*/
.long DefaultISR /* 194*/
.long DefaultISR /* 195*/
.long DefaultISR /* 196*/
.long DefaultISR /* 197*/
.long DefaultISR /* 198*/
.long DefaultISR /* 199*/
.long DefaultISR /* 200*/
.long DefaultISR /* 201*/
.long DefaultISR /* 202*/
.long DefaultISR /* 203*/
.long DefaultISR /* 204*/
.long DefaultISR /* 205*/
.long DefaultISR /* 206*/
.long DefaultISR /* 207*/
.long DefaultISR /* 208*/
.long DefaultISR /* 209*/
.long DefaultISR /* 210*/
.long DefaultISR /* 211*/
.long DefaultISR /* 212*/
.long DefaultISR /* 213*/
.long DefaultISR /* 214*/
.long DefaultISR /* 215*/
.long DefaultISR /* 216*/
.long DefaultISR /* 217*/
.long DefaultISR /* 218*/
.long DefaultISR /* 219*/
.long DefaultISR /* 220*/
.long DefaultISR /* 221*/
.long DefaultISR /* 222*/
.long DefaultISR /* 223*/
.long DefaultISR /* 224*/
.long DefaultISR /* 225*/
.long DefaultISR /* 226*/
.long DefaultISR /* 227*/
.long DefaultISR /* 228*/
.long DefaultISR /* 229*/
.long DefaultISR /* 230*/
.long DefaultISR /* 231*/
.long DefaultISR /* 232*/
.long DefaultISR /* 233*/
.long DefaultISR /* 234*/
.long DefaultISR /* 235*/
.long DefaultISR /* 236*/
.long DefaultISR /* 237*/
.long DefaultISR /* 238*/
.long DefaultISR /* 239*/
.long DefaultISR /* 240*/
.long DefaultISR /* 241*/
.long DefaultISR /* 242*/
.long DefaultISR /* 243*/
.long DefaultISR /* 244*/
.long DefaultISR /* 245*/
.long DefaultISR /* 246*/
.long DefaultISR /* 247*/
.long DefaultISR /* 248*/
.long DefaultISR /* 249*/
.long DefaultISR /* 250*/
.long DefaultISR /* 251*/
.long DefaultISR /* 252*/
.long DefaultISR /* 253*/
.long DefaultISR /* 254*/
.long 0xFFFFFFFF /* Reserved for user TRIM value*/
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
/* Flash Configuration */
.section .FlashConfig
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFE
.thumb
/* Reset Handler */
.section .cs3.reset,"x",%progbits
.thumb_func
.globl __cs3_reset_cortex_m
.type __cs3_reset_cortex_m, %function
__cs3_reset_cortex_m:
.fnstart
LDR R0, =SystemInit
BLX R0
LDR R0, =init_data_bss
BLX R0
LDR R0,=_start
BX R0
.pool
.cantunwind
.fnend
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
.section ".text"
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
B DefaultISR
.size DefaultISR, . - DefaultISR
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler DMA4_IRQHandler
def_irq_handler DMA5_IRQHandler
def_irq_handler DMA6_IRQHandler
def_irq_handler DMA7_IRQHandler
def_irq_handler DMA8_IRQHandler
def_irq_handler DMA9_IRQHandler
def_irq_handler DMA10_IRQHandler
def_irq_handler DMA11_IRQHandler
def_irq_handler DMA12_IRQHandler
def_irq_handler DMA13_IRQHandler
def_irq_handler DMA14_IRQHandler
def_irq_handler DMA15_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler MCM_IRQHandler
def_irq_handler FTF_IRQHandler
def_irq_handler Read_Collision_IRQHandler
def_irq_handler LVD_LVW_IRQHandler
def_irq_handler LLWU_IRQHandler
def_irq_handler WDOG_EWM_IRQHandler
def_irq_handler RNG_IRQHandler
def_irq_handler LPI2C0_IRQHandler
def_irq_handler LPI2C1_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler I2S0_Tx_IRQHandler
def_irq_handler I2S0_Rx_IRQHandler
def_irq_handler LPUART0_IRQHandler
def_irq_handler UART0_RX_TX_IRQHandler
def_irq_handler UART0_ERR_IRQHandler
def_irq_handler UART1_RX_TX_IRQHandler
def_irq_handler UART1_ERR_IRQHandler
def_irq_handler UART2_RX_TX_IRQHandler
def_irq_handler UART2_ERR_IRQHandler
def_irq_handler Reserved53_IRQHandler
def_irq_handler Reserved54_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler Reserved57_IRQHandler
def_irq_handler TPM0_IRQHandler
def_irq_handler TPM1_IRQHandler
def_irq_handler TPM2_IRQHandler
def_irq_handler Reserved61_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler PIT0_IRQHandler
def_irq_handler PIT1_IRQHandler
def_irq_handler PIT2_IRQHandler
def_irq_handler PIT3_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler Reserved70_IRQHandler
def_irq_handler Reserved71_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler MCG_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler SWI_IRQHandler
def_irq_handler Reserved81_IRQHandler
def_irq_handler Reserved82_IRQHandler
def_irq_handler Reserved83_IRQHandler
def_irq_handler Reserved84_IRQHandler
def_irq_handler Reserved85_IRQHandler
def_irq_handler FLEXIO_IRQHandler
def_irq_handler Reserved87_IRQHandler
def_irq_handler Reserved88_IRQHandler
def_irq_handler Reserved89_IRQHandler
def_irq_handler Reserved90_IRQHandler
def_irq_handler CAN0_ORed_Message_buffer_IRQHandler
def_irq_handler CAN0_Bus_Off_IRQHandler
def_irq_handler CAN0_Error_IRQHandler
def_irq_handler CAN0_Tx_Warning_IRQHandler
def_irq_handler CAN0_Rx_Warning_IRQHandler
def_irq_handler CAN0_Wake_Up_IRQHandler
def_irq_handler Reserved97_IRQHandler
def_irq_handler Reserved98_IRQHandler
def_irq_handler Reserved99_IRQHandler
def_irq_handler Reserved100_IRQHandler
def_irq_handler Reserved101_IRQHandler
def_irq_handler Reserved102_IRQHandler
def_irq_handler Reserved103_IRQHandler
def_irq_handler I2S1_Tx_IRQHandler
def_irq_handler I2S1_Rx_IRQHandler
def_irq_handler Reserved106_IRQHandler
def_irq_handler Reserved107_IRQHandler
def_irq_handler Reserved108_IRQHandler
def_irq_handler Reserved109_IRQHandler
def_irq_handler CAN1_ORed_Message_buffer_IRQHandler
def_irq_handler CAN1_Bus_Off_IRQHandler
def_irq_handler CAN1_Error_IRQHandler
def_irq_handler CAN1_Tx_Warning_IRQHandler
def_irq_handler CAN1_Rx_Warning_IRQHandler
def_irq_handler CAN1_Wake_Up_IRQHandler

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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KS22P100M120SF0RM, Rev. 0, June 15, 2015
** Version: rev. 1.0, 2015-06-23
** Build: b150820
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2015-06-23)
** Initial version.
**
** ###################################################################
*/
/*!
* @file MKS22F25612
* @version 1.0
* @date 2015-06-23
* @brief Device specific configuration file for MKS22F25612 (implementation
* file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "fsl_device_registers.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit(void)
{
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if (DISABLE_WDOG)
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG->STCTRLH:
* ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
*/
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
#endif /* (DISABLE_WDOG) */
#ifdef CLOCK_SETUP
if ((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
{
if ((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
{
PMC->REGSC |=
PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
}
}
else
{
#ifdef SYSTEM_RTC_CR_VALUE
SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U)
{ /* Only if the OSCILLATOR is not already enabled */
RTC_CR = (uint32_t)((RTC_CR & (uint32_t) ~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK |
RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) |
(uint32_t)SYSTEM_RTC_CR_VALUE);
RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
RTC_CR &= (uint32_t) ~(uint32_t)RTC_CR_CLKO_MASK;
}
#endif
}
/* Power mode protection initialization */
#ifdef SYSTEM_SMC_PMPROT_VALUE
SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
#endif
/* High speed run mode enable */
#if (((SYSTEM_SMC_PMCTRL_VALUE)&SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
while (SMC->PMSTAT != 0x80U)
{ /* Wait until the system is in HSRUN mode */
}
#endif
/* System clock initialization */
/* Internal reference clock trim initialization */
#if defined(SLOW_TRIM_ADDRESS)
if (*((uint8_t *)SLOW_TRIM_ADDRESS) != 0xFFU)
{ /* Skip if non-volatile flash memory is erased */
MCG->C3 = *((uint8_t *)SLOW_TRIM_ADDRESS);
#endif /* defined(SLOW_TRIM_ADDRESS) */
#if defined(SLOW_FINE_TRIM_ADDRESS)
MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t *)SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
#endif
#if defined(FAST_TRIM_ADDRESS)
MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) | ((*((uint8_t *)FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
#endif
#if defined(FAST_FINE_TRIM_ADDRESS)
MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t *)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
#endif /* defined(FAST_FINE_TRIM_ADDRESS) */
#if defined(SLOW_TRIM_ADDRESS)
}
#endif /* defined(SLOW_TRIM_ADDRESS) */
/* Set system prescalers and clock sources */
SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) |
((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
SIM->SOPT2 =
((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) |
((SYSTEM_SIM_SOPT2_VALUE) &
(SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
/* Set MCG and OSC */
#if ((((SYSTEM_OSC_CR_VALUE)&OSC_CR_ERCLKEN_MASK) != 0x00U) || \
((((SYSTEM_MCG_C5_VALUE)&MCG_C5_PLLCLKEN0_MASK) != 0x00U) && \
(((SYSTEM_MCG_C7_VALUE)&MCG_C7_OSCSEL_MASK) == 0x00U)))
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
if (((SYSTEM_MCG_C2_VALUE)&MCG_C2_EREFS_MASK) != 0x00U)
{
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
}
#endif
MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable
etc.) */
/* Check that the source of the FLL reference clock is the requested one. */
if (((SYSTEM_MCG_C1_VALUE)&MCG_C1_IREFS_MASK) != 0x00U)
{
while ((MCG->S & MCG_S_IREFST_MASK) == 0x00U)
{
}
}
else
{
while ((MCG->S & MCG_S_IREFST_MASK) != 0x00U)
{
}
}
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) |
(SYSTEM_MCG_C2_VALUE &
(uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding
trim bits; low power bit is set later) */
MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) |
(MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
#if (MCG_MODE == MCG_MODE_BLPI)
/* BLPI specific */
MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
#endif
#else /* MCG_MODE */
/* Set MCG and OSC */
#if (((SYSTEM_OSC_CR_VALUE)&OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE)&MCG_C7_OSCSEL_MASK) == 0x00U)
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
if (((SYSTEM_MCG_C2_VALUE)&MCG_C2_EREFS_MASK) != 0x00U)
{
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
}
#endif
MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) |
(SYSTEM_MCG_C2_VALUE &
(uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding
trim bits; low power bit is set later) */
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
#if (MCG_MODE == MCG_MODE_PEE)
MCG->C1 =
(SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int.
reference enable etc.) - PBE mode*/
#else
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable
etc.) */
#endif
if ((((SYSTEM_MCG_C2_VALUE)&MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE)&MCG_C7_OSCSEL_MASK) == 0x00U))
{
while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U)
{ /* Check that the oscillator is running */
}
}
/* Check that the source of the FLL reference clock is the requested one. */
if (((SYSTEM_MCG_C1_VALUE)&MCG_C1_IREFS_MASK) != 0x00U)
{
while ((MCG->S & MCG_S_IREFST_MASK) == 0x00U)
{
}
}
else
{
while ((MCG->S & MCG_S_IREFST_MASK) != 0x00U)
{
}
}
MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) |
(MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
#endif /* MCG_MODE */
/* Common for all MCG modes */
/* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
MCG->C5 = (SYSTEM_MCG_C5_VALUE) &
(uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t) ~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
if ((SYSTEM_MCG_C5_VALUE)&MCG_C5_PLLCLKEN0_MASK)
{
MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
}
/* BLPE, PEE and PBE MCG mode specific */
#if (MCG_MODE == MCG_MODE_BLPE)
MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
#elif((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
while ((MCG->S & MCG_S_LOCK0_MASK) == 0x00U)
{ /* Wait until PLL is locked*/
}
#if (MCG_MODE == MCG_MODE_PEE)
MCG->C1 &= (uint8_t) ~(MCG_C1_CLKS_MASK);
#endif
#endif
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
while ((MCG->S & MCG_S_CLKST_MASK) != 0x00U)
{ /* Wait until output of the FLL is selected */
}
/* Use LPTMR to wait for 1ms for FLL clock stabilization */
SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* Alow software control of LPMTR */
LPTMR0->CMR = LPTMR_CMR_COMPARE(0); /* Default 1 LPO tick */
LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
LPTMR0->CSR = LPTMR_CSR_TEN_MASK; /* LPMTR enable */
while ((LPTMR0_CSR & LPTMR_CSR_TCF_MASK) == 0u)
{
}
LPTMR0_CSR = 0x00; /* Disable LPTMR */
SIM_SCGC5 &= (uint32_t) ~(uint32_t)SIM_SCGC5_LPTMR_MASK;
#elif((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
while ((MCG->S & MCG_S_CLKST_MASK) != 0x04U)
{ /* Wait until internal reference clock is selected as MCG output */
}
#elif((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
while ((MCG->S & MCG_S_CLKST_MASK) != 0x08U)
{ /* Wait until external reference clock is selected as MCG output */
}
#elif(MCG_MODE == MCG_MODE_PEE)
while ((MCG->S & MCG_S_CLKST_MASK) != 0x0CU)
{ /* Wait until output of the PLL is selected */
}
#endif
#if (((SYSTEM_SMC_PMCTRL_VALUE)&SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
while (SMC->PMSTAT != 0x04U)
{ /* Wait until the system is in VLPR mode */
}
#endif
#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) |
((SYSTEM_SIM_CLKDIV2_VALUE) &
(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
#endif
/* PLL loss of lock interrupt request initialization */
if (((SYSTEM_MCG_C6_VALUE)&MCG_C6_LOLIE0_MASK) != 0U)
{
NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
}
#endif
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate(void)
{
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint16_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
{
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
{
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
{
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
{
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
{
switch (MCG->C1 & MCG_C1_FRDIV_MASK)
{
case 0x38U:
Divider = 1536U;
break;
case 0x30U:
Divider = 1280U;
break;
default:
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
break;
}
}
else
{ /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
}
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
}
else
{ /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
{
case 0x00U:
MCGOUTClock *= 640U;
break;
case 0x20U:
MCGOUTClock *= 1280U;
break;
case 0x40U:
MCGOUTClock *= 1920U;
break;
case 0x60U:
MCGOUTClock *= 2560U;
break;
case 0x80U:
MCGOUTClock *= 732U;
break;
case 0xA0U:
MCGOUTClock *= 1464U;
break;
case 0xC0U:
MCGOUTClock *= 2197U;
break;
case 0xE0U:
MCGOUTClock *= 2929U;
break;
default:
break;
}
}
else
{ /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
/* PLL is selected */
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
}
else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
{
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
{
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
}
else
{ /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
}
else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
{
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
{
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
}
else
{ /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
SystemCoreClock =
(MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

70
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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__TARGET_CONFIG_H__)
#define __TARGET_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief Constants for clock frequencies.
enum _target_clocks
{
kDefaultClock = 20971520u,
kHIRC = 48000000u,
kMinCoreClockWithUsbSupport = 20000000u,
kMaxCoreClock = 120000000u,
kMaxBusClock = 60000000u,
kMaxFlashClock = 25000000u,
kDivider_Min = 1,
kDivider_Max = 16,
};
//! @brief Constants for sram partition
enum _sram_partition
{
kSram_LowerPart = 1,
kSram_UpperPart = 3,
};
//! @brief Version constants for the target.
enum _target_version_constants
{
kTarget_Version_Name = 'T',
kTarget_Version_Major = 1,
kTarget_Version_Minor = 0,
kTarget_Version_Bugfix = 0
};
#endif // __TARGET_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __USB_DEVICE_CONFIG_H__
#define __USB_DEVICE_CONFIG_H__ 1
#include "bootloader_common.h"
/*!
* @addtogroup usb_device_configuration
* @{
*/
/*!
* @name Hardware instance define
* @{
*/
/*! @brief KHCI instance count */
#define USB_DEVICE_CONFIG_KHCI (BL_CONFIG_USB_HID | BL_CONFIG_USB_MSC)
/*! @brief EHCI instance count */
#define USB_DEVICE_CONFIG_EHCI (0U)
/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/
#define USB_DEVICE_CONFIG_NUM (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI)
/* @} */
/*!
* @name class instance define
* @{
*/
/*! @brief HID instance count */
#define USB_DEVICE_CONFIG_HID (BL_CONFIG_USB_HID)
/*! @brief CDC ACM instance count */
#define USB_DEVICE_CONFIG_CDC_ACM (0U)
/*! @brief MSC instance count */
#define USB_DEVICE_CONFIG_MSC (BL_CONFIG_USB_MSC)
/*! @brief Audio instance count */
#define USB_DEVICE_CONFIG_AUDIO (0U)
/*! @brief PHDC instance count */
#define USB_DEVICE_CONFIG_PHDC (0U)
/*! @brief Video instance count */
#define USB_DEVICE_CONFIG_VIDEO (0U)
/*! @brief CCID instance count */
#define USB_DEVICE_CONFIG_CCID (0U)
/*! @brief Printer instance count */
#define USB_DEVICE_CONFIG_PRINTER (0U)
/*! @brief DFU instance count */
#define USB_DEVICE_CONFIG_DFU (0U)
/* @} */
/*! @brief Whether device is self power. 1 supported, 0 not supported */
#define USB_DEVICE_CONFIG_SELF_POWER (1U)
/*! @brief Whether device remote wakeup supported. 1 supported, 0 not supported */
#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
/*! @brief How many endpoints are supported in the stack. */
#define USB_DEVICE_CONFIG_ENDPOINTS (8U)
/*! @brief Whether the device task is enabled. */
#define USB_DEVICE_CONFIG_USE_TASK (0U)
/*! @brief How many the notification message are supported when the device task enabled. */
#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U)
#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
/*! @brief The MAX buffer length for the KHCI DMA workaround.*/
/* clang-format off */
#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U)
/*! @brief Whether handle the USB KHCI bus error. */
#define USB_DEVICE_CONFIG_KHCI_ERROR_HANDLING (0U)
/* clang-format on */
#endif
#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
/*! @brief How many the DTD are supported. */
/* clang-format off */
#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
/*! @brief Whether handle the USB EHCI bus error. */
#define USB_DEVICE_CONFIG_EHCI_ERROR_HANDLING (0U)
/*! @brief Whether test mode enabled. */
#define USB_DEVICE_CONFIG_EHCI_TEST_MODE (0U)
/*! @brief Whether the EHCI ID pin detect feature enabled. */
#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U)
/* clang-format on */
#endif
/*! @brief Whether the keep alive feature enabled. */
/* clang-format off */
#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U)
/*! @brief Whether the transfer buffer is cache-enabled or not. */
#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
/*! @brief Whether the low power mode is enabled or not. */
#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
/*! @brief Whether the device detached feature is enabled or not. */
#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
/* clang-format on */
/* @} */
#endif /* __USB_DEVICE_CONFIG_H__ */