463 lines
21 KiB
C
463 lines
21 KiB
C
/*
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** ###################################################################
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** GNU C Compiler - CodeSourcery Sourcery G++
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** IAR ANSI C/C++ Compiler for ARM
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**
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** Reference manual: KS22P100M120SF0RM, Rev. 0, June 15, 2015
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** Version: rev. 1.0, 2015-06-23
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** Build: b150820
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright (c) 2015 Freescale Semiconductor, Inc.
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 1.0 (2015-06-23)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file MKS22F25612
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* @version 1.0
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* @date 2015-06-23
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* @brief Device specific configuration file for MKS22F25612 (implementation
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* file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "fsl_device_registers.h"
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit(void)
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{
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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#if (DISABLE_WDOG)
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/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
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/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
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/* WDOG->STCTRLH:
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* ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
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*/
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WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
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WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
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#endif /* (DISABLE_WDOG) */
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#ifdef CLOCK_SETUP
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if ((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
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{
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if ((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
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{
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PMC->REGSC |=
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PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
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}
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}
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else
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{
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#ifdef SYSTEM_RTC_CR_VALUE
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SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
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if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U)
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{ /* Only if the OSCILLATOR is not already enabled */
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RTC_CR = (uint32_t)((RTC_CR & (uint32_t) ~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK |
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RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) |
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(uint32_t)SYSTEM_RTC_CR_VALUE);
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RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
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RTC_CR &= (uint32_t) ~(uint32_t)RTC_CR_CLKO_MASK;
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}
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#endif
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}
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/* Power mode protection initialization */
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#ifdef SYSTEM_SMC_PMPROT_VALUE
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SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
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#endif
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/* High speed run mode enable */
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#if (((SYSTEM_SMC_PMCTRL_VALUE)&SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
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SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
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while (SMC->PMSTAT != 0x80U)
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{ /* Wait until the system is in HSRUN mode */
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}
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#endif
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/* System clock initialization */
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/* Internal reference clock trim initialization */
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#if defined(SLOW_TRIM_ADDRESS)
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if (*((uint8_t *)SLOW_TRIM_ADDRESS) != 0xFFU)
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{ /* Skip if non-volatile flash memory is erased */
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MCG->C3 = *((uint8_t *)SLOW_TRIM_ADDRESS);
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#endif /* defined(SLOW_TRIM_ADDRESS) */
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#if defined(SLOW_FINE_TRIM_ADDRESS)
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MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t *)SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
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#endif
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#if defined(FAST_TRIM_ADDRESS)
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MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) | ((*((uint8_t *)FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
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#endif
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#if defined(FAST_FINE_TRIM_ADDRESS)
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MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t *)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
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#endif /* defined(FAST_FINE_TRIM_ADDRESS) */
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#if defined(SLOW_TRIM_ADDRESS)
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}
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#endif /* defined(SLOW_TRIM_ADDRESS) */
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/* Set system prescalers and clock sources */
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SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
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SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) |
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((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
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SIM->SOPT2 =
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((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) |
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((SYSTEM_SIM_SOPT2_VALUE) &
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(SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
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#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
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/* Set MCG and OSC */
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#if ((((SYSTEM_OSC_CR_VALUE)&OSC_CR_ERCLKEN_MASK) != 0x00U) || \
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((((SYSTEM_MCG_C5_VALUE)&MCG_C5_PLLCLKEN0_MASK) != 0x00U) && \
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(((SYSTEM_MCG_C7_VALUE)&MCG_C7_OSCSEL_MASK) == 0x00U)))
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/* SIM_SCGC5: PORTA=1 */
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SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
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/* PORTA_PCR18: ISF=0,MUX=0 */
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PORTA_PCR18 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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if (((SYSTEM_MCG_C2_VALUE)&MCG_C2_EREFS_MASK) != 0x00U)
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{
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/* PORTA_PCR19: ISF=0,MUX=0 */
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PORTA_PCR19 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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}
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#endif
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MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
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MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable
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etc.) */
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/* Check that the source of the FLL reference clock is the requested one. */
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if (((SYSTEM_MCG_C1_VALUE)&MCG_C1_IREFS_MASK) != 0x00U)
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{
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while ((MCG->S & MCG_S_IREFST_MASK) == 0x00U)
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{
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}
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}
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else
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{
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while ((MCG->S & MCG_S_IREFST_MASK) != 0x00U)
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{
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}
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}
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MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) |
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(SYSTEM_MCG_C2_VALUE &
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(uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding
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trim bits; low power bit is set later) */
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MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) |
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(MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
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OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
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MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
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#if (MCG_MODE == MCG_MODE_BLPI)
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/* BLPI specific */
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MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
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#endif
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#else /* MCG_MODE */
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/* Set MCG and OSC */
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#if (((SYSTEM_OSC_CR_VALUE)&OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE)&MCG_C7_OSCSEL_MASK) == 0x00U)
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/* SIM_SCGC5: PORTA=1 */
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SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
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/* PORTA_PCR18: ISF=0,MUX=0 */
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PORTA_PCR18 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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if (((SYSTEM_MCG_C2_VALUE)&MCG_C2_EREFS_MASK) != 0x00U)
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{
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/* PORTA_PCR19: ISF=0,MUX=0 */
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PORTA_PCR19 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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}
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#endif
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MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
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MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) |
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(SYSTEM_MCG_C2_VALUE &
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(uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding
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trim bits; low power bit is set later) */
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OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
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MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
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#if (MCG_MODE == MCG_MODE_PEE)
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MCG->C1 =
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(SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int.
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reference enable etc.) - PBE mode*/
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#else
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MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable
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etc.) */
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#endif
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if ((((SYSTEM_MCG_C2_VALUE)&MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE)&MCG_C7_OSCSEL_MASK) == 0x00U))
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{
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while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U)
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{ /* Check that the oscillator is running */
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}
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}
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/* Check that the source of the FLL reference clock is the requested one. */
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if (((SYSTEM_MCG_C1_VALUE)&MCG_C1_IREFS_MASK) != 0x00U)
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{
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while ((MCG->S & MCG_S_IREFST_MASK) == 0x00U)
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{
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}
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}
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else
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{
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while ((MCG->S & MCG_S_IREFST_MASK) != 0x00U)
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{
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}
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}
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MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) |
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(MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
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#endif /* MCG_MODE */
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/* Common for all MCG modes */
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/* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
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MCG->C5 = (SYSTEM_MCG_C5_VALUE) &
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(uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
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MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t) ~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
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if ((SYSTEM_MCG_C5_VALUE)&MCG_C5_PLLCLKEN0_MASK)
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{
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MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
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}
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/* BLPE, PEE and PBE MCG mode specific */
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#if (MCG_MODE == MCG_MODE_BLPE)
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MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
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#elif((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
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MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
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while ((MCG->S & MCG_S_LOCK0_MASK) == 0x00U)
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{ /* Wait until PLL is locked*/
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}
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#if (MCG_MODE == MCG_MODE_PEE)
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MCG->C1 &= (uint8_t) ~(MCG_C1_CLKS_MASK);
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#endif
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#endif
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#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
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while ((MCG->S & MCG_S_CLKST_MASK) != 0x00U)
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{ /* Wait until output of the FLL is selected */
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}
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/* Use LPTMR to wait for 1ms for FLL clock stabilization */
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SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* Alow software control of LPMTR */
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LPTMR0->CMR = LPTMR_CMR_COMPARE(0); /* Default 1 LPO tick */
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LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
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LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
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LPTMR0->CSR = LPTMR_CSR_TEN_MASK; /* LPMTR enable */
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while ((LPTMR0_CSR & LPTMR_CSR_TCF_MASK) == 0u)
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{
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}
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LPTMR0_CSR = 0x00; /* Disable LPTMR */
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SIM_SCGC5 &= (uint32_t) ~(uint32_t)SIM_SCGC5_LPTMR_MASK;
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#elif((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
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while ((MCG->S & MCG_S_CLKST_MASK) != 0x04U)
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{ /* Wait until internal reference clock is selected as MCG output */
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}
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#elif((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
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while ((MCG->S & MCG_S_CLKST_MASK) != 0x08U)
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{ /* Wait until external reference clock is selected as MCG output */
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}
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#elif(MCG_MODE == MCG_MODE_PEE)
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while ((MCG->S & MCG_S_CLKST_MASK) != 0x0CU)
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{ /* Wait until output of the PLL is selected */
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}
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#endif
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#if (((SYSTEM_SMC_PMCTRL_VALUE)&SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
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SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
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while (SMC->PMSTAT != 0x04U)
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{ /* Wait until the system is in VLPR mode */
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}
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#endif
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#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
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SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) |
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((SYSTEM_SIM_CLKDIV2_VALUE) &
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(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
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#endif
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/* PLL loss of lock interrupt request initialization */
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if (((SYSTEM_MCG_C6_VALUE)&MCG_C6_LOLIE0_MASK) != 0U)
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{
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NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
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}
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#endif
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate(void)
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{
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uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
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uint16_t Divider;
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if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
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{
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/* Output of FLL or PLL is selected */
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if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
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{
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/* FLL is selected */
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if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
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{
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/* External reference clock is selected */
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switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
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{
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case 0x00U:
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MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
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break;
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case 0x01U:
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MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
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break;
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case 0x02U:
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default:
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MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
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break;
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}
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if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
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{
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switch (MCG->C1 & MCG_C1_FRDIV_MASK)
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{
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case 0x38U:
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Divider = 1536U;
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break;
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case 0x30U:
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Divider = 1280U;
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break;
|
|
default:
|
|
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{ /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
|
|
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
|
}
|
|
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
|
}
|
|
else
|
|
{ /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
|
|
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
|
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
|
|
/* Select correct multiplier to calculate the MCG output clock */
|
|
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
|
|
{
|
|
case 0x00U:
|
|
MCGOUTClock *= 640U;
|
|
break;
|
|
case 0x20U:
|
|
MCGOUTClock *= 1280U;
|
|
break;
|
|
case 0x40U:
|
|
MCGOUTClock *= 1920U;
|
|
break;
|
|
case 0x60U:
|
|
MCGOUTClock *= 2560U;
|
|
break;
|
|
case 0x80U:
|
|
MCGOUTClock *= 732U;
|
|
break;
|
|
case 0xA0U:
|
|
MCGOUTClock *= 1464U;
|
|
break;
|
|
case 0xC0U:
|
|
MCGOUTClock *= 2197U;
|
|
break;
|
|
case 0xE0U:
|
|
MCGOUTClock *= 2929U;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{ /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
|
|
/* PLL is selected */
|
|
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
|
|
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
|
|
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
|
|
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
|
|
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
|
|
}
|
|
else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
|
|
{
|
|
/* Internal reference clock is selected */
|
|
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
|
|
{
|
|
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
|
}
|
|
else
|
|
{ /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
|
|
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
|
|
MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
|
|
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
|
|
}
|
|
else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
|
|
{
|
|
/* External reference clock is selected */
|
|
switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
|
|
{
|
|
case 0x00U:
|
|
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
|
break;
|
|
case 0x01U:
|
|
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
|
break;
|
|
case 0x02U:
|
|
default:
|
|
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{ /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
|
|
/* Reserved value */
|
|
return;
|
|
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
|
|
SystemCoreClock =
|
|
(MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
|
}
|