Add KBOOT.

src/drivers/common/fsl_common.c

@@ -0,0 +1,95 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#if !(defined(NODEBUG) || defined(NDEBUG))
+#if (defined(__CC_ARM)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __asm("bkpt #0");
+    }
+}
+#elif(defined(__GNUC__))
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __asm("bkpt #0");
+    }
+}
+#endif /* (defined(__CC_ARM)) ||  (defined (__ICCARM__)) */
+#endif /* !(defined(NODEBUG) || defined(NDEBUG)) */
+
+void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) */
+    uint32_t n;
+
+    __disable_irq();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    __enable_irq();
+}

src/drivers/common/fsl_common.h

@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#if !defined(BOOTLOADER_HOST)
+#include "fsl_device_registers.h"
+#endif // BOOTLOADER_HOST
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U   /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U   /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U  /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+#if !defined(BOOTLOADER_HOST)
+#include "fsl_clock.h"
+#endif // BOOTLOADER_HOST
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if !defined(BOOTLOADER_HOST)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void EnableIRQ(IRQn_Type interrupt)
+{
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+        NVIC_EnableIRQ(interrupt);
+    }
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void DisableIRQ(IRQn_Type interrupt)
+{
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+        NVIC_DisableIRQ(interrupt);
+    }
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+}
+
+/*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+    __set_PRIMASK(primask);
+}
+
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ */
+void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // BOOTLOADER_HOST
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */

src/drivers/crc/fsl_crc.c

@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_crc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT
+/* @brief Default user configuration structure for CRC-16-CCITT */
+#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U
+/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */
+#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
+/*< Default initial checksum */
+#define CRC_DRIVER_DEFAULT_REFLECT_IN false
+/*< Default is no transpose */
+#define CRC_DRIVER_DEFAULT_REFLECT_OUT false
+/*< Default is transpose bytes */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false
+/*< Default is without complement of CRC data register read data */
+#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16
+/*< Default is 16-bit CRC protocol */
+#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum
+/*< Default is resutl type is final checksum */
+#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */
+
+/*! @brief CRC type of transpose of read write data */
+typedef enum _crc_transpose_type
+{
+    kCrcTransposeNone = 0U,         /*! No transpose  */
+    kCrcTransposeBits = 1U,         /*! Tranpose bits in bytes  */
+    kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */
+    kCrcTransposeBytes = 3U,        /*! Transpose bytes */
+} crc_transpose_type_t;
+
+/*!
+* @brief CRC module configuration.
+*
+* This structure holds the configuration for the CRC module.
+*/
+typedef struct _crc_module_config
+{
+    uint32_t polynomial;                 /*!< CRC Polynomial, MSBit first.@n
+                                              Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
+    uint32_t seed;                       /*!< Starting checksum value */
+    crc_transpose_type_t readTranspose;  /*!< Type of transpose when reading CRC result. */
+    crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */
+    bool complementChecksum;             /*!< True if the result shall be complement of the actual checksum. */
+    crc_bits_t crcBits;                  /*!< Selects 16- or 32- bit CRC protocol. */
+} crc_module_config_t;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Returns transpose type for CRC protocol reflect in parameter.
+ *
+ * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter.
+ *
+ * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter.
+ */
+static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable)
+{
+    return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes);
+}
+
+/*!
+ * @brief Returns transpose type for CRC protocol reflect out parameter.
+ *
+ * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter.
+ *
+ * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter.
+ */
+static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enable)
+{
+    return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone);
+}
+
+/*!
+ * @brief Starts checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts the checksum computation by writing the seed value
+ *
+ * @param base CRC peripheral address.
+ * @param config Pointer to protocol configuration structure.
+ */
+static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
+{
+    uint32_t crcControl;
+
+    /* pre-compute value for CRC control registger based on user configuraton without WAS field */
+    crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) |
+                 CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits);
+
+    /* make sure the control register is clear - WAS is deasserted, and protocol is set */
+    base->CTRL = crcControl;
+
+    /* write polynomial register */
+    base->GPOLY = config->polynomial;
+
+    /* write pre-computed control register value along with WAS to start checksum computation */
+    base->CTRL = crcControl | CRC_CTRL_WAS(true);
+
+    /* write seed (initial checksum) */
+    base->DATA = config->seed;
+
+    /* deassert WAS by writing pre-computed CRC control register value */
+    base->CTRL = crcControl;
+}
+
+/*!
+ * @brief Starts final checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts final checksum computation by writing the seed value.
+ * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum
+ *       (output reflection and xor functions are applied).
+ *
+ * @param base CRC peripheral address.
+ * @param protocolConfig Pointer to protocol configuration structure.
+ */
+static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+{
+    crc_module_config_t moduleConfig;
+    /* convert protocol to CRC peripheral module configuration, prepare for final checksum */
+    moduleConfig.polynomial = protocolConfig->polynomial;
+    moduleConfig.seed = protocolConfig->seed;
+    moduleConfig.readTranspose = crc_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
+    moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.complementChecksum = protocolConfig->complementChecksum;
+    moduleConfig.crcBits = protocolConfig->crcBits;
+
+    crc_ConfigureAndStart(base, &moduleConfig);
+}
+
+/*!
+ * @brief Starts intermediate checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts intermediate checksum computation by writing the seed value.
+ * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value).
+ *
+ * @param base CRC peripheral address.
+ * @param protocolConfig Pointer to protocol configuration structure.
+ */
+static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+{
+    crc_module_config_t moduleConfig;
+    /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */
+    moduleConfig.polynomial = protocolConfig->polynomial;
+    moduleConfig.seed = protocolConfig->seed;
+    moduleConfig.readTranspose =
+        kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */
+    moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */
+    moduleConfig.crcBits = protocolConfig->crcBits;
+
+    crc_ConfigureAndStart(base, &moduleConfig);
+}
+
+void CRC_Init(CRC_Type *base, const crc_config_t *config)
+{
+    /* ungate clock */
+    CLOCK_EnableClock(kCLOCK_Crc0);
+    /* configure CRC module and write the seed */
+    if (config->crcResult == kCrcFinalChecksum)
+    {
+        crc_SetProtocolConfig(base, config);
+    }
+    else
+    {
+        crc_SetRawProtocolConfig(base, config);
+    }
+}
+
+void CRC_GetDefaultConfig(crc_config_t *config)
+{
+    static const crc_config_t crc16ccit = {
+        CRC_DRIVER_DEFAULT_POLYNOMIAL,          CRC_DRIVER_DEFAULT_SEED,
+        CRC_DRIVER_DEFAULT_REFLECT_IN,          CRC_DRIVER_DEFAULT_REFLECT_OUT,
+        CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS,
+        CRC_DRIVER_DEFAULT_CRC_RESULT,
+    };
+
+    *config = crc16ccit;
+}
+
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
+{
+    const uint32_t *data32;
+
+    /* 8-bit reads and writes till source address is aligned 4 bytes */
+    while ((dataSize) && ((uint32_t)data & 3U))
+    {
+        base->ACCESS8BIT.DATALL = *data;
+        data++;
+        dataSize--;
+    }
+
+    /* use 32-bit reads and writes as long as possible */
+    data32 = (const uint32_t *)data;
+    while (dataSize >= sizeof(uint32_t))
+    {
+        base->DATA = *data32;
+        data32++;
+        dataSize -= sizeof(uint32_t);
+    }
+
+    data = (const uint8_t *)data32;
+
+    /* 8-bit reads and writes till end of data buffer */
+    while (dataSize)
+    {
+        base->ACCESS8BIT.DATALL = *data;
+        data++;
+        dataSize--;
+    }
+}
+
+uint16_t CRC_Get16bitResult(CRC_Type *base)
+{
+    uint32_t retval;
+    uint32_t totr; /* type of transpose read bitfield */
+
+    retval = base->DATA;
+    totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT;
+
+    /* check transpose type to get 16-bit out of 32-bit register */
+    if (totr >= 2U)
+    {
+        /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */
+        retval &= 0xFFFF0000U;
+        retval = retval >> 16U;
+    }
+    else
+    {
+        /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */
+        retval &= 0x0000FFFFU;
+    }
+    return (uint16_t)retval;
+}

src/drivers/crc/fsl_crc.h

@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief CRC driver version. */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+
+/*! @brief Has data register with name CRC */
+#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
+#define DATA CRC
+#define DATALL CRCLL
+#endif
+
+/*! @brief Default configuration struct filled by CRC_GetDefaultConfig(). */
+#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
+#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
+#endif
+
+/*! @brief CRC bit width */
+typedef enum _crc_bits
+{
+    kCrcBits16 = 0U, /*! Generate 16-bit CRC code  */
+    kCrcBits32 = 1U  /*! Generate 32-bit CRC code  */
+} crc_bits_t;
+
+/*! @brief CRC result type */
+typedef enum _crc_result
+{
+    kCrcFinalChecksum = 0U,       /*! CRC data register read value is the final checksum.
+                                      Reflect out and final xor protocol features are applied. */
+    kCrcIntermediateChecksum = 1U /*! CRC data register read value is intermediate checksum (raw value).
+                                      Reflect out and final xor protocol feature are not applied.
+                                      Intermediate checksum can be used as a seed for CRC_Init()
+                                      to continue adding data to this checksum. */
+} crc_result_t;
+
+/*!
+* @brief CRC protocol configuration.
+*
+* This structure holds the configuration for the CRC protocol.
+*
+*/
+typedef struct _crc_config
+{
+    uint32_t polynomial;     /*!< CRC Polynomial, MSBit first.
+                                  Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
+    uint32_t seed;           /*!< Starting checksum value */
+    bool reflectIn;          /*!< Reflect bits on input. */
+    bool reflectOut;         /*!< Reflect bits on output. */
+    bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
+    crc_bits_t crcBits;      /*!< Selects 16- or 32- bit CRC protocol. */
+    crc_result_t crcResult;  /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or
+                                CRC_Get32bitResult() */
+} crc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable and configure the CRC peripheral module
+ *
+ * This functions enables the clock gate in the Kinetis SIM module for the CRC peripheral.
+ * It also configures the CRC module and starts checksum computation by writing the seed.
+ *
+ * @param base CRC peripheral address.
+ * @param config CRC module configuration structure
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config);
+
+/*!
+ * @brief Disable the CRC peripheral module
+ *
+ * This functions disables the clock gate in the Kinetis SIM module for the CRC peripheral.
+ *
+ * @param base CRC peripheral address.
+ */
+static inline void CRC_Deinit(CRC_Type *base)
+{
+    /* gate clock */
+    CLOCK_DisableClock(kCLOCK_Crc0);
+}
+
+/*!
+ * @brief Loads default values to CRC protocol configuration structure.
+ *
+ * Loads default values to CRC protocol configuration structure. The default values are:
+ * @code
+ *   config->polynomial = 0x1021;
+ *   config->seed = 0xFFFF;
+ *   config->reflectIn = false;
+ *   config->reflectOut = false;
+ *   config->complementChecksum = false;
+ *   config->crcBits = kCrcBits16;
+ *   config->crcResult = kCrcFinalChecksum;
+ * @endcode
+ *
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetDefaultConfig(crc_config_t *config);
+
+/*!
+ * @brief Write data to the CRC module.
+ *
+ * Writes input data buffer bytes to CRC data register.
+ * The configured type of transpose is applied.
+ *
+ * @param base CRC peripheral address.
+ * @param data Input data stream, MSByte in data[0].
+ * @param dataSize Size in bytes of the input data buffer.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
+
+/*!
+ * @brief Read 32-bit checksum from the CRC module.
+ *
+ * Reads CRC data register (intermediate or final checksum).
+ * The configured type of transpose and complement are applied.
+ *
+ * @param base CRC peripheral address.
+ * @return intermediate or final 32-bit checksum, after configured transpose and complement operations.
+ */
+static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->DATA;
+}
+
+/*!
+ * @brief Read 16-bit checksum from the CRC module.
+ *
+ * Reads CRC data register (intermediate or final checksum).
+ * The configured type of transpose and complement are applied.
+ *
+ * @param base CRC peripheral address.
+ * @return intermediate or final 16-bit checksum, after configured transpose and complement operations.
+ */
+uint16_t CRC_Get16bitResult(CRC_Type *base);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_CRC_H_ */

src/drivers/gpio/fsl_gpio.c

@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+
+/*!
+* @brief Gets the GPIO instance according to the GPIO base
+*
+* @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+* @retval GPIO instance
+*/
+static uint32_t GPIO_GetInstance(GPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t GPIO_GetInstance(GPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++)
+    {
+        if (s_gpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_GPIO_COUNT);
+
+    return instance;
+}
+
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1U << pin);
+    }
+    else
+    {
+        GPIO_WritePinOutput(base, pin, config->outputLogic);
+        base->PDDR |= (1U << pin);
+    }
+}
+
+uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+/*!
+* @brief Gets the FGPIO instance according to the GPIO base
+*
+* @param base    FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+* @retval FGPIO instance
+*/
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++)
+    {
+        if (s_fgpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT);
+
+    return instance;
+}
+
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1U << pin);
+    }
+    else
+    {
+        FGPIO_WritePinOutput(base, pin, config->outputLogic);
+        base->PDDR |= (1U << pin);
+    }
+}
+
+uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
+{
+    uint8_t instance;
+    instance = FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    instance = FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */

src/drivers/gpio/fsl_gpio.h

@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_GPIO_H_
+#define _FSL_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gpio_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief GPIO driver version. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+
+/*! @brief GPIO direction definition*/
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused
+ * Note : In some cases, the corresponding port property should be configured in advance
+ *        cwith the PORT_SetPinConfig()
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< gpio direction, input or output */
+    /* Output configurations, please ignore if configured as a input one */
+    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name configuration
+ * @{
+ */
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param pin    GPIO port pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+/* @} */
+
+/*!
+ * @name Output Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param pin     GPIO pin's number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low logic level.
+ *        - 1: corresponding pin output high logic level.
+ */
+static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1 << pin;
+    }
+    else
+    {
+        base->PSOR = 1 << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param mask GPIO pins' numbers macro
+ */
+static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param mask GPIO pins' numbers macro
+ */
+static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param mask GPIO pins' numbers macro
+ */
+static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/* @} */
+
+/*!
+ * @name Input Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param pin     GPIO pin's number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low logic level.
+ *        - 1: corresponding pin input high logic level.
+ */
+static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/* @} */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Reads whole GPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
+
+/*!
+ * @brief Clears multiple GPIO pins' interrupt status flag.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param mask GPIO pins' numbers macro
+ */
+void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name FGPIO Operation
+ *
+ * @note FGPIO (Fast GPIO) is only available in a few MCUs. FGPIO and GPIO share the same
+ *       peripheral but use different registers. FGPIO is closer to the core than the regular GPIO
+ *       and it's faster to read and write.
+ * @{
+ */
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*!
+ * @brief Introduce the FGPIO feature.
+ * The FGPIO features are only support on some of kinetis chips.
+ * The FGPIO registers are aliased to the IOPORT interface. Accesses via the IOPORT interface
+ * occur in parallel with any instruction fetches and will therefore complete in a single cycle. This aliased Fast GPIO
+ * memory map is called FGPIO.
+ */
+
+/*!
+ * @name Configuration
+ * @{
+ */
+
+/*!
+ * @brief Initializes a FGPIO pin used by the board.
+ *
+ * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file.
+ * Then, call the FGPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param pin    FGPIO port pin number
+ * @param config FGPIO pin configuration pointer
+ */
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/* @} */
+
+/*!
+ * @name Output Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
+ *
+ * @param base    FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param pin     FGPIO pin's number
+ * @param output  FGPIOpin output logic level.
+ *        - 0: corresponding pin output low logic level.
+ *        - 1: corresponding pin output high logic level.
+ */
+static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1 << pin;
+    }
+    else
+    {
+        base->PSOR = 1 << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param mask FGPIO pins' numbers macro
+ */
+static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param mask FGPIO pins' numbers macro
+ */
+static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+/*!
+ * @brief Reverses current output logic of the multiple FGPIO pins.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param mask FGPIO pins' numbers macro
+ */
+static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/* @} */
+
+/*!
+ * @name Input Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads the current input value of the whole FGPIO port.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param pin  FGPIO pin's number
+ * @retval FGPIO port input value
+ *        - 0: corresponding pin input low logic level.
+ *        - 1: corresponding pin input high logic level.
+ */
+static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/* @} */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+
+/*!
+ * @brief Reads the whole FGPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
+
+/*!
+ * @brief Clears the multiple FGPIO pins' interrupt status flag.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, etc.)
+ * @param mask FGPIO pins' numbers macro
+ */
+void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
+
+/* @} */
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_GPIO_H_*/

src/drivers/intmux/fsl_intmux.c

@@ -0,0 +1,156 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_intmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for INTMUX.
+ *
+ * @param base INTMUX peripheral base address.
+ */
+static uint32_t INTMUX_GetInstance(INTMUX_Type *base);
+
+/*!
+ * @brief Handle INTMUX all channels IRQ.
+ *
+ * The handler reads the INTMUX channel's active vector register. This returns the offset
+ * from the start of the vector table to the vector for the INTMUX channel's highest priority
+ * pending source interrupt. After a check for spurious interrupts (an offset of 0), the
+ * function address at the vector offset is read and jumped to.
+ *
+ * @param instance INTMUX instance number.
+ * @param channel INTMUX channel number.
+ */
+static void INTMUX_CommonIRQHandler(uint32_t instance, uint32_t channel);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map INTMUX instance number to base pointer. */
+static INTMUX_Type *const s_intmuxBases[] = INTMUX_BASE_PTRS;
+
+/*! @brief Array to map INTMUX instance number to clock name. */
+static const clock_ip_name_t s_intmuxClockName[] = INTMUX_CLOCKS;
+
+/*! @brief Array to map INTMUX instance number to IRQ number. */
+static const IRQn_Type s_intmuxIRQNumber[] = INTMUX_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t INTMUX_GetInstance(INTMUX_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_INTMUX_COUNT; instance++)
+    {
+        if (s_intmuxBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_INTMUX_COUNT);
+
+    return instance;
+}
+
+static void INTMUX_CommonIRQHandler(uint32_t instance, uint32_t channel)
+{
+    INTMUX_Type *intmuxBase;
+    uint32_t pendingIrqOffset;
+    
+    intmuxBase = s_intmuxBases[instance];
+    pendingIrqOffset = intmuxBase->CHANNEL[channel].CHn_VEC;
+    if (pendingIrqOffset)
+    {
+        uint32_t isr = *(uint32_t *)(SCB->VTOR + pendingIrqOffset);
+        ((void (*)(void))isr)();
+    }
+}
+
+void INTMUX_Init(INTMUX_Type *base)
+{
+    uint32_t channel;
+
+    /* Enable clock gate. */
+    CLOCK_EnableClock(s_intmuxClockName[INTMUX_GetInstance(base)]);
+    /* Reset all channels and enable NVIC vectors for all INTMUX channels. */
+    for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++)
+    {
+        INTMUX_ResetChannel(base, channel);
+        NVIC_EnableIRQ(s_intmuxIRQNumber[channel]);
+    }
+}
+
+void INTMUX_Deinit(INTMUX_Type *base)
+{
+    uint32_t channel;
+
+    /* Disable clock gate. */
+    CLOCK_DisableClock(s_intmuxClockName[INTMUX_GetInstance(base)]);
+    /* Disable NVIC vectors for all of the INTMUX channels. */
+    for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++)
+    {
+        NVIC_DisableIRQ(s_intmuxIRQNumber[channel]);
+    }
+}
+
+void INTMUX0_0_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 0);
+}
+
+void INTMUX0_1_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 1);
+}
+
+void INTMUX0_2_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 2);
+}
+
+void INTMUX0_3_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 3);
+}
+

src/drivers/intmux/fsl_intmux.h

@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_INTMUX_H_
+#define _FSL_INTMUX_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup intmux_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!< Version 2.0.0. */
+#define FSL_INTMUX_DRIVER_VERSION   (MAKE_VERSION(2, 0, 0))
+
+/*! @brief INTMUX channel logic mode. */
+typedef enum _intmux_channel_logic_mode
+{
+    kINTMUX_ChannelLogicOR = 0x0U, /*!< Logic OR all enabled interrupt inputs */
+    kINTMUX_ChannelLogicAND,       /*!< Logic AND all enabled interrupt inputs */
+} intmux_channel_logic_mode_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Initialization and deinitialization */
+/*@{*/
+
+/*!
+ * @brief Initializes INTMUX module.
+ *
+ * This function enables the clock gate for the specified INTMUX. It then resets all channels, so that no
+ * interrupt sources are routed and the logic mode is set to the default of #kINTMUX_ChannelLogicOR.
+ * Finally, the NVIC vectors for all of the INTMUX output channels are enabled.
+ *
+ * @param base INTMUX peripheral base address.
+ */
+void INTMUX_Init(INTMUX_Type *base);
+
+/*!
+ * @brief Deinitializes an INTMUX instance for operation.
+ *
+ * The clock gate for the specified INTMUX is disabled, and the NVIC vectors for all channels are disabled.
+ *
+ * @param base INTMUX peripheral base address.
+ */
+void INTMUX_Deinit(INTMUX_Type *base);
+
+/*!
+ * @brief Reset an INTMUX channel.
+ *
+ * Set all register values in the specified channel to their reset value. This will disable all interrupt
+ * sources for the channel.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel The INTMUX channel number.
+ */
+static inline void INTMUX_ResetChannel(INTMUX_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+    
+    base->CHANNEL[channel].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK;
+}
+
+/*!
+ * @brief Set the logic mode for an INTMUX channel.
+ *
+ * INTMUX channels can be configured to use one of two logic modes that control how pending interrupt sources
+ * on the channel trigger the output interrupt.
+ * - #kINTMUX_ChannelLogicOR means any source pending will trigger the output interrupt.
+ * - #kINTMUX_ChannelLogicAND means all selected sources on the channel must be pending before the channel
+ *          output interrupt will trigger.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel The INTMUX channel number.
+ * @param logic The INTMUX channel logic mode.
+ */
+static inline void INTMUX_SetChannelMode(INTMUX_Type *base, uint32_t channel, intmux_channel_logic_mode_t logic)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+    
+    base->CHANNEL[channel].CHn_CSR = INTMUX_CHn_CSR_AND(logic);
+}
+
+/*@}*/
+/*! @name Sources */
+/*@{*/
+
+/*!
+ * @brief Enable an interrupt source on an INTMUX channel.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel Index of the INTMUX channel on which the specified interrupt will be enabled.
+ * @param irq Interrupt to route to the specified INTMUX channel. The interrupt must be an INTMUX source.
+ */
+static inline void INTMUX_EnableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+    assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX);
+    
+    base->CHANNEL[channel].CHn_IER_31_0 |= (1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX));
+}
+
+/*!
+ * @brief Disable an interrupt source on an INTMUX channel.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel Index of the INTMUX channel on which the specified interrupt will be disabled.
+ * @param irq Interrupt number. The interrupt must be an INTMUX source.
+ */
+static inline void INTMUX_DisableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+    assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX);
+    
+    base->CHANNEL[channel].CHn_IER_31_0 &= ~(1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX));
+}
+
+/*@}*/
+/*! @name Status */
+/*@{*/
+
+/*!
+ * @brief Get INTMUX pending interrupt sources for specific channel.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel The INTMUX channel number.
+ * @return The mask of pending interrupt bits. Bit[n] set means intmux source n is pending.
+ */
+static inline uint32_t INTMUX_GetChannelPendingSources(INTMUX_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+
+    return base->CHANNEL[channel].CHn_IPR_31_0;
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_INTMUX_H_ */

src/drivers/ltc/ltc.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ltc_h
+#define _ltc_h
+
+#include "bootloader_common.h"
+
+//! @addtogroup ltc
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @name ltc_aes_security
+//@{
+
+//! @brief An initialization function for the decryption peripheral
+void ltc_aes_init(uint32_t *key);
+
+//! @brief Encrypts a 16 byte block of data
+//! in and out may use the same address so encrypting in place is supported
+void ltc_aes_encrypt(uint32_t *in, uint32_t *key, uint32_t *out);
+
+//! @brief Decrypts a 16 byte block of data
+//! in and out may use the same address so decrypting in place is supported
+void ltc_aes_decrypt(uint32_t *in, uint32_t *key, uint32_t *out);
+//@}
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // _ltc_h
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/ltc/src/ltc_aes_functions.c

@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "security/aes_security.h"
+
+// * - 00010000 - AES
+#define LTC_MODE_AES 0x10
+
+// ECB sub algorithm for AES mode
+#define LTC_AES_ALG_ECB 0x20
+
+// Algorithm state values
+// * - 00 - Update
+// * - 01 - Initialize
+// * - 10 - Finalize
+// * - 11 - Initialize/Finalize
+#define LTC_ALGORITHM_STATE_UPDATE 0
+#define LTC_ALGORITHM_STATE_INIT 1
+#define LTC_ALGORITHM_STATE_FINALIZE 2
+#define LTC_ALGORITHM_STATE_INIT_FIN 3
+
+// LTC Mode values for the ENC field
+// * - 0 - Decrypt.
+// * - 1 - Encrypt.
+#define LTC_DECRYPT 0
+#define LTC_ENCRYPT 1
+
+// Define LTC0 as LTC to make SW compatible with others.
+#ifndef LTC0
+#if defined(LTC)
+#define LTC0 LTC
+#endif
+#endif
+
+// Endian swaps each word in a 16 byte block
+static void reverse_bytes_block(uint32_t *data)
+{
+    uint32_t i;
+
+    for (i = 0; i < AES_BLOCK_SIZE_WORDS; i++)
+    {
+        data[i] = ((data[i] & (uint32_t)0x000000ffUL) << 24) | ((data[i] & (uint32_t)0x0000ff00UL) << 8) |
+                  ((data[i] & (uint32_t)0x00ff0000UL) >> 8) | ((data[i] & (uint32_t)0xff000000UL) >> 24);
+    }
+}
+
+void ltc_aes_init(uint32_t *key)
+{
+// Enable the LTC module
+#if defined(SIM_SCGC2_LTC_MASK)
+    SIM->SCGC2 |= SIM_SCGC2_LTC_MASK;
+#elif defined(SIM_SCGC5_LTC_MASK)
+    SIM->SCGC5 |= SIM_SCGC5_LTC_MASK;
+#else
+#error "Unknown LTC clock gate"
+#endif
+}
+
+void ltc_aes_encrypt(uint32_t *in, uint32_t *key, uint32_t *out)
+{
+    // Clear everything
+    LTC0->CW = ~0U;
+
+    reverse_bytes_block(key);
+    reverse_bytes_block(in);
+
+    // Write the key
+    LTC0->KEY[0] = key[0];
+    LTC0->KEY[1] = key[1];
+    LTC0->KEY[2] = key[2];
+    LTC0->KEY[3] = key[3];
+
+    // Write the key size
+    LTC0->KS = (AES_128_KEY_SIZE & LTC_KS_KS_MASK);
+
+    LTC0->MD = (LTC_MD_ALG(LTC_MODE_AES) |                // AES Mode
+                LTC_MD_AAI(LTC_AES_ALG_ECB) |             // AES ECB Algorithm
+                LTC_MD_AS(LTC_ALGORITHM_STATE_INIT_FIN) | // As per the RM set these bits although other parts of the
+                                                          // manual say it doesnt use this
+                LTC_MD_ENC(LTC_ENCRYPT));                 // We are encrypting
+
+    // Write the data size
+    LTC0->DS = (AES_BLOCK_SIZE & LTC_DS_DS_MASK);
+
+    // Clear the done interrupt/bit
+    LTC0->STA |= LTC_STA_DI_MASK;
+
+    // write the data
+    LTC0->IFIFO = in[0];
+    LTC0->IFIFO = in[1];
+    LTC0->IFIFO = in[2];
+    LTC0->IFIFO = in[3];
+
+    // wait for done bit
+    while (!(LTC0->STA & LTC_STA_DI_MASK))
+        ;
+
+    // read out the data
+    out[0] = LTC0->OFIFO;
+    out[1] = LTC0->OFIFO;
+    out[2] = LTC0->OFIFO;
+    out[3] = LTC0->OFIFO;
+
+    // Clear the done interrupt/bit
+    LTC0->STA |= LTC_STA_DI_MASK;
+
+    reverse_bytes_block(key);
+    reverse_bytes_block(in);
+    if (in != out)
+    {
+        reverse_bytes_block(out);
+    }
+    LTC0->DS = 0;
+}
+
+void ltc_aes_decrypt(uint32_t *in, uint32_t *key, uint32_t *out)
+{
+    // Clear everything
+    LTC0->CW = ~0U;
+
+    reverse_bytes_block(key);
+    reverse_bytes_block(in);
+
+    // Write the key
+    LTC0->KEY[0] = key[0];
+    LTC0->KEY[1] = key[1];
+    LTC0->KEY[2] = key[2];
+    LTC0->KEY[3] = key[3];
+
+    // Write the key size
+    LTC0->KS = (AES_128_KEY_SIZE & LTC_KS_KS_MASK);
+
+    LTC0->MD = (LTC_MD_ALG(LTC_MODE_AES) |                // AES Mode
+                LTC_MD_AAI(LTC_AES_ALG_ECB) |             // AES ECB Algorithm
+                LTC_MD_AS(LTC_ALGORITHM_STATE_INIT_FIN) | // As per the RM set these bits although other parts of the
+                                                          // manual say it doesnt use this
+                LTC_MD_ENC(LTC_DECRYPT));                 // We are decrypting
+
+    // Write the data size
+    LTC0->DS = (AES_BLOCK_SIZE & LTC_DS_DS_MASK);
+
+    // Clear the done interrupt/bit
+    LTC0->STA |= LTC_STA_DI_MASK;
+
+    // write the data
+    LTC0->IFIFO = in[0];
+    LTC0->IFIFO = in[1];
+    LTC0->IFIFO = in[2];
+    LTC0->IFIFO = in[3];
+
+    // wait for done bit
+    while (!(LTC0->STA & LTC_STA_DI_MASK))
+        ;
+
+    // read out the data
+    // read out the data
+    out[0] = LTC0->OFIFO;
+    out[1] = LTC0->OFIFO;
+    out[2] = LTC0->OFIFO;
+    out[3] = LTC0->OFIFO;
+
+    // Clear the done interrupt/bit
+    LTC0->STA |= LTC_STA_DI_MASK;
+
+    reverse_bytes_block(key);
+    reverse_bytes_block(in);
+    if (in != out)
+    {
+        reverse_bytes_block(out);
+    }
+    LTC0->DS = 0;
+}

src/drivers/microseconds/microseconds.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * @file microseconds.h
+ * @brief Microseconds timer driver based on PIT(Periodic Interrupt Timer)
+ *
+ * Notes:
+ */
+
+#ifndef ___MICROSECONDS_H__
+#define ___MICROSECONDS_H__
+
+#include <stdio.h>
+#include "fsl_device_registers.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif // __cplusplus
+
+/********************************************************************/
+//! @brief Initialize timer facilities.
+void microseconds_init(void);
+
+//! @brief Shutdown the microsecond timer
+void microseconds_shutdown(void);
+
+//! @brief Read back the running tick count
+uint64_t microseconds_get_ticks(void);
+
+//! @brief Returns the conversion of ticks to actual microseconds
+//!        This is used to seperate any calculations from getting a tick
+//         value for speed critical scenarios
+uint32_t microseconds_convert_to_microseconds(uint32_t ticks);
+
+//! @brief Returns the conversion of microseconds to ticks
+uint64_t microseconds_convert_to_ticks(uint32_t microseconds);
+
+//! @brief Delay specified time
+void microseconds_delay(uint32_t us);
+
+//! @brief Gets the clock value used for microseconds driver
+uint32_t microseconds_get_clock(void);
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+
+#endif /* ___MICROSECONDS_H__ */
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/microseconds/src/microseconds_pit.c

@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * @file microseconds.c
+ * @brief Microseconds timer driver source file
+ *
+ * Notes: The driver configure PIT as lifetime timer
+ */
+#include "microseconds/microseconds.h"
+#include <stdarg.h>
+#include "bootloader_common.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+// Below MACROs are defined in order to keep this driver compabtile among all targets.
+#if defined(PIT0)
+#define PIT PIT0
+#endif
+#if defined(SIM_SCGC6_PIT0_MASK)
+#define SIM_SCGC6_PIT_MASK SIM_SCGC6_PIT0_MASK
+#endif
+
+enum
+{
+    kFrequency_1MHz = 1000000UL
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+uint32_t s_tickPerMicrosecondMul8; //!< This value equal to 8 times ticks per microseconds
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Initialize timer facilities.
+//!
+//! It is initialize the timer to lifetime timer by chained channel 0
+//! and channel 1 together, and set b0th channels to maximum counting period
+void microseconds_init(void)
+{
+    uint32_t busClock;
+
+    // PIT clock gate control ON
+    SIM->SCGC6 |= SIM_SCGC6_PIT_MASK;
+
+    // Turn on PIT: MDIS = 0, FRZ = 0
+    PIT->MCR = 0x00;
+
+    // Set up timer 1 to max value
+    PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;          // setup timer 1 for maximum counting period
+    PIT->CHANNEL[1].TCTRL = 0;                   // Disable timer 1 interrupts
+    PIT->CHANNEL[1].TFLG = 1;                    // clear the timer 1 flag
+    PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_CHN_MASK; // chain timer 1 to timer 0
+    PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // start timer 1
+
+    // Set up timer 0 to max value
+    PIT->CHANNEL[0].LDVAL = 0xFFFFFFFF;         // setup timer 0 for maximum counting period
+    PIT->CHANNEL[0].TFLG = 1;                   // clear the timer 0 flag
+    PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // start timer 0
+
+    /* Calculate this value early
+     * The reason why use this solution is that lowest clock frequency supported by L0PB and L4KS
+     * is 0.25MHz, this solution will make sure ticks per microscond is greater than 0.
+     */
+
+    busClock = get_bus_clock();
+    s_tickPerMicrosecondMul8 = (busClock * 8) / kFrequency_1MHz;
+
+    // Make sure this value is greater than 0
+    if (!s_tickPerMicrosecondMul8)
+    {
+        s_tickPerMicrosecondMul8 = 1;
+    }
+}
+
+//! @brief Shutdown the microsecond timer
+void microseconds_shutdown(void)
+{
+    // Turn off PIT: MDIS = 1, FRZ = 0
+    PIT->MCR |= PIT_MCR_MDIS_MASK;
+}
+
+//! @brief Read back running tick count
+uint64_t microseconds_get_ticks(void)
+{
+    uint64_t valueH;
+    uint32_t valueL;
+
+#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && (FSL_FEATURE_PIT_HAS_LIFETIME_TIMER == 1)
+    valueH = PIT->LTMR64H;
+    valueL = PIT->LTMR64L;
+#else
+    // Make sure that there are no rollover of valueL.
+    // Because the valueL always decreases, so, if the formal valueL is greater than
+    // current value, that means the valueH is updated during read valueL.
+    // In this case, we need to re-update valueH and valueL.
+    do
+    {
+        valueH = PIT->CHANNEL[1].CVAL;
+        valueL = PIT->CHANNEL[0].CVAL;
+    } while (valueL < PIT->CHANNEL[0].CVAL);
+#endif // FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+
+    // Invert to turn into an up counter
+    return ~((valueH << 32) | valueL);
+}
+
+//! @brief Returns the conversion of ticks to actual microseconds
+//!        This is used to seperate any calculations from getting a timer
+//         value for speed critical scenarios
+uint32_t microseconds_convert_to_microseconds(uint32_t ticks)
+{
+    // return the total ticks divided by the number of Mhz the system clock is at to give microseconds
+    return (8 * ticks / s_tickPerMicrosecondMul8); //!< Assumes system clock will never be < 0.125 Mhz
+}
+
+//! @brief Returns the conversion of microseconds to ticks
+uint64_t microseconds_convert_to_ticks(uint32_t microseconds)
+{
+    return ((uint64_t)microseconds * s_tickPerMicrosecondMul8 / 8);
+}
+
+//! @brief Delay specified time
+//!
+//! @param us Delay time in microseconds unit
+void microseconds_delay(uint32_t us)
+{
+    uint64_t currentTicks = microseconds_get_ticks();
+
+    //! The clock value in Mhz = ticks/microsecond
+    uint64_t ticksNeeded = ((uint64_t)us * s_tickPerMicrosecondMul8 / 8) + currentTicks;
+    while (microseconds_get_ticks() < ticksNeeded)
+    {
+        ;
+    }
+}
+
+//! @brief Gets the clock value used for microseconds driver
+uint32_t microseconds_get_clock(void)
+{
+    return get_bus_clock();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/microseconds/src/microseconds_sysclk.c

@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * @file microseconds_sysclk.c
+ * @brief Microseconds sysclk timer driver source file
+ *
+ * Notes: The driver configure sysclk as lifetime timer
+ */
+#include "bootloader_common.h"
+#include "microseconds/microseconds.h"
+#include "fsl_device_registers.h"
+#include <stdarg.h>
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+enum
+{
+    kFrequency_1MHz = 1000000UL
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+//! @brief Tracks number of timer rollovers for extended time keeping
+//!        with 32 bits here + the 24 bits of the counter for lower resolution
+//!        it will be years worth of time
+volatile uint32_t s_highCounter;
+uint32_t s_tickPerMicrosecondMul8; //!< This value equal to 8 times ticks per microseconds
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Initialize and start the timer facilities using the SysTick.
+void microseconds_init(void)
+{
+    s_highCounter = 0;
+    SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; // Set reload register to max value
+    SysTick->VAL = 0;                        // As per ARM reference initialization, set initial value to 0
+                                             //  interrupts are only triggered when going from 1 to 0
+
+    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | // Set timer to core clock frequency
+                    SysTick_CTRL_TICKINT_Msk |   // Enable interrupts on timeout
+                    SysTick_CTRL_ENABLE_Msk;     // Enable SysTick IRQ and SysTick Timer
+
+    /* Calculate this value early
+     * The reason why use this solution is that lowest clock frequency supported by L0PB and L4KS
+     * is 0.25MHz, this solution will make sure ticks per microscond is greater than 0.
+     */
+    s_tickPerMicrosecondMul8 = (SystemCoreClock * 8) / kFrequency_1MHz;
+
+    // Make sure this value is greater than 0
+    if (!s_tickPerMicrosecondMul8)
+    {
+        s_tickPerMicrosecondMul8 = 1;
+    }
+}
+
+//! @brief Shutdown the microsecond timer
+void microseconds_shutdown(void)
+{
+    // Disable the timer and interrupts from it
+    SysTick->CTRL = SysTick->CTRL & ~(SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
+    
+    // Clear the current value register
+    SysTick->VAL = 0;
+}
+
+//! @brief Read back the running tick count
+uint64_t microseconds_get_ticks(void)
+{
+    uint64_t retVal;
+
+    //! The rollover counter keeps track of increments higher than the 24 bit SysTick counter
+    //! to combine them shift rollover up 24 bits and add the current ticks
+    uint32_t high;
+    uint32_t low;
+
+    // Check for an overflow condition between the two reads above
+    do
+    {
+        high = s_highCounter;
+        low = ~SysTick->VAL & SysTick_LOAD_RELOAD_Msk;
+    } while (high != s_highCounter);
+
+    retVal = ((uint64_t)high << 24) + low;
+
+    return retVal;
+}
+
+//! @brief Returns the conversion of ticks to actual microseconds
+//!        This is used to seperate any calculations from getting a timer
+//         value for timing sensitive scenarios
+uint32_t microseconds_convert_to_microseconds(uint32_t ticks)
+{
+    // return the total ticks divided by the number of Mhz the system clock is at to give microseconds
+    return (8 * ticks / s_tickPerMicrosecondMul8); //!< Assumes system clock will never be < 0.125 Mhz
+}
+
+//! @brief Returns the conversion of microseconds to ticks
+uint64_t microseconds_convert_to_ticks(uint32_t microseconds)
+{
+    return ((uint64_t)microseconds * s_tickPerMicrosecondMul8 / 8);
+}
+
+//! @brief Delay specified time
+//!
+//! @param us Delay time in microseconds unit
+void microseconds_delay(uint32_t us)
+{
+    uint64_t currentTicks = microseconds_get_ticks();
+
+    //! The clock value in Mhz = ticks/microsecond
+    uint64_t ticksNeeded = ((uint64_t)us * s_tickPerMicrosecondMul8 / 8) + currentTicks;
+    while (microseconds_get_ticks() < ticksNeeded)
+    {
+        ;
+    }
+}
+
+//! @brief Gets the clock value used for microseconds driver
+uint32_t microseconds_get_clock(void)
+{
+    return SystemCoreClock;
+}
+
+//! @brief Interrupt handler for the SysTick timer, this will just increment
+//         the rollover counter for extended time keeping
+void SysTick_Handler(void)
+{
+    s_highCounter++;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/mmcau/Freescale Software License Agreement.txt

@@ -0,0 +1,51 @@
+FREESCALE END-USER SOFTWARE LICENSE AGREEMENT
+This is a license agreement between you (either as an individual or as an authorized representative acting on behalf of your employer) and Freescale Semiconductor, Inc. (“Freescale”). It concerns your rights to use the software provided to you in binary or source code form and any accompanying written materials (the “Software”). The Software may include any updates or error corrections or documentation relating to the Software provided to you by Freescale under this License. In consideration for Freescale allowing you to access the Software, you are agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download or install the Software. If you change your mind later, stop using the Software and delete all copies of the Software in your possession or control. Any copies of the Software that you have already distributed, where permitted, and do not destroy will continue to be governed by this Agreement. Your prior use will also continue to be governed by this Agreement.
+
+1.	LICENSE GRANT. Freescale grants to you, free of charge, the non-exclusive, non-transferable, non-sublicensable right (1) to use the Software, (2) to reproduce the Software, (3) to prepare derivative works of the Software, 4) to distribute the Software and derivative works thereof in object (machine–readable) form as part of a programmable processing unit (e.g. a microprocessor, microcontroller, or digital signal processor) supplied directly or indirectly from Freescale (“Freescale System”), or in source (human-readable) form for the sole purpose of developing object (machine-readable) code for use of a Freescale System and (5) to sublicense to others the right to use the distributed Software, provided that any and all such sublicenses include the same terms and conditions of this Agreement.  Notwithstanding the limitation on damages in Section 8, Licensee will indemnify, defend, and hold harmless Freescale against any and all claims, costs, damages, liabilities, judgments and attorneys’ fees resulting from or arising out of any breach by the sublicensee, or resulting from or arising out of any action by the sublicensee inconsistent with this Agreement.  
+
+2.	OTHER RESTRICTIONS.  Subject to the license grant above, the following restrictions apply:
+
+a.	Freescale reserves all rights not expressly granted herein. 
+
+b.	You may not rent, lease, sublicense, lend or encumber the Software, unless otherwise expressly agreed to within this Agreement 
+
+c.	You may not distribute, manufacture, have manufactured, sublicense or otherwise reproduce the Software for purposes other than intended in this Agreement.
+
+d.	You may not remove or alter any proprietary legends, notices, or trademarks contained in the Licensed Software,
+
+e.	The terms and conditions of this Agreement will apply to any Software updates, provided to you at Freescale’s discretion, that replace and/or supplement the original Software, unless such update contains a separate license. 
+
+f.	You may not translate, reverse engineer, decompile, or disassemble the Software provided to you solely in object code format (machine readable) except to the extent applicable law specifically prohibits such restriction.  You will prohibit your sublicensees from translating, reverse engineering, decompiling, or disassembling the Software except to the extent applicable law specifically prohibits such restriction.
+
+3.	OPEN SOURCE.  Any open source software included in the Software licensed herein is not licensed under the terms of this Agreement, but is instead licensed under the terms of applicable open source license(s), such as the BSD License, Apache License or the Lesser GNU General Public License.  Your use of such open source software is subject to the terms of each applicable license.  You must agree to the terms of each such applicable license, or you should not use the open source software.  
+
+4.	COPYRIGHT.  The Software is licensed to you, not sold.  Freescale owns the Software, and United States copyright laws and international treaty provisions protect the Software. Therefore, you must treat the Software like any other copyrighted material (e.g. a book or musical recording). You may not use or copy the Software for any other purpose than what is described in this Agreement. Except as expressly provided herein, Freescale does not grant to you any express or implied rights under any Freescale or third party patents, copyrights, trademarks, or trade secrets. Additionally, you must reproduce and apply any copyright or other proprietary rights notices included on or embedded in the Software to any copies made thereof, in whole or in part, if any.  You may not remove any copyright notices of Freescale incorporated in the Software.
+
+5.	TERM AND TERMINATION.  The term of this Agreement shall commence on the date of installation or download and shall continue perpetually, unless earlier terminated in accordance with this Agreement.  Freescale has the right to terminate this Agreement without notice and require that you stop using and delete all copies of the Software in your possession or control if you violate any of the terms or restrictions of this Agreement.  Freescale may terminate this Agreement should any of the Software become, or in Freescale's reasonable opinion is likely to become, the subject of a claim of intellectual infringement or trade secret misappropriation.  Upon termination, you must cease use of and destroy, the Software and confirm compliance in writing to Freescale. Upon termination, the license granted pursuant to this Agreement immediately terminates and the provisions of Sections 4 through 18 will survive any termination of this Agreement. 
+
+6.	SUPPORT.  Freescale is NOT obligated to provide any support, upgrades or new releases of the Software. If you wish, you may contact Freescale and report problems and provide suggestions regarding the Software. Freescale has no obligation whatsoever to respond in any way to such a problem report or suggestion. Freescale may make changes to the Software at any time, without any obligation to notify or provide updated versions of the Software to you.
+
+7.	NO WARRANTY.  TO THE MAXIMUM EXTENT PERMITTED BY LAW, FREESCALE EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A WARRANTY OR REPRESENTATION BY FREESCALE THAT THE SOFTWARE OR ANY DERIVATIVE WORK DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES. 
+
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+
+9.	LIMITATION OF LIABILITY.  IN NO EVENT WILL FREESCALE BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW EVEN IF INFORMED IN ADVANCE OF THE POSSIBILITY OF SUCH DAMAGES.  FREESCALE’S LIABILITY WILL IN ANY EVENT AND UNDER ANY THEORY OF RECOVERY BE LIMITED TO THE TOTAL AMOUNT RECEIVED BY FREESCALE UNDER THIS AGREEMENT.  
+
+10.	COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must not resell, re-export, or provide, directly or indirectly, the licensed software or direct product thereof, in any form without obtaining appropriate export or re-export licenses from the United States Government and from the country from which the export or re-export is to occur.  An export occurs when products, technology, or software is transferred from one country to another by any means, including physical shipments, FTP file transfers, E-mails, faxes, remote server access, conversations, and the like.  An export also occurs when technology or software is transferred to a foreign national in the United States, or foreign national of the country in which the business activity is taking place.  A foreign national is any person who is neither a citizen nor permanent resident of the United States, or the country in which the business activity is taking place. Furthermore, if an export/import license, permit or other government required authority (collectively referred to as “government authorization”) is required to transfer technology, software, hardware or other Freescale property to non- Freescale party(ies) and is not approved, then Freescale is not obligated to transfer the Software under this Agreement until such “government authorization” is granted..
+
+11.	GOVERNMENT RIGHTS.  The Licensed Software is a “Commercial Item” as defined in 48 C.F.R. §2.101, consisting of “Commercial Computer Software” and “Commercial Computer Software Documentation,” as such terms are used in 48 C.F.R. § 12.212 or 48 C.F.R. §227.7202, as applicable and are only licensed to U.S. Government end users with the rights as are set forth herein..
+
+12.	HIGH RISK ACTIVITIES.  You acknowledge that the Software is not fault tolerant and is not designed, manufactured or intended by Freescale for incorporation into products intended for use or resale in on-line control equipment in hazardous, dangerous to life or potentially life-threatening environments requiring fail-safe performance, such as in the operation of nuclear facilities, aircraft navigation or communication systems, air traffic control, direct life support machines or weapons systems, in which the failure of products could lead directly to death, personal injury or severe physical or environmental damage (“High Risk Activities”). You specifically represent and warrant that you will not use the Software or any derivative work of the Software for High Risk Activities. 
+
+13.	CHOICE OF LAW; VENUE; LIMITATIONS.  You agree that the statutes and laws of the United States and the State of Texas, USA, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the state or federal courts in Texas, USA.  You agree that regardless of any statute or law to the contrary, any claim or cause of action arising out of or related to this Agreement or the Software must be filed within one (1) year after such claim or cause of action arose or be forever barred.
+
+14.	CONFIDENTIAL INFORMATION.  You must treat the Software as confidential information and you agree to retain the Software in confidence perpetually, with respect to Software in source code form (human readable), or for a period of five (5) years from the date of termination of this Agreement, with respect to all other parts of the Software.  During this period you may not disclose any part of the Software to anyone other than employees who have a need to know of the Software and who have executed written agreements obligating them to protect such Licensed Software to at least the same degree of care as in this Agreement.  You agree to use the same degree of care, but no less than a reasonable degree of care, with the Software as you do with your own confidential information. You may disclose Software to the extent required by a court or under operation of law or order provided that you notify Freescale of such requirement prior to disclosure, which you only disclose information required, and that you allow Freescale the opportunity to object to such court or other legal body requiring such disclosure.
+
+15.	PRODUCT LABELING.  You are not authorized to use any Freescale trademarks, brand names, or logos.
+
+16.	ENTIRE AGREEMENT.  This Agreement constitutes the entire agreement between you and Freescale regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any.  This Agreement may only be amended in written form, executed by you and Freescale.
+
+17.	SEVERABILITY.  If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or Freescale of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision.
+
+18.	NO WAIVER.  The waiver by Freescale of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision.
+

src/drivers/mmcau/mmcau.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _mmcau_h
+#define _mmcau_h
+
+#include "bootloader_common.h"
+
+//! @addtogroup mmcau
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @name mmcau_aes_security
+//@{
+
+//! @brief An initialization function for the decryption peripheral
+void mmcau_aes_init(uint32_t *key, uint32_t *keySchedule, uint32_t *rcon);
+
+//! @brief Encrypts a 16 byte block of data
+//! in and out may use the same address so encrypting in place is supported
+void mmcau_aes_encrypt(uint32_t *in, uint32_t *key, uint32_t *keySchedule, uint32_t *out);
+
+//! @brief Decrypts a 16 byte block of data
+//! in and out may use the same address so decrypting in place is supported
+void mmcau_aes_decrypt(uint32_t *in, uint32_t *key, uint32_t *keySchedule, uint32_t *out);
+//@}
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // _mmcau_h
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/mmcau/src/mmcau_aes_functions.c

@@ -0,0 +1,270 @@
+/********************************************************************************/
+/********************************************************************************/
+/**/
+/* Copyright (c) Freescale Semiconductor, Inc 2011.*/
+/**/
+/* FILE NAME      : mmcau_aes_functions.c*/
+/* VERSION        : $Id: mmcau_aes_functions.c.rca 1.2 Sat Jan  8 01:21:45 2011 rzsx60 Experimental $*/
+/* TYPE           : Source C library code*/
+/* DEPARTMENT     : MSG R&D Core and Platforms*/
+/* AUTHOR         : David Schimke*/
+/* AUTHOR'S EMAIL : David.Schimke@freescale.com*/
+/* -----------------------------------------------------------------------------*/
+/* Release history*/
+/* VERSION  Date       AUTHOR           DESCRIPTION*/
+/*          08-2010    David Schimke    Initial Release*/
+/*          01-2011    David Schimke    Add byte reverse to correct double word*/
+/*                                      read of byte array inputs for little*/
+/*                                      endian, header added, comment cleanup*/
+/**/
+/********************************************************************************/
+/********************************************************************************/
+
+#include "security/aes_security.h"
+#include "fsl_device_registers.h"
+
+#define AES_128_NUMBER_ROUNDS 10
+
+#define mmcau_1_cmd(c1) (0x80000000 + ((c1) << 22))
+#define mmcau_2_cmds(c1, c2) (0x80100000 + ((c1) << 22) + ((c2) << 11))
+#define mmcau_3_cmds(c1, c2, c3) (0x80100200 + ((c1) << 22) + ((c2) << 11) + c3)
+#define byterev(d) (((d) >> 24) | (((d) >> 8) & 0xff00) | (((d) << 8) & 0xff0000) | ((d) << 24))
+
+// Opcodes
+#define TL 0
+#define TS 0
+#define CASR 0
+#define CAA 1
+#define CA0 2
+#define CA1 3
+#define CA2 4
+#define CA3 5
+#define CA4 6
+#define CA5 7
+#define CA6 8
+#define CA7 9
+#define CA8 10
+#define CNOP 0x000
+#define LDR 0x010
+#define STR 0x020
+#define ADR 0x030
+#define RADR 0x040
+#define ADRA 0x050
+#define XOR 0x060
+#define ROTL 0x070
+#define MVRA 0x080
+#define MVAR 0x090
+#define AESS 0x0a0
+#define AESIS 0x0b0
+#define AESC 0x0c0
+#define AESIC 0x0d0
+#define AESR 0x0e0
+#define AESIR 0x0f0
+#define DESR 0x100
+#define DESK 0x110
+#define HASH 0x120
+#define SHS 0x130
+#define MDS 0x140
+#define SHS2 0x150
+#define ILL 0x1f0
+#define IP 8
+#define FP 4
+#define DC 1
+#define CP 2
+#define KSL1 0
+#define KSL2 1
+#define KSR1 2
+#define KSR2 3
+#define HFF 0
+#define HFG 1
+#define HFH 2
+#define HFI 3
+#define HFP 2
+#define HFC 4
+#define HFM 5
+#define HF2C 6
+#define HF2M 7
+#define HF2S 8
+#define HF2T 9
+#define HF2U 10
+#define HF2V 11
+
+#define MMCAU_INDIRECT_MASK 0x800
+
+#define MMCAU_PPB_DIRECT ((volatile uint32_t *)CAU_BASE)
+#define MMCAU_PPB_INDIRECT ((volatile uint32_t *)(CAU_BASE | MMCAU_INDIRECT_MASK))
+
+/********************************************************************************/
+/********************************************************************************/
+
+/********************************************************************************/
+/**/
+/* AES: Performs an AES key expansion*/
+/*   arguments*/
+/*     *key         pointer to input key 128 bits in length */
+/*     *keySchedule pointer to key schedule 128 bits in length */
+/*     *rcon needs to be set to the following structure which must be located outside */
+/*           outside of this function in order to make this code relocatable */
+/*           unsigned int rcon[10] = {0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, */
+/*                                    0x20000000, 0x40000000, 0x80000000, 0x1b000000, 0x36000000}; */
+/**/
+
+void mmcau_aes_init(uint32_t *key, uint32_t *keySchedule, uint32_t *rcon)
+{
+    int32_t i, j;
+
+    for (i = 0; i < 4; i++)
+    {
+        keySchedule[i] = byterev(key[i]);
+    }
+
+    *(MMCAU_PPB_INDIRECT + (LDR + CAA)) = keySchedule[i - 1]; /* CAA= key[3]*/
+
+    for (j = 0; j < 10; j++)
+    {
+        *(MMCAU_PPB_INDIRECT + (ROTL + CAA)) = 8;      /* rotate 8*/
+        *(MMCAU_PPB_DIRECT) = mmcau_1_cmd(AESS + CAA); /* SubBytes*/
+        *(MMCAU_PPB_INDIRECT + (XOR + CAA)) = rcon[j]; /* XOR rcon[j]*/
+
+        /* 1st calculation for keySchedule[4+0,8+0,12+0,16+0,20+0,24+0,28+0,32+0,36+0,40+0]*/
+        *(MMCAU_PPB_INDIRECT + (XOR + CAA)) = keySchedule[i - 4]; /*XOR key[i-4]*/
+        keySchedule[i++] = *(MMCAU_PPB_INDIRECT + (STR + CAA));   /*store key[i]*/
+
+        /* 2nd calculation for keySchedule[4+1,8+1,12+1,16+1,20+1,24+1,28+1,32+1,36+1,40+1]*/
+        *(MMCAU_PPB_INDIRECT + (XOR + CAA)) = keySchedule[i - 4]; /*XOR key[i-4]*/
+        keySchedule[i++] = *(MMCAU_PPB_INDIRECT + (STR + CAA));   /*store key[i]*/
+
+        /* 3rd calculation for keySchedule[4+2,8+2,12+2,16+2,20+2,24+2,28+2,32+2,36+2,40+2]*/
+        *(MMCAU_PPB_INDIRECT + (XOR + CAA)) = keySchedule[i - 4]; /*XOR key[i-4]*/
+        keySchedule[i++] = *(MMCAU_PPB_INDIRECT + (STR + CAA));   /*store key[i]*/
+
+        /* 4th calculation for keySchedule[4+3,8+3,12+3,16+3,20+3,24+3,28+3,32+3,36+3,40+3]*/
+        *(MMCAU_PPB_INDIRECT + (XOR + CAA)) = keySchedule[i - 4]; /*XOR key[i-4]*/
+        keySchedule[i++] = *(MMCAU_PPB_INDIRECT + (STR + CAA));   /*store key[i]*/
+    }
+}
+
+/********************************************************************************/
+/********************************************************************************/
+/**/
+/* AES: Encrypts a single 16-byte block*/
+/*   arguments*/
+/*           *in          pointer to 16-byte block of input plaintext*/
+/*           *key         pointer to input key 128 bits in length*/
+/*           *keySchedule pointer to key schedule 128 bits in length*/
+/*           *out         pointer to 16-byte block of output ciphertext*/
+/**/
+/*   NOTE    Input and output blocks may overlap*/
+/**/
+
+void mmcau_aes_encrypt(uint32_t *in, uint32_t *key, uint32_t *keySchedule, uint32_t *out)
+{
+    int32_t i, j;
+
+    /* load the 4 plain test bytes into the CAU's CA0 - CA3 registers*/
+    *(MMCAU_PPB_INDIRECT + (LDR + CA0)) = byterev(in[0]); /* load in[0]-> CA0*/
+    *(MMCAU_PPB_INDIRECT + (LDR + CA1)) = byterev(in[1]); /* load in[1]-> CA1*/
+    *(MMCAU_PPB_INDIRECT + (LDR + CA2)) = byterev(in[2]); /* load in[2]-> CA2*/
+    *(MMCAU_PPB_INDIRECT + (LDR + CA3)) = byterev(in[3]); /* load in[3]-> CA3*/
+
+    /* XOR the first 4 keys into the CAU's CA0 - CA3 registers*/
+    *(MMCAU_PPB_INDIRECT + (XOR + CA0)) = keySchedule[0]; /* XOR keys*/
+    *(MMCAU_PPB_INDIRECT + (XOR + CA1)) = keySchedule[1];
+    *(MMCAU_PPB_INDIRECT + (XOR + CA2)) = keySchedule[2];
+    *(MMCAU_PPB_INDIRECT + (XOR + CA3)) = keySchedule[3];
+
+    /* send a series of cau commands to perform the encryption*/
+    for (i = 0, j = 4; i < AES_128_NUMBER_ROUNDS - 1; i++, j += 4)
+    {
+        *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(AESS + CA0, AESS + CA1, AESS + CA2); /*Sbytes*/
+        *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(AESS + CA3, AESR);                   /*Sbyte,Shft*/
+        *(MMCAU_PPB_INDIRECT + (AESC + CA0)) = keySchedule[j];                  /* MixCols*/
+        *(MMCAU_PPB_INDIRECT + (AESC + CA1)) = keySchedule[j + 1];
+        *(MMCAU_PPB_INDIRECT + (AESC + CA2)) = keySchedule[j + 2];
+        *(MMCAU_PPB_INDIRECT + (AESC + CA3)) = keySchedule[j + 3];
+    }
+
+    *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(AESS + CA0, AESS + CA1, AESS + CA2); /* SubBytes*/
+    *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(AESS + CA3, AESR);                   /*SByte,Shft*/
+    *(MMCAU_PPB_INDIRECT + (XOR + CA0)) = keySchedule[j];                   /* XOR keys*/
+    *(MMCAU_PPB_INDIRECT + (XOR + CA1)) = keySchedule[j + 1];
+    *(MMCAU_PPB_INDIRECT + (XOR + CA2)) = keySchedule[j + 2];
+    *(MMCAU_PPB_INDIRECT + (XOR + CA3)) = keySchedule[j + 3];
+
+    /* store the 16-byte ciphertext output block into memory*/
+    out[0] = *(MMCAU_PPB_INDIRECT + (STR + CA0)); /* store 1st 4 bytes*/
+    out[1] = *(MMCAU_PPB_INDIRECT + (STR + CA1)); /* store 2nd 4 bytes*/
+    out[2] = *(MMCAU_PPB_INDIRECT + (STR + CA2)); /* store 3rd 4 bytes*/
+    out[3] = *(MMCAU_PPB_INDIRECT + (STR + CA3)); /* store 4th 4 bytes*/
+
+    out[0] = byterev(out[0]); /* Reverse 1st 4 bytes*/
+    out[1] = byterev(out[1]); /* Reverse 2nd 4 bytes*/
+    out[2] = byterev(out[2]); /* Reverse 3rd 4 bytes*/
+    out[3] = byterev(out[3]); /* Reverse 4th 4 bytes*/
+}
+
+/********************************************************************************/
+/********************************************************************************/
+/**/
+/* AES: Decrypts a single 16-byte block*/
+/*   arguments*/
+/*           *in          pointer to 16-byte block of input chiphertext*/
+/*           *key         pointer to input key 128 bits in length*/
+/*           *keySchedule pointer to key schedule 128 bits in length*/
+/*           *out         pointer to 16-byte block of output plaintext*/
+/**/
+/*   NOTE    Input and output blocks may overlap*/
+/**/
+
+void mmcau_aes_decrypt(uint32_t *in, uint32_t *key, uint32_t *keySchedule, uint32_t *out)
+{
+    int32_t i;
+
+    /* load the cipher bytes into the CAU's CA0 - CA3 registers*/
+    *(MMCAU_PPB_INDIRECT + (LDR + CA0)) = byterev(in[0]); /* load in[0] -> CA0*/
+    *(MMCAU_PPB_INDIRECT + (LDR + CA1)) = byterev(in[1]); /* load in[1] -> CA1*/
+    *(MMCAU_PPB_INDIRECT + (LDR + CA2)) = byterev(in[2]); /* load in[2] -> CA2*/
+    *(MMCAU_PPB_INDIRECT + (LDR + CA3)) = byterev(in[3]); /* load in[3] -> CA3*/
+
+    /* the keySchedule index (i) is adjusted to define the end of the elements*/
+    /* the adjustment factor = f(nr) is defined by the expression:*/
+    /*   end of keySchedule = 4 x (nr + 1) for nr = {10, 12, 14}*/
+    i = 4 * (AES_128_NUMBER_ROUNDS + 1);
+
+    /* XOR the keys into the CAU's CA0 - CA3 registers*/
+    *(MMCAU_PPB_INDIRECT + (XOR + CA3)) = keySchedule[--i]; /* XOR keys*/
+    *(MMCAU_PPB_INDIRECT + (XOR + CA2)) = keySchedule[--i];
+    *(MMCAU_PPB_INDIRECT + (XOR + CA1)) = keySchedule[--i];
+    *(MMCAU_PPB_INDIRECT + (XOR + CA0)) = keySchedule[--i];
+
+    /* send a series of cau commands to perform the decryption*/
+    while (i > 4)
+    {
+        *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(AESIR, AESIS + CA3, AESIS + CA2);
+        /* InvShiftRows,InvSubBytes*/
+        *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(AESIS + CA1, AESIS + CA0); /* InvSubByts*/
+        *(MMCAU_PPB_INDIRECT + (AESIC + CA3)) = keySchedule[--i];     /* InvMxCols*/
+        *(MMCAU_PPB_INDIRECT + (AESIC + CA2)) = keySchedule[--i];
+        *(MMCAU_PPB_INDIRECT + (AESIC + CA1)) = keySchedule[--i];
+        *(MMCAU_PPB_INDIRECT + (AESIC + CA0)) = keySchedule[--i];
+    }
+
+    *(MMCAU_PPB_DIRECT) = mmcau_3_cmds(AESIR, AESIS + CA3, AESIS + CA2);
+    /* InvShiftRows,InvSubBytes*/
+    *(MMCAU_PPB_DIRECT) = mmcau_2_cmds(AESIS + CA1, AESIS + CA0); /* InvSBytes*/
+    *(MMCAU_PPB_INDIRECT + (XOR + CA3)) = keySchedule[--i];       /* XOR keys*/
+    *(MMCAU_PPB_INDIRECT + (XOR + CA2)) = keySchedule[--i];
+    *(MMCAU_PPB_INDIRECT + (XOR + CA1)) = keySchedule[--i];
+    *(MMCAU_PPB_INDIRECT + (XOR + CA0)) = keySchedule[--i];
+
+    /* store the 16-byte ciphertext output block into memory*/
+    out[0] = *(MMCAU_PPB_INDIRECT + (STR + CA0)); /* store 1st 4 bytes*/
+    out[1] = *(MMCAU_PPB_INDIRECT + (STR + CA1)); /* store 2nd 4 bytes*/
+    out[2] = *(MMCAU_PPB_INDIRECT + (STR + CA2)); /* store 3rd 4 bytes*/
+    out[3] = *(MMCAU_PPB_INDIRECT + (STR + CA3)); /* store 4th 4 bytes*/
+
+    out[0] = byterev(out[0]); /* Reverse 1st 4 bytes*/
+    out[1] = byterev(out[1]); /* Reverse 2nd 4 bytes*/
+    out[2] = byterev(out[2]); /* Reverse 3rd 4 bytes*/
+    out[3] = byterev(out[3]); /* Reverse 4th 4 bytes*/
+}

src/drivers/otfad/fsl_otfad_driver.h

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _fsl_otfad_h
+#define _fsl_oftad_h
+
+#include "bootloader_common.h"
+#include "otfad/hal/fsl_otfad_hal.h"
+
+//! @addtogroup otfad
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief OTFAD Driver status codes.
+enum _otfad_driver_errors
+{
+    kStatus_OtfadSecurityViolation = MAKE_STATUS(kStatusGroup_OTFADDriver, 0),
+    kStatus_OtfadLogicallyDisabled = MAKE_STATUS(kStatusGroup_OTFADDriver, 1),
+    kStatus_OtfadInvalidKey = MAKE_STATUS(kStatusGroup_OTFADDriver, 2),
+    kStatus_OtfadInvalidKeyBlob = MAKE_STATUS(kStatusGroup_OTFADDriver, 3)
+};
+
+//! @brief Format of OTFAD key wrap key (KEK).
+//!
+//! The four consecutive little-endian memory-mapped
+//! registers provide 128 bits of key storage.
+typedef struct OtfadKek
+{
+    uint32_t keyWord0; //!< Word0: KEY[31:0][A03, A02, A01, A00]
+    uint32_t keyWord1; //!< Word1: KEY[31:0][A07, A06, A05, A04]
+    uint32_t keyWord2; //!< Word2: KEY[31:0][A11, A10, A09, A08]
+    uint32_t keyWord3; //!< Word3: KEY[31:0][A15, A14, A13, A12]
+} otfad_kek_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif // __cplusplus
+
+//! @brief Initialize.
+//!
+//! If OTFAD KEY in the SIM module is invalid, or the key blobs are invalid,
+//! then the OTFAD will be initialized to bypass mode
+//! (no decryption). Otherwise, keyBlobs will be unwrapped and programmed into
+//! the OTFAD context registers.
+//!
+//! @param instance Module instance
+//! @param keyBlobs Pointer to array of 4 key blobs
+//! @param kek Pointer to OTFAD Key Encryption Key (KEK)
+//! @retval kStatus_OtfadLogicallyDisabled OTFAD is disabled
+//! @retval kStatus_OtfadSecurityViolation Security violation detectd
+//! @retval kStatus_Success OTFAD has been initialized
+status_t otfad_init(uint32_t instance, const uint8_t *keyBlobs, const otfad_kek_t *kek);
+
+//! @brief Bypass.
+//!
+//! @param instance Module instance
+//! @retval kStatus_Success OTFAD has been bypassed.
+status_t otfad_bypass(uint32_t instance);
+
+//! @brief Resume.
+//!
+//! @param instance Module instance
+//! @retval kStatus_Success OTFAD has been resumed.
+status_t otfad_resume(uint32_t instance);
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+
+//! @}
+
+#endif // _fsl_otfad.h_
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/otfad/hal/fsl_otfad_hal.c

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bootloader_common.h"
+#include "fsl_device_registers.h"
+#include "utilities/fsl_assert.h"
+#include "fsl_otfad_hal.h"
+
+#if BL_FEATURE_OTFAD_MODULE
+
+//! @addtogroup otfad_hal
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+// See fsl_otfad_hal.h for documentation on this function.
+uint32_t otfad_hal_get_mode(OTFAD_Type *baseAddr)
+{
+    return ((baseAddr->SR & OTFAD_SR_MODE_MASK) >> OTFAD_SR_MODE_SHIFT);
+}
+
+// See fsl_otfad_hal.h for documentation on this function.
+void otfad_hal_global_enable(OTFAD_Type *baseAddr)
+{
+    baseAddr->CR |= OTFAD_CR_GE_MASK;
+}
+
+// See fsl_otfad_hal.h for documentation on this function.
+void otfad_hal_global_disable(OTFAD_Type *baseAddr)
+{
+    baseAddr->CR &= ~OTFAD_CR_GE_MASK;
+}
+
+// See fsl_otfad_hal.h for documentation on this function.
+bool otfad_hal_is_enabled(OTFAD_Type *baseAddr)
+{
+    return (baseAddr->CR & OTFAD_CR_GE_MASK) ? true : false;
+}
+
+// See fsl_otfad_hal.h for documentation on this function.
+void otfad_hal_restricted_register_access_enable(OTFAD_Type *baseAddr)
+{
+    baseAddr->CR |= OTFAD_CR_RRAE_MASK;
+}
+
+// See fsl_otfad_hal.h for documentation on this function.
+bool otfad_hal_is_register_access_restricted(OTFAD_Type *baseAddr)
+{
+    return (baseAddr->CR & OTFAD_CR_RRAE_MASK) ? true : false;
+}
+
+// See fsl_otfad_hal.h for documentation on this function.
+uint32_t otfad_hal_get_hardware_revision_level(OTFAD_Type *baseAddr)
+{
+    return ((baseAddr->SR & OTFAD_SR_HRL_MASK) >> OTFAD_SR_HRL_SHIFT);
+}
+
+// See fsl_otfad_hal.h for documentation on this function.
+uint32_t otfad_hal_get_number_of_contexts(OTFAD_Type *baseAddr)
+{
+    return ((baseAddr->SR & OTFAD_SR_NCTX_MASK) >> OTFAD_SR_NCTX_SHIFT);
+}
+
+// See fsl_otfad_hal.h for documentation on this function.
+void otfad_hal_set_context(OTFAD_Type *baseAddr, uint32_t contextNum, const otfad_context_info_t *contextInfo)
+{
+    // Key words
+    baseAddr->CTX[contextNum].CTX_KEY[0] = contextInfo->keyInfo[0];
+    baseAddr->CTX[contextNum].CTX_KEY[1] = contextInfo->keyInfo[1];
+    baseAddr->CTX[contextNum].CTX_KEY[2] = contextInfo->keyInfo[2];
+    baseAddr->CTX[contextNum].CTX_KEY[3] = contextInfo->keyInfo[3];
+
+    // Counter words
+    baseAddr->CTX[contextNum].CTX_CTR[0] = contextInfo->ctrInfo[0];
+    baseAddr->CTX[contextNum].CTX_CTR[1] = contextInfo->ctrInfo[1];
+
+    // Region words
+    baseAddr->CTX[contextNum].CTX_RGD[0] = contextInfo->regionInfo[0];
+    baseAddr->CTX[contextNum].CTX_RGD[1] = contextInfo->regionInfo[1];
+}
+
+//! @}
+
+#endif // BL_FEATURE_OTFAD_MODULE
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/otfad/hal/fsl_otfad_hal.h

@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _fsl_otfad_hal_h
+#define _fsl_oftad_hal_h
+
+#include "bootloader_common.h"
+
+//! @addtogroup otfad_hal
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Constants
+enum _hal_constants
+{
+    kOtfadNumKeyWords = 4, //!< Number of key words
+    kOtfadNumCtrWords = 2, //!< Number of counter words
+    kOtfadNumRgnWords = 2  //!< Number of region words
+};
+
+//! @brief Format of context info.
+typedef struct OtfadContextInfo
+{
+    uint32_t keyInfo[kOtfadNumKeyWords];    //!< Key words
+    uint32_t ctrInfo[kOtfadNumCtrWords];    //!< Counter words
+    uint32_t regionInfo[kOtfadNumRgnWords]; //!< Region words
+} otfad_context_info_t;
+
+//! @brief Operational modes.
+enum _otfad_modes
+{
+    kOtfadMode_Normal = 0x00,            //!< Normal mode (NRM)
+    kOtfadMode_SecurityViolation = 0x02, //!< Security Violation Mode (SVM)
+    kOtfadMode_LogiallyDisabled = 0x03   //!< Logically Disabled Mode (LDM)
+};
+
+//! @brief Enable flags.
+enum _otfad_enables
+{
+    kOtfadDisable = 0x00, //!< Disable
+    kOtfadEnable = 0x01   //!< Enable
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif // __cplusplus
+
+//! @brief Get the current mode.
+//!
+//! @param baseAddr Module base address
+//! @return Current mode in status register
+uint32_t otfad_hal_get_mode(OTFAD_Type *baseAddr);
+
+//! @brief Enable the module.
+//!
+//! Set the global enable flag in the control register to '1'.
+//! A power-on reset is required to clear this flag.
+//!
+//! @param baseAddr Module base address
+void otfad_hal_global_enable(OTFAD_Type *baseAddr);
+
+//! @brief Disable the module.
+//!
+//! Clear the global enable flag in the control register to '0'.
+//! A power-on reset is required to clear this flag.
+//!
+//! @param baseAddr Module base address
+void otfad_hal_global_disable(OTFAD_Type *baseAddr);
+
+//! @brief Get enabled state.
+//!
+//! @param baseAddr Module base address
+//! @return Global enabled flag in status register
+bool otfad_hal_is_enabled(OTFAD_Type *baseAddr);
+
+//! @brief Enable restricted register status.
+//!
+//! Set the restricted register access enable flag in the control register to '1'.
+//! A power-on reset is required to clear this flag.
+//!
+//! @param baseAddr Module base address
+void otfad_hal_restricted_register_access_enable(OTFAD_Type *baseAddr);
+
+//! @brief Get restricted register access state.
+//!
+//! @param baseAddr Module base address
+//! @return Restricted register access flag in status register
+bool otfad_hal_is_register_access_restricted(OTFAD_Type *baseAddr);
+
+//! @brief Get hardware revision level.
+//!
+//! @param baseAddr Module base address
+//! @return Hardware revision level from status register
+uint32_t otfad_hal_get_hardware_revision_level(OTFAD_Type *baseAddr);
+
+//! @brief Get number of contexts.
+//!
+//! @param baseAddr Module base address
+//! @return Number of contexts from status register
+uint32_t otfad_hal_get_number_of_contexts(OTFAD_Type *baseAddr);
+
+//! @brief Set context info.
+//!
+//! @param baseAddr Module base address
+//! @param contextNum Context number
+//! @param contextInfo Ponter to context info struct
+void otfad_hal_set_context(OTFAD_Type *baseAddr, uint32_t contextNum, const otfad_context_info_t *contextInfo);
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+
+//! @}
+
+#endif // _fsl_otfad_hal.h_
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/otfad/src/fsl_otfad_driver.c

@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include "bootloader_common.h"
+#include "fsl_device_registers.h"
+#include "utilities/fsl_assert.h"
+#include "otfad/fsl_otfad_driver.h"
+#include "security/aes128_key_wrap_unwrap.h"
+#include "crc/crc32.h"
+#include "security/aes_security.h"
+
+#if BL_FEATURE_OTFAD_MODULE
+
+//! @addtogroup otfad
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Constants
+enum _constants
+{
+    kAesKeySizeBytes = 16,                                    //!< Number of bytes in AES-128 key
+    kCtrSizeBytes = 8,                                        //!< Number of bytes in Ctr
+    kCrc32SizeBytes = 32,                                     //!< Number of bytes covered by CRC32
+    kNumKeyBlobs = 4,                                         //!< Number of key blobs
+    kKeyBlobSizeBytes = 64,                                   //!< Key blob size in bytes
+    kKeyBlobArraySizeBytes = kKeyBlobSizeBytes * kNumKeyBlobs //!< Key blob array size in bytes
+};
+
+//! @brief Key Blob format.
+typedef struct KeyBlob
+{
+    uint8_t key[kAesKeySizeBytes]; // 16 bytes, 128-bits, KEY[A15...A00]
+    uint8_t ctr[kCtrSizeBytes];    // 8 bytes, 64-bits, CTR[C7...C0]
+    uint32_t srtaddr;              // region start, STRADDR[31 - 10]
+    uint32_t endaddr;              // region end, ENDADDR[31 - 10] + flags R0,ADE,VLD
+                                   // end of 32-byte area covered by CRC
+    uint32_t zero_fill;            // zeros
+    uint32_t key_blob_crc32;       // crc32 over 1st 32-bytes
+                                   // end of 40 byte (5*64-bit) key blob data
+    uint8_t expanded_wrap_data[8]; // 8 bytes, used for wrap expanded data
+                                   // end of 48 byte (6*64-bit) wrap data
+    uint8_t unused_filler[16];     // unused fill to 64 bytes
+} keyblob_t;
+
+typedef struct KeyBlobUnwrap
+{
+    uint8_t ivHeader[8]; // 8 bytes that are added during the wrap for an unwrap error check (ivHeader == wrapIV)
+    keyblob_t keyBlob;   // The actual keyblob
+} keyblob_data_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// Local function prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+static void program_contexts(OTFAD_Type *baseAddr, uint8_t *keyBlobs, uint32_t *kek);
+static bool validate_crc(const keyblob_t *keyBlob);
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Instance base addresses.
+const uint32_t g_otfadBaseAddr[] = OTFAD_BASE_ADDRS;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Validate CRC32 in key blob.
+//!
+//! @param keyBlob Pointer to key blob
+//! @return True if CRC matches, False otherwise
+bool validate_crc(const keyblob_t *keyBlob)
+{
+    assert(keyBlob);
+    crc32_data_t crc32Data;
+
+    crc32_init(&crc32Data);
+    crc32_update(&crc32Data, (const uint8_t *)keyBlob, kCrc32SizeBytes);
+    uint32_t hash;
+    crc32_finalize(&crc32Data, &hash);
+    return hash == keyBlob->key_blob_crc32;
+}
+
+//! @brief Program context regiters with information from key blobs.
+//!
+//! Key blobs are unwrapped first. Each blob is validated with CRC32.
+//!
+//! @param baseAddr OTFAD module base address
+//! @param keyBlobs pointer to array of 4 key blobs
+//! @param kek KeK words
+static void program_contexts(OTFAD_Type *baseAddr, uint8_t *keyBlobs, uint32_t *kek)
+{
+    assert(kek);
+    assert(keyBlobs);
+
+    uint32_t numContexts = otfad_hal_get_number_of_contexts(baseAddr);
+    keyblob_data_t unwrappedKeyBlob;
+
+    for (uint32_t ctx = 0; ctx < numContexts; ++ctx)
+    {
+        uint32_t status = do_aes128_key_unwrap(keyBlobs, (uint8_t *)&unwrappedKeyBlob, kek);
+        if (status == 0)
+        {
+            if (!validate_crc(&unwrappedKeyBlob.keyBlob))
+            {
+                // Ignore this key blob and move to the next one.
+                keyBlobs += sizeof(keyblob_t);
+                continue;
+            }
+
+            // Program context registers from unwrapped keyblob.
+            const otfad_context_info_t *contextInfo = (const otfad_context_info_t *)&unwrappedKeyBlob.keyBlob;
+            otfad_hal_set_context(baseAddr, ctx, contextInfo);
+        }
+
+        // Advance to next wrapped key blob.
+        keyBlobs += sizeof(keyblob_t);
+    }
+
+    // Clear unwrapped key blob memory on stack.
+    memset(&unwrappedKeyBlob, 0, sizeof(unwrappedKeyBlob));
+}
+
+// See fsl_otfd_driver.h for documentation on this function.
+status_t otfad_init(uint32_t instance, const uint8_t *keyBlobs, const otfad_kek_t *otfadKek)
+{
+    assert(instance < FSL_FEATURE_SOC_OTFAD_COUNT);
+    uint32_t baseAddr = g_otfadBaseAddr[instance];
+    assert(keyBlobs);
+    assert(otfadKek);
+
+    // Make local copies of keyBlobs and Kek.
+    static uint8_t blobs[kKeyBlobArraySizeBytes];
+    static uint32_t kek[AES_BLOCK_SIZE_WORDS];
+    memcpy(blobs, keyBlobs, sizeof(blobs));
+    memcpy(kek, otfadKek, sizeof(kek));
+
+    aes_init(kek);
+
+    // Get the operational mode.
+    uint32_t opMode = otfad_hal_get_mode((OTFAD_Type *)baseAddr);
+
+    if (opMode == kOtfadMode_Normal)
+    {
+        // It the module is access restricted it cannot be programmed.
+        if (otfad_hal_is_register_access_restricted((OTFAD_Type *)baseAddr))
+        {
+            return kStatus_OtfadLogicallyDisabled;
+        }
+
+        program_contexts((OTFAD_Type *)baseAddr, blobs, kek);
+
+        // Enable decryption.
+        otfad_hal_global_enable((OTFAD_Type *)baseAddr);
+        if (!otfad_hal_is_enabled((OTFAD_Type *)baseAddr))
+        {
+            // Could not enable module.
+            otfad_hal_restricted_register_access_enable((OTFAD_Type *)baseAddr);
+            return kStatus_OtfadLogicallyDisabled;
+        }
+
+        // Restrict access to context registers so software can't read clear keys.
+        otfad_hal_restricted_register_access_enable((OTFAD_Type *)baseAddr);
+
+        return kStatus_Success;
+    }
+    else if (opMode == kOtfadMode_SecurityViolation)
+    {
+        return kStatus_OtfadSecurityViolation;
+    }
+    else
+    {
+        return kStatus_OtfadLogicallyDisabled;
+    }
+}
+
+// See fsl_otfd_driver.h for documentation on this function.
+status_t otfad_bypass(uint32_t instance)
+{
+    assert(instance < FSL_FEATURE_SOC_OTFAD_COUNT);
+    uint32_t baseAddr = g_otfadBaseAddr[instance];
+
+    otfad_hal_global_disable((OTFAD_Type *)baseAddr);
+
+    return kStatus_Success;
+}
+
+// See fsl_otfd_driver.h for documentation on this function.
+status_t otfad_resume(uint32_t instance)
+{
+    assert(instance < FSL_FEATURE_SOC_OTFAD_COUNT);
+    uint32_t baseAddr = g_otfadBaseAddr[instance];
+
+    otfad_hal_global_enable((OTFAD_Type *)baseAddr);
+
+    return kStatus_Success;
+}
+
+//! @}
+
+#endif // BL_FEATURE_OTFAD_MODULE
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/port/fsl_port.h

@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_PORT_H_
+#define _FSL_PORT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup port_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!< Version 2.0.0. */
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+
+/*! @brief Internal resistor pull feature selection */
+enum _port_pull
+{
+    kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */
+    kPORT_PullDown = 2U,    /*!< internal pull-down resistor is enabled. */
+    kPORT_PullUp = 3U,      /*!< internal pull-up resistor is enabled. */
+};
+
+/*! @brief Slew rate selection */
+enum _port_slew_rate
+{
+    kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */
+    kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */
+};
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+/*! @brief Internal resistor pull feature enable/disable */
+enum _port_open_drain_enable
+{
+    kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */
+    kPORT_OpenDrainEnable = 1U,  /*!< internal pull-up resistor is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+/*! @brief Passive filter feature enable/disable */
+enum _port_passive_filter_enable
+{
+    kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */
+    kPORT_PassiveFilterEnable = 1U,  /*!< slow slew rate is configured. */
+};
+
+/*! @brief Configures the drive strength.*/
+enum _port_drive_strength
+{
+    kPORT_LowDriveStrength = 0U,  /*!< low drive strength is configured. */
+    kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */
+};
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+/*! @brief unlock/lock the pin control register field[15:0] */
+enum _port_lock_register
+{
+    kPORT_UnLockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
+    kPORT_LockRegister = 1U,   /*!< Pin Control Register fields [15:0] are locked. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+
+/*! @brief Pin mux selection*/
+typedef enum _port_mux
+{
+    kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin.*/
+    kPORT_MuxAsGpio = 1U,           /*!< corresponding pin is configured as GPIO.*/
+    kPORT_MuxAlt2 = 2U,             /*!< chip-specific*/
+    kPORT_MuxAlt3 = 3U,             /*!< chip-specific*/
+    kPORT_MuxAlt4 = 4U,             /*!< chip-specific*/
+    kPORT_MuxAlt5 = 5U,             /*!< chip-specific*/
+    kPORT_MuxAlt6 = 6U,             /*!< chip-specific*/
+    kPORT_MuxAlt7 = 7U,             /*!< chip-specific*/
+} port_mux_t;
+
+/*! @brief Configures the interrupt generation condition.*/
+typedef enum _port_interrupt
+{
+    kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled.*/
+#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
+    kPORT_DmaRisingEdge = 0x1U,  /*!< DMA request on rising edge.*/
+    kPORT_DmaFallingEdge = 0x2U, /*!< DMA request on falling edge.*/
+    kPORT_DmaEitherEdge = 0x3U,  /*!< DMA request on either edge.*/
+#endif
+    kPORT_InterruptLogicZero = 0x8U,            /*!< Interrupt when logic zero. */
+    kPORT_InterruptRisingEdge = 0x9U,           /*!< Interrupt on rising edge. */
+    kPORT_InterruptFallingEdge = 0xAU,          /*!< Interrupt on falling edge. */
+    kPORT_InterruptEitherEdge = 0xBU,           /*!< Interrupt on either edge. */
+    kPORT_InterruptLogicOne = 0xCU,             /*!< Interrupt when logic one. */
+    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */
+    kPORT_ActiveLowTriggerOutputEnable = 0xEU,  /*!< Enable active low trigger output. */
+} port_interrupt_t;
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*! @brief Digital filter clock source selection*/
+typedef enum _port_digital_filter_clock_source
+{
+    kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock.*/
+    kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock.*/
+} port_digital_filter_clock_source_t;
+
+/*! @brief PORT digital filter feature configuration definition*/
+typedef struct _port_digital_filter_config
+{
+    uint32_t digitalFilterWidth;                    /*!< Set digital filter width */
+    port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
+} port_digital_filter_config_t;
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+/*! @brief PORT pin config structure */
+typedef struct _port_pin_config
+{
+    uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */
+    uint16_t slewRate : 1;   /*!< fast/slow slew rate Configure */
+    uint16_t : 1;
+    uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+    uint16_t openDrainEnable : 1; /*!< open drain enable/disable */
+#else
+    uint16_t : 1;
+#endif                          /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+    uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */
+    uint16_t : 1;
+    uint16_t mux : 3; /*!< pin mux Configure */
+    uint16_t : 4;
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+    uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+} port_pin_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the port PCR register.
+ *
+ * This is an example to define an input pin or output pin PCR configuration:
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnLockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param pin    PORT pin number.
+ * @param config PORT PCR register configure structure.
+ */
+static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
+{
+    assert(config);
+    uint32_t addr = (uint32_t)&base->PCR[pin];
+    *(volatile uint16_t *)(addr) = *((const uint16_t *)config);
+}
+
+/*!
+ * @brief Sets the port PCR register.
+ *
+ * This is an example to define an input pin or output pin PCR configuration:
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp ,
+ *      kPORT_PullEnable,
+ *      kPORT_FastSlewRate,
+ *      0,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      0,
+ *      kPORT_MuxAsGpio,
+ *      0,
+ *      kPORT_UnLockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param mask    PORT pin mask.
+ * @param config PORT PCR register configure structure.
+ */
+static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
+{
+    assert(config);
+
+    uint16_t PCRL = *((const uint16_t *)config);
+
+    if (mask & 0xffffU)
+    {
+        base->GPCLR = (mask & 0xffffU) | PCRL;
+    }
+    if (mask >> 16)
+    {
+        base->GPCHR = (mask >> 16) | PCRL;
+    }
+}
+
+/*!
+ * @brief Configures the pin muxing.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param pin   PORT pin number.
+ * @param mux   pin muxing slot selection.
+ *        - kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
+ *        - kPORT_MuxAsGpio          : Set as GPIO.
+ *        - others                : chip-specific.
+ *
+ * Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
+ *        the PORT_SetPinsConfig need to configure the pin mux anyway(Otherwise the pin mux will
+ *        be reset to zero : kPORT_PinDisabledOrAnalog).
+ *        This function is recommended to use in the case you just need to reset the pin mux
+ */
+static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
+}
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*!
+ * @brief Enables the digital filter in one port.
+ *        Each bit of the 32-bit register represents one pin.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param mask  PORT pins' numbers macro.
+ */
+static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
+{
+    if (enable == true)
+    {
+        base->DFER |= mask;
+    }
+    else
+    {
+        base->DFER &= ~mask;
+    }
+}
+
+/*!
+ * @brief set the digital filter in one port.
+ *        Each bit of the 32-bit register represents one pin.
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param config PORT digital filter configuration structure.
+ */
+static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
+{
+    assert(config);
+
+    base->DFCR = PORT_DFCR_CS(config->clockSource);
+    base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
+}
+
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+/*@}*/
+
+/*! @name Interrupt */
+/*@{*/
+
+/*!
+ * @brief Configures the port pin interrupt/DMA request.
+ *
+ * @param base    PORT peripheral base pointer.
+ * @param pin     PORT pin number.
+ * @param config  PORT pin interrupt configuration.
+ *        - kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ *        - kPORT_DmaRisingEdge : DMA request on rising edge.
+ *        - kPORT_DmaFallingEdge: DMA request on falling edge.
+ *        - kPORT_DmaEitherEdge : DMA request on either edge.
+ *        - kPORT_InterruptLogicZero  : Interrupt when logic zero.
+ *        - kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ *        - kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ *        - kPORT_InterruptEitherEdge : Interrupt on either edge.
+ *        - kPORT_InterruptLogicOne   : Interrupt when logic one.
+ *        - kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output.
+ *        - kPORT_ActiveLowTriggerOutputEnable  : Enable active low trigger output.
+ */
+static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, const port_interrupt_t config)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
+}
+
+/*!
+ * @brief Reads the whole port status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base PORT peripheral base pointer.
+ * @retval Current port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
+{
+    return base->ISFR;
+}
+/*!
+ * @brief Clears the multiple pins' interrupt status flag.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param mask PORT pins' numbers macro.
+ */
+static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
+{
+    base->ISFR = mask;
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PORT_H_ */

src/drivers/qspi/qspi.h

@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __QSPI_H__
+#define __QSPI_H__
+
+#include "memory/memory.h"
+#include "bootloader_common.h"
+
+/*!
+ * @addtogroup qspi_driver
+ * @{
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+#define QSPI_LUT_MAX_ENTRIES 64
+#define QSPI_PRE_CMD_CNT 4 //!< the max number of pre commands
+#define QSPI_FEATURE_ENABLE 1
+
+#define QSPI_VERSION_NAME 'Q'
+
+enum __qspi_config_block_tags
+{
+    //! @brief Tag value used to validate the qspi config block.
+    kQspiConfigTag = FOUR_CHAR_CODE('k', 'q', 'c', 'f'),
+    //!< kQspiVersion1.1 Support Parallel mode, timeout check
+    //!< kQspiVersion1.2 Support configuring QuadSPI_FLSHCR[TDH]
+    kQspiVersionTag = FOUR_CHAR_CODE(0, 2, 1, 'Q'),
+};
+
+//! @brief QSPI Flash mode options
+typedef enum _qspiflash_mode_option
+{
+    kQspiFlashMode_Serial = 0,  //!< Serial mode
+    kQspiFlashMode_Parallel = 1 //!< Parallel mode
+} qspiflash_mode_option_t;
+
+//! @brief External spi flash pad definition
+typedef enum _qspiflash_pad
+{
+    kQspiFlashPad_Single = 0, //!< Single-pad spi flash
+    kQspiFlashPad_Dual = 1,   //!< Dual-pad spi flash
+    kQspiFlashPad_Quad = 2,   //!< Quad-pad spi flash
+    kQspiFlashPad_Octal = 3   //!< Octal-pad spi flash
+} qspiflash_pad_t;
+
+//! @brief QSPI Serial Clock Frequency options
+typedef enum _qspi_serial_clock_freq
+{
+    kQspiSerialClockFreq_Low = 0, //!< QuadSPI module works at low frequency
+    kQspiSerialClockFreq_Mid = 1, //!< QuadSPI module works at mid frequency
+    kQspiSerialClockFreq_High = 2 //!< QuadSPI module works at high frequency
+} qspi_serial_clock_freq_t;
+
+//! @brief QSPI flash property tag values
+typedef enum _qspiflash_property
+{
+    kQspiFlashProperty_InitStatus = 0,
+    kQspiFlaghProperty_StartAddress = 1,           //!< Tag used to retrieve start address
+    kQspiFlashProperty_TotalFlashSizeInKBytes = 2, //!< Tag used to retrieve total flash size in terms of KByte
+    kQspiFlashProperty_PageSize = 3,               //!< Tag used to retreive page size in terms of byte
+    kQspiFlashProperty_SectorSize = 4,             //!< Tag used to retrieve sector size in term of byte
+    kQspiFlashProperty_BlockSize = 5,              //!< Tag used to retrieve block size in terms of byte
+
+    kQspiFlashProperty_TotalFlashSize = 0x10, //!< Tag used to retrieve total flash size in terms of byte
+} qspiflash_property_t;
+
+//! @brief Endianess supported by QSPI module
+typedef enum _qspi_endianness
+{
+    kQspiEndianess_64BE = 0U, //!< 64-bit Big Endian
+    kQspiEndianess_32LE = 1U, //!< 32-bit Little Endian
+    kQspiEndianess_32BE = 2U, //!< 32-bit Big Endian
+    kQspiEndianess_64LE = 3U, //!< 64-bit Little Endian
+} qspi_endianess_t;
+
+//! @brief Port Enablement Option
+typedef enum _qspi_port_enable
+{
+    kQspiPort_EnablePortA = 0U,    //!< Only PORTA is enabled
+    kQspiPort_EnableBothPorts = 1, //!< Enable Both PoartA and PortB
+} qspi_port_enable_t;
+
+//! @brief Definition for AHB data tranfer size
+typedef enum _qspi_ahb_data_transfer_size
+{
+    kQspiAHBDataTransferSize_64Bytes = 8U,   //!< AHB data transfer size is 64bytes
+    kQspiAHBDataTransferSize_256Bytes = 32U, //!< AHB data transfer size is 256bytes
+    kQspiAHBDataTransferSize_512Bytes = 64U, //!< AHB data transfer size is 512bytes
+} qspi_ahb_data_transfer_size_t;
+
+//! @brief Error codes of QuadSPI driver
+typedef enum _qspiflash_status
+{
+    //! @brief Error code which represents that flash size is error
+    kStatus_QspiFlashSizeError = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 0),
+    //! @brief Error code which represents that start address for programming is not page aligned.
+    kStatus_QspiFlashAlignmentError = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 1),
+    //! @brief Error code which represents that the address is invalid
+    kStatus_QspiFlashAddressError = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 2),
+    //! @brief Error code which represents that the operation is not successfully executed.
+    kStatus_QspiFlashCommandFailure = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 3),
+    //! @brief Error code which represents that the property is not supported
+    kStatus_QspiFlashUnknownProperty = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 4),
+    //! @brief Error code which represents that qspi module is not configured yet.
+    kStatus_QspiNotConfigured = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 5),
+    //! @brief Error code which represents that a command is not supported under
+    //!        certain mode.
+    kStatus_QspiCommandNotSupported = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 6),
+    //! @brief Error code which represents that operation is timeout
+    kStatus_QspiCommandTimeout = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 7),
+
+    //! @brief Error code which represents that QSPI cannot perform write operation at expected frequency
+    kStatus_QspiWriteFailure = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 8),
+
+    //! @brief Error code which represents that the QSPI module is busy, which may be caused by incorrect
+    //        commands in LUT
+    kStatusQspiModuleBusy = MAKE_STATUS(kStatusGroup_QuadSPIDriver, 9),
+} qspiflash_status_t;
+
+//! @brief QuadSPI Config block structure
+typedef struct __sflash_configuration_parameter
+{
+    uint32_t tag;               //!< Set to magic number of 'kqcf'
+    standard_version_t version; //!< version of config struct
+                                //!< the version number i organized as following:
+    uint32_t lengthInBytes;     //!< Total length of strcut in bytes
+
+    uint32_t dqs_loopback;          //!< Sets DQS LoopBack Mode to enable Dummy Pad MCR[24]
+    uint32_t data_hold_time;        //!< Serial flash data In Hold time, valid value: 0/1/2
+    uint32_t reserved0[2];          //!< Reserved for K80
+    uint32_t device_mode_config_en; //!< Determine if it is required to config working mode of external spi flash.
+    uint32_t device_cmd;            //!< Command to be tranferred to device
+    uint32_t write_cmd_ipcr;        //!< IPCR value of Write command
+    uint32_t word_addressable;      //!< Determine if the serial flash is word addressable
+
+    uint32_t cs_hold_time;         //!< CS hold time in terms of serial clock.(for example 1 serial clock cyle)
+    uint32_t cs_setup_time;        //!< CS setup time in terms of serial clock.(for example 1 serial clock cyle)
+    uint32_t sflash_A1_size;       //!< Size of flash connected on QSPI0A Ports and QSPI0A_SS0, in terms of Bytes
+    uint32_t sflash_A2_size;       //!< Size of flash connected on QSPI0A Ports and QSPI0A_SS1, in terms of Bytes
+    uint32_t sflash_B1_size;       //!< Size of flash connected on QSPI0B Ports and QSPI0B_SS0, in terms of Bytes
+    uint32_t sflash_B2_size;       //!< Size of flash connected on QSPI0B Ports and QSPI0B_SS1, in terms of Bytes
+    uint32_t sclk_freq;            //!< In  00 - 24MHz, 01 - 48MHz, 10 - 96MHz,(only for SDR Mode)
+    uint32_t busy_bit_offset;      //!< Flash device busy bit offset in status register
+    uint32_t sflash_type;          //!< SPI flash type: 0-Single,1--Dual 2--Quad, 3-- Octal
+    uint32_t sflash_port;          //!< 0--Only Port-A, 1--Both PortA and PortB
+    uint32_t ddr_mode_enable;      //!< Enable DDR mode if set to TRUE
+    uint32_t dqs_enable;           //!< Enable DQS mode if set to TRUE.
+    uint32_t parallel_mode_enable; //!< Enable Individual or parrallel mode.
+    uint32_t portA_cs1;            //!< Enable PORTA CS1
+    uint32_t portB_cs1;            //!< Enable PORTB CS1
+    uint32_t fsphs;                //!< Full speed delay selection for SDR instructions
+    uint32_t fsdly;                //!< Full speed phase selection for SDR instructions
+    uint32_t ddrsmp;               //!< Select the sampling point for incomming data when serial flash is in DDR mdoe
+    uint32_t
+        look_up_table[QSPI_LUT_MAX_ENTRIES]; //!< Set of seq to perform optimum read on SFLASH as as per vendor SFLASH
+    uint32_t column_address_space;           //!< The width of the column address
+    uint32_t config_cmd_en;                  //!< Enable config commands
+    uint32_t config_cmds[QSPI_PRE_CMD_CNT];  //!< Config comands, used to configure nor flash
+    uint32_t config_cmds_args[QSPI_PRE_CMD_CNT]; //!< Config commands arguments
+    uint32_t differential_clock_pin_enable;      //!< Differential flash clock pins enable
+    uint32_t flash_CK2_clock_pin_enable;         //!< Flash CK2 clock pin enable
+    uint32_t dqs_inverse_sel;                    //!< Select clock source for internal DQS generation
+    uint32_t dqs_latency_enable;                 //!< DQS Latency Enable
+    uint32_t dqs_loopback_internal;              //!< 0: dqs loopback from pad, 1: dqs loopback internally
+    uint32_t dqs_phase_sel;                      //!< dqs phase sel
+    uint32_t dqs_fa_delay_chain_sel;             //!< dqs fa delay chain selection
+    uint32_t dqs_fb_delay_chain_sel;             //!< dqs fb delay chain selection
+    uint32_t reserved1[2];                       //!< reserved
+    uint32_t pagesize;                           //!< page Size of Serial Flash
+    uint32_t sectorsize;                         //!< sector Size of Serial Flash
+
+    uint32_t timeout_milliseconds; //!< timeout in terms of millisecond in case of infinite loop in qspi driver
+                                   //!<  0 represents disabling timeout check. This value is valid since version 1.1.0
+    uint32_t ips_command_second_divider; //!< second devider for all IPS commands.
+    uint32_t need_multi_phases;          //!< Determine if multiple hases command are needed.
+    uint32_t is_spansion_hyperflash;     //!< Determine if connected spi flash device belongs to Hyperflash family
+    uint32_t pre_read_status_cmd_address_offset; //!< Address for PreReadStatus command
+    uint32_t pre_unlock_cmd_address_offset;      //!< Address for PreWriteEnable command
+    uint32_t unlock_cmd_address_offset;          //!< Address for WriteEnable command
+    uint32_t pre_program_cmd_address_offset;     //!< Address for PreProgram command
+    uint32_t pre_erase_cmd_address_offset;       //!< Address for PreErase command
+    uint32_t erase_all_cmd_address_offset;       //!< Address for EraseAll command
+    uint32_t reserved2[3];                       //!< Reserved words to make sure qspi config block is page-aligend.
+
+} qspi_config_t, *SFLASH_CONFIGURATION_PARAM_PTR;
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @brief Get Property from QSPI driver
+//!
+//! This function is used to retrieve qspi related properties
+//!
+//! @param wichProperty     Property tag
+//! @param value  Pointer which is used to return the propery value
+//!
+//! @return An error code or kStatus_Success
+status_t quadspi_get_property(uint32_t whichProperty, uint32_t *value);
+
+//! @brief Page program to external spi flash
+//!
+//! This function programs certain length of data to expected address according
+//! to parameters passed in
+//!
+//! @param dst_addr Destination Address to be programmed
+//! @param src  Data to be programmed
+//! @param lengthInBytes Size of data to be programmed
+//!
+//! @return An error code or kStatus_Success
+status_t quadspi_page_program(uint32_t dst_addr, const uint32_t *src, uint32_t lengthInBytes);
+
+//! @brief Intialize QSPI module according to parameters passed in
+//!
+//! This function intializes and configures QuadSPI module according to the
+//! pointer which points to quad spi config block
+//!
+//! @param config_base Base address of a quadspi config block
+//!
+//! @return An error code or kStatus_Success
+status_t quadspi_init(qspi_config_t *config_base);
+
+//! @brief Get the status of quadspi configuration
+//!
+//! This function return True or False which represents the QuadSPI module is
+//! successfully configured or not configured yet respectively.
+//!
+//! @return true or false
+bool is_quadspi_configured(void);
+
+//! @brief Configure pinmux of QSPI module according to parameters passed in
+//!
+//! This function configures pinmux for QSPI modules dynamically according to
+//! the pointer which points to a qspi config block.
+//! This function is target-specific, should be implemented in BSP.
+//!
+//! @param config_base A pointer which points to a qspi config block
+//!
+//! @return An error code or kStatus_Success
+extern status_t quadspi_iomux_configuration(qspi_config_t *config_base);
+
+//! @brief Configure QSPI serial clock frquency
+//!
+//! This function configures the serial clock frequency of QSPI module according
+//! to the expected option.
+//! This function is target-specific, should be implemented in BSP.
+//!
+//! @param freq enumerated variable represent serial clock frequency
+extern void quadspi_serial_clock_configure(qspi_serial_clock_freq_t freq);
+
+//! @brief Erase the entire spi flash devices
+//!
+//! @return An error code or kStatus_Success
+status_t quadspi_erase_all(void);
+
+//! @brief Erase one sector from the provided address
+//!
+//! @param address The start address of the sector to be erased.
+//!
+//! @return An error code or kStatus_Success
+status_t quadspi_erase_sector(uint32_t address);
+
+//! @brief Flush QSPI cache
+//!
+//! @return kStatus_Success
+status_t quadspi_cache_clear(void);
+
+#if defined(__cplusplus)
+}
+
+/*! @}*/
+
+#endif // #ifndef __QSPI_H__
+
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/smc/smc.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013-14, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * File:        smc.h
+ * Purpose:     Provides low power mode entry routines
+ *
+ * Notes:
+ */
+
+#ifndef __SMC_H__
+#define __SMC_H__
+
+/********************************************************************/
+
+// function prototypes
+void sleep(void);
+void deepsleep(void);
+void enter_wait(void);
+void enter_stop(uint8_t partial_stop_opt);
+int32_t enter_vlpr(void);
+void exit_vlpr(void);
+void enter_vlps(void);
+#if !defined(CPU_PKE18F512VLH15)
+void enter_lls(void);
+void enter_vlls3(void);
+void enter_vlls2(void);
+void enter_vlls1(void);
+#endif
+void enter_vlls0(uint8_t PORPO_value);
+void enter_vlls0_nopor(void);
+
+/********************************************************************/
+#endif /* __SMC_H__ */

src/drivers/systick/src/systick.c

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "systick/systick.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+static systick_hook_t systick_hook;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Initialize SysTick Module
+status_t systick_init(uint32_t ticks)
+{
+    if (ticks > SysTick_LOAD_RELOAD_Msk)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+    SysTick->VAL = 0;                                      /* Load the SysTick Counter Value */
+    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk |
+                    SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+    return kStatus_Success;
+}
+
+//! @brief Set Systick IRQ hook.
+void systick_set_hook(systick_hook_t hook)
+{
+    systick_hook = hook;
+}
+
+//! @brief Shutdown Systick timer and interrupts
+void systick_shutdown(void)
+{
+    // Disable the timer and interrupts from it
+    SysTick->CTRL = SysTick->CTRL & ~(SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk);
+}
+
+//! @brief SysTick interrupt handler
+void SysTick_Handler(void)
+{
+    if (systick_hook)
+    {
+        systick_hook();
+    }
+}

src/drivers/systick/systick.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+#include "bootloader_common.h"
+#include "fsl_device_registers.h"
+
+//! @addtogroup systick_driver
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+typedef void (*systick_hook_t)(void);
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif // __cplusplus
+
+/*!
+ * @brief Systick Initialization
+ * @param ticks Number of ticks between two interrupts
+ *
+ * @return kStatus_InvalidArgument or kStatus_Success
+ */
+status_t systick_init(uint32_t ticks);
+
+/*!
+ * @brief Set Hook for Systick IRQ
+ * @param hook Hook to be called in Systick IRQ handler
+ */
+void systick_set_hook(systick_hook_t hook);
+
+/*!
+ * @brief Disable Systick Timer and Interrupt
+ */
+void systick_shutdown(void);
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+
+//@}
+
+#endif // __SYSTICK_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/watchdog/fsl_watchdog.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_WATCHDOG__
+#define __FSL_WATCHDOG__
+
+#include "bootloader_common.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @name Watchdog
+//@{
+
+//! @brief Initializes the Watchdog module.
+void fsl_watchdog_init(void);
+
+//! @brief Deinitializes the device.
+//!
+//! Clears the control register and turns off the clock to the module.
+void fsl_watchdog_deinit(void);
+
+//! @brief Service the watchdog module.
+void fsl_watchdog_service(void);
+
+//@}
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // ifndef __FSL_WATCHDOG__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/watchdog/src/fsl_watchdog_cop.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "watchdog/fsl_watchdog.h"
+#include "microseconds/microseconds.h"
+#include "bootloader_common.h"
+#include "utilities/fsl_rtos_abstraction.h"
+#include "utilities/fsl_assert.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+//! @brief Initializes the Watchdog module.
+void fsl_watchdog_init(void)
+{
+}
+
+//! @brief Deinitializes the device.
+//!
+//! Clears the control register and turns off the clock to the module.
+void fsl_watchdog_deinit(void)
+{
+    fsl_watchdog_service();
+}
+
+//! @brief Service the watchdog module.
+void fsl_watchdog_service(void)
+{
+    SIM->SRVCOP = 0x55;
+    SIM->SRVCOP = 0xAA;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

src/drivers/wdog32/fsl_wdog32.c

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_wdog32.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask)
+{
+    if (mask & kWDOG32_InterruptFlag)
+    {
+        base->CS |= WDOG_CS_FLG_MASK;
+    }
+}
+
+void WDOG32_GetDefaultConfig(wdog32_config_t *config)
+{
+    assert(config);
+
+    config->enableWdog32 = true;
+    config->clockSource = kWDOG32_ClockSource1;
+    config->prescaler = kWDOG32_ClockPrescalerDivide1;
+    config->workMode.enableWait = true;
+    config->workMode.enableStop = false;
+    config->workMode.enableDebug = false;
+    config->testMode = kWDOG32_TestModeDisabled;
+    config->enableUpdate = true;
+    config->enableInterrupt = false;
+    config->enableWindowMode = false;
+    config->windowValue = 0U;
+    config->timeoutValue = 0xFFFFU;
+}
+
+void WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config)
+{
+    assert(config);
+
+    uint32_t value = 0U;
+    uint32_t primaskValue = 0U;
+
+    value = WDOG_CS_EN(config->enableWdog32) | WDOG_CS_CLK(config->clockSource) | WDOG_CS_INT(config->enableInterrupt) |
+            WDOG_CS_WIN(config->enableWindowMode) | WDOG_CS_UPDATE(config->enableUpdate) |
+            WDOG_CS_DBG(config->workMode.enableDebug) | WDOG_CS_STOP(config->workMode.enableStop) |
+            WDOG_CS_WAIT(config->workMode.enableWait) | WDOG_CS_PRES(config->prescaler) | WDOG_CS_CMD32EN(true) |
+            WDOG_CS_TST(config->testMode);
+
+    /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence
+     * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */
+    primaskValue = DisableGlobalIRQ();
+    WDOG32_Unlock(base);
+    base->WIN = config->windowValue;
+    base->TOVAL = config->timeoutValue;
+    base->CS = value;
+    EnableGlobalIRQ(primaskValue);
+}
+void WDOG32_Deinit(WDOG_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupts */
+    primaskValue = DisableGlobalIRQ();
+    WDOG32_Unlock(base);
+    WDOG32_Disable(base);
+    EnableGlobalIRQ(primaskValue);
+}

src/drivers/wdog32/fsl_wdog32.h

@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_WDOG32_H_
+#define _FSL_WDOG32_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup wdog32_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief WDOG32 driver version. */
+#define FSL_WDOG32_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+
+/*! @brief Describes WDOG32 clock source. */
+typedef enum _wdog32_clock_source
+{
+    kWDOG32_ClockSource0 = 0U, /*!< Clock source 0 */
+    kWDOG32_ClockSource1 = 1U, /*!< Clock source 1 */
+    kWDOG32_ClockSource2 = 2U, /*!< Clock source 2 */
+    kWDOG32_ClockSource3 = 3U, /*!< Clock source 3 */
+} wdog32_clock_source_t;
+
+/*! @brief Describes the selection of the clock prescaler. */
+typedef enum _wdog32_clock_prescaler
+{
+    kWDOG32_ClockPrescalerDivide1 = 0x0U,   /*!< Divided by 1 */
+    kWDOG32_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */
+} wdog32_clock_prescaler_t;
+
+/*! @brief Defines WDOG32 work mode. */
+typedef struct _wdog32_work_mode
+{
+    bool enableWait;  /*!< Enables or disables WDOG32 in wait mode */
+    bool enableStop;  /*!< Enables or disables WDOG32 in stop mode */
+    bool enableDebug; /*!< Enables or disables WDOG32 in debug mode */
+} wdog32_work_mode_t;
+
+/*! @brief Describes WDOG32 test mode. */
+typedef enum _wdog32_test_mode
+{
+    kWDOG32_TestModeDisabled = 0U, /*!< Test Mode diabled */
+    kWDOG32_UserModeEnabled = 1U,  /*!< User Mode enabled */
+    kWDOG32_LowByteTest = 2U,      /*!< Test Mode enabled, only low byte is used */
+    kWDOG32_HighByteTest = 3U,     /*!< Test Mode enabled, only high byte is used */
+} wdog32_test_mode_t;
+
+/*! @brief Describes WDOG32 configuration structure. */
+typedef struct _wdog32_config
+{
+    bool enableWdog32;                  /*!< Enables or disables WDOG32 */
+    wdog32_clock_source_t clockSource;  /*!< Clock source select */
+    wdog32_clock_prescaler_t prescaler; /*!< Clock prescaler value */
+    wdog32_work_mode_t workMode;        /*!< Configures WDOG32 work mode in debug stop and wait mode */
+    wdog32_test_mode_t testMode;        /*!< Configures WDOG32 test mode */
+    bool enableUpdate;                  /*!< Update write-once register enable */
+    bool enableInterrupt;               /*!< Enables or disables WDOG32 interrupt */
+    bool enableWindowMode;              /*!< Enables or disables WDOG32 window mode */
+    uint16_t windowValue;               /*!< Window value */
+    uint16_t timeoutValue;              /*!< Timeout value */
+} wdog32_config_t;
+
+/*!
+ * @brief WDOG32 interrupt configuration structure.
+ *
+ * This structure contains the settings for all of the WDOG32 interrupt configurations.
+ */
+enum _wdog32_interrupt_enable_t
+{
+    kWDOG32_InterruptEnable = WDOG_CS_INT_MASK, /*!< Interrupt will be generated before forcing a reset */
+};
+
+/*!
+ * @brief WDOG32 status flags.
+ *
+ * This structure contains the WDOG32 status flags for use in the WDOG32 functions.
+ */
+enum _wdog32_status_flags_t
+{
+    kWDOG32_RunningFlag = WDOG_CS_EN_MASK,    /*!< Running flag, set when WDOG32 is enabled */
+    kWDOG32_InterruptFlag = WDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */
+};
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name WDOG32 Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes WDOG32 configure sturcture.
+ *
+ * This function initializes the WDOG32 configure structure to default value. The default
+ * value are:
+ * @code
+ *   wdog32Config->enableWdog32 = true;
+ *   wdog32Config->clockSource = kWDOG32_ClockSource1;
+ *   wdog32Config->prescaler = kWDOG32_ClockPrescalerDivide1;
+ *   wdog32Config->workMode.enableWait = true;
+ *   wdog32Config->workMode.enableStop = false;
+ *   wdog32Config->workMode.enableDebug = false;
+ *   wdog32Config->testMode = kWDOG32_TestModeDisabled;
+ *   wdog32Config->enableUpdate = true;
+ *   wdog32Config->enableInterrupt = false;
+ *   wdog32Config->enableWindowMode = false;
+ *   wdog32Config->windowValue = 0U;
+ *   wdog32Config->timeoutValue = 0xFFFFU;
+ * @endcode
+ *
+ * @param config Pointer to WDOG32 config structure.
+ * @see wdog32_config_t
+ */
+void WDOG32_GetDefaultConfig(wdog32_config_t *config);
+
+/*!
+ * @brief Initializes WDOG32 module.
+ *
+ * This function is used to initializes WDOG32.
+ * If user wants to reconfigure WDOG32 without forcing a reset first, enableUpdate must be set to true
+ * in configuration.
+ *
+ * Example:
+ * @code
+ *   wdog32_config_t config;
+ *   WDOG32_GetDefaultConfig(&config);
+ *   config.timeoutValue = 0x7ffU;
+ *   config.enableUpdate = true;
+ *   WDOG32_Init(wdog_base,&config);
+ * @endcode
+ *
+ * @param base   WDOG32 peripheral base address
+ * @param config The configuration of WDOG32
+ */
+void WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config);
+
+/*!
+ * @brief De-initializes WDOG32 module.
+ *
+ * This function shuts down the WDOG32.
+ * Make sure that the WDOG_CS.UPDATE is 1 which means that the register update is enabled.
+ *
+ * @param base   WDOG32 peripheral base address
+ */
+void WDOG32_Deinit(WDOG_Type *base);
+
+/* @} */
+
+/*!
+ * @name WDOG32 functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables WDOG32 module.
+ *
+ * This function write value into WDOG_CS register to enable WDOG32.
+ * WDOG_CS register is a write-once register, make sure the WCT window is still open and
+ * this register has not been written in this WCT while this function is called.
+ *
+ * @param base WDOG32 peripheral base address
+ */
+static inline void WDOG32_Enable(WDOG_Type *base)
+{
+    base->CS |= WDOG_CS_EN_MASK;
+}
+
+/*!
+ * @brief Disables WDOG32 module.
+ *
+ * This function write value into WDOG_CS register to disable WDOG32.
+ * WDOG_CS register is a write-once register, make sure the WCT window is still open and
+ * this register has not been written in this WCT while this function is called.
+ *
+ * @param base WDOG32 peripheral base address
+ */
+static inline void WDOG32_Disable(WDOG_Type *base)
+{
+    base->CS &= ~WDOG_CS_EN_MASK;
+}
+
+/*!
+ * @brief Enable WDOG32 interrupt.
+ *
+ * This function write value into WDOG_CS register to enable the WDOG32 interrupt.
+ * WDOG_CS register is a write-once register, make sure the WCT window is still open and
+ * this register has not been written in this WCT while this function is called.
+ *
+ * @param base WDOG32 peripheral base address
+ * @param mask The interrupts to enable
+ *        The parameter can be combination of the following source if defined:
+ *        @arg kWDOG32_InterruptEnable
+ */
+static inline void WDOG32_EnableInterrupts(WDOG_Type *base, uint32_t mask)
+{
+    base->CS |= mask;
+}
+
+/*!
+ * @brief Disable WDOG32 interrupt.
+ *
+ * This function write value into WDOG_CS register to disable the WDOG32 interrupt.
+ * WDOG_CS register is a write-once register, make sure the WCT window is still open and
+ * this register has not been written in this WCT while this function is called.
+ *
+ * @param base WDOG32 peripheral base address
+ * @param mask The interrupts to disable
+ *        The parameter can be combination of the following source if defined:
+ *        @arg kWDOG32_InterruptEnable
+ */
+static inline void WDOG32_DisableInterrupts(WDOG_Type *base, uint32_t mask)
+{
+    base->CS &= ~mask;
+}
+
+/*!
+ * @brief Gets WDOG32 all status flags.
+ *
+ * This function gets all status flags.
+ *
+ * Example for getting Running Flag:
+ * @code
+ *   uint32_t status;
+ *   status = WDOG32_GetStatusFlags(wdog_base) & kWDOG32_RunningFlag;
+ * @endcode
+ * @param base        WDOG32 peripheral base address
+ * @return            State of the status flag: asserted (true) or not-asserted (false).@see _wdog32_status_flags_t
+ *                    - true: related status flag has been set.
+ *                    - false: related status flag is not set.
+ */
+uint32_t inline WDOG32_GetStatusFlags(WDOG_Type *base)
+{
+    return (base->CS & (WDOG_CS_EN_MASK | WDOG_CS_FLG_MASK));
+}
+
+/*!
+ * @brief Clear WDOG32 flag.
+ *
+ * This function clears WDOG32 status flag.
+ *
+ * Example for clearing interrupt flag:
+ * @code
+ *   WDOG32_ClearStatusFlags(wdog_base,kWDOG32_InterruptFlag);
+ * @endcode
+ * @param base        WDOG32 peripheral base address
+ * @param mask        The status flags to clear.
+ *                    The parameter could be any combination of the following values:
+ *                    @arg kWDOG32_InterruptFlag
+ */
+void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask);
+
+/*!
+ * @brief Set the WDOG32 timeout value.
+ *
+ * This function write timeout value into WDOG_TOVAL register.
+ * WDOG_TOVAL register is a write-once register, make sure the WCT window is still open and
+ * this register has not been written in this WCT while this function is called.
+ *
+ * @param base WDOG32 peripheral base address
+ * @param timeoutCount WDOG32 timeout value, count of WDOG32 clock tick.
+ */
+static inline void WDOG32_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)
+{
+    base->TOVAL = timeoutCount;
+}
+
+/*!
+ * @brief Sets the WDOG32 window value.
+ *
+ * This function write window value into WDOG_WIN register.
+ * WDOG_WIN register is a write-once register, make sure the WCT window is still open and
+ * this register has not been written in this WCT while this function is called.
+ *
+ * @param base WDOG32 peripheral base address
+ * @param windowValue WDOG32 window value.
+ */
+static inline void WDOG32_SetWindowValue(WDOG_Type *base, uint16_t windowValue)
+{
+    base->WIN = windowValue;
+}
+
+/*!
+ * @brief Unlocks the WDOG32 register written.
+ *
+ * This function unlocks the WDOG32 register written.
+ *
+ * Before starting the unlock sequence and following congfiguration, disable the global interrupts.
+ * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire,
+ * After the configuration finishes, re-enable the global interrupts.
+ *
+ * @param base WDOG32 peripheral base address
+ */
+static inline void WDOG32_Unlock(WDOG_Type *base)
+{
+    base->CNT = WDOG_UPDATE_KEY;
+}
+
+/*!
+ * @brief Refreshes the WDOG32 timer.
+ *
+ * This function feeds the WDOG32.
+ * This function should be called before watchdog timer is in timeout. Otherwise, a reset is asserted.
+ *
+ * @param base WDOG32 peripheral base address
+ */
+static inline void WDOG32_Refresh(WDOG_Type *base)
+{
+    base->CNT = WDOG_REFRESH_KEY;
+}
+
+/*!
+ * @brief Gets WDOG32 counter value.
+ *
+ * This function gets the WDOG32 counter value.
+ *
+ * @param base WDOG32 peripheral base address
+ * @return     Current WDOG32 counter value
+ */
+static inline uint16_t WDOG32_GetCounterValue(WDOG_Type *base)
+{
+    return base->CNT;
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_WDOG32_H_ */