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KSDK_2.0_MKL03Z8xxx4/devices/MKL03Z4/MKL03Z4.h
László Monda 183142d667 Add KSDK and readme.
2016-08-09 18:02:18 +02:00

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/*
** ###################################################################
** Processors: MKL03Z16VFG4
** MKL03Z16VFK4
** MKL03Z32CAF4
** MKL03Z32VFG4
** MKL03Z32VFK4
** MKL03Z8VFG4
** MKL03Z8VFK4
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL03P24M48SF0RM, Rev 2, Apr 2014
** Version: rev. 1.4, 2014-08-28
** Build: b160126
**
** Abstract:
** CMSIS Peripheral Access Layer for MKL03Z4
**
** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-12-11)
** Initial version.
** - rev. 1.1 (2014-04-16)
** Update of the I2C module (SMBUS feature).
** Update of the MCG_Light module.
** Added register file system (RFSYS).
** - rev. 1.2 (2014-04-30)
** PEx compatibility macros has been added.
** - rev. 1.3 (2014-06-27)
** I2C_S1 register was renamed.
** GPIO - Modules PTA,PTB renamed to GPIOA,GPIOB.
** - rev. 1.4 (2014-08-28)
** Update of system files - default clock configuration changed.
** Update of startup files - possibility to override DefaultISR added.
**
** ###################################################################
*/
/*!
* @file MKL03Z4.h
* @version 1.4
* @date 2014-08-28
* @brief CMSIS Peripheral Access Layer for MKL03Z4
*
* CMSIS Peripheral Access Layer for MKL03Z4
*/
#ifndef _MKL03Z4_H_
#define _MKL03Z4_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0100U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0004U
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Auxiliary constants */
NotAvail_IRQn = -128, /**< Not available device specific interrupt */
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
/* Device specific interrupts */
Reserved16_IRQn = 0, /**< Reserved interrupt */
Reserved17_IRQn = 1, /**< Reserved interrupt */
Reserved18_IRQn = 2, /**< Reserved interrupt */
Reserved19_IRQn = 3, /**< Reserved interrupt */
Reserved20_IRQn = 4, /**< Reserved interrupt */
FTFA_IRQn = 5, /**< Command complete and read collision */
PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
LLWU_IRQn = 7, /**< Low leakage wakeup */
I2C0_IRQn = 8, /**< I2C0 interrupt */
Reserved25_IRQn = 9, /**< Reserved interrupt */
SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
Reserved27_IRQn = 11, /**< Reserved interrupt */
LPUART0_IRQn = 12, /**< LPUART0 status and error */
Reserved29_IRQn = 13, /**< Reserved interrupt */
Reserved30_IRQn = 14, /**< Reserved interrupt */
ADC0_IRQn = 15, /**< ADC0 interrupt */
CMP0_IRQn = 16, /**< CMP0 interrupt */
TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
Reserved35_IRQn = 19, /**< Reserved interrupt */
RTC_IRQn = 20, /**< RTC alarm */
RTC_Seconds_IRQn = 21, /**< RTC seconds */
Reserved38_IRQn = 22, /**< Reserved interrupt */
Reserved39_IRQn = 23, /**< Reserved interrupt */
Reserved40_IRQn = 24, /**< Reserved interrupt */
Reserved41_IRQn = 25, /**< Reserved interrupt */
Reserved42_IRQn = 26, /**< Reserved interrupt */
Reserved43_IRQn = 27, /**< Reserved interrupt */
LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
Reserved45_IRQn = 29, /**< Reserved interrupt */
PORTA_IRQn = 30, /**< PORTA Pin detect */
PORTB_IRQn = 31 /**< PORTB Pin detect */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M0 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm0plus.h" /* Core Peripheral Access Layer */
#include "system_MKL03Z4.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Mapping Information
---------------------------------------------------------------------------- */
/*!
* @addtogroup Mapping_Information Mapping Information
* @{
*/
/** Mapping Information */
/*!
* @}
*/ /* end of group Mapping_Information */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
__IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
__I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
__IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
__IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
__IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
__IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
__IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
__IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
uint8_t RESERVED_0[4];
__IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
__IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
__IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
__IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
__IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
__IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
__IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/*! @name SC1 - ADC Status and Control Registers 1 */
#define ADC_SC1_ADCH_MASK (0x1FU)
#define ADC_SC1_ADCH_SHIFT (0U)
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
#define ADC_SC1_AIEN_MASK (0x40U)
#define ADC_SC1_AIEN_SHIFT (6U)
#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
#define ADC_SC1_COCO_MASK (0x80U)
#define ADC_SC1_COCO_SHIFT (7U)
#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
/* The count of ADC_SC1 */
#define ADC_SC1_COUNT (2U)
/*! @name CFG1 - ADC Configuration Register 1 */
#define ADC_CFG1_ADICLK_MASK (0x3U)
#define ADC_CFG1_ADICLK_SHIFT (0U)
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK (0xCU)
#define ADC_CFG1_MODE_SHIFT (2U)
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK (0x10U)
#define ADC_CFG1_ADLSMP_SHIFT (4U)
#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
#define ADC_CFG1_ADIV_MASK (0x60U)
#define ADC_CFG1_ADIV_SHIFT (5U)
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK (0x80U)
#define ADC_CFG1_ADLPC_SHIFT (7U)
#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
/*! @name CFG2 - ADC Configuration Register 2 */
#define ADC_CFG2_ADLSTS_MASK (0x3U)
#define ADC_CFG2_ADLSTS_SHIFT (0U)
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK (0x4U)
#define ADC_CFG2_ADHSC_SHIFT (2U)
#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
#define ADC_CFG2_ADACKEN_MASK (0x8U)
#define ADC_CFG2_ADACKEN_SHIFT (3U)
#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
#define ADC_CFG2_MUXSEL_MASK (0x10U)
#define ADC_CFG2_MUXSEL_SHIFT (4U)
#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
/*! @name R - ADC Data Result Register */
#define ADC_R_D_MASK (0xFFFFU)
#define ADC_R_D_SHIFT (0U)
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
/* The count of ADC_R */
#define ADC_R_COUNT (2U)
/*! @name CV1 - Compare Value Registers */
#define ADC_CV1_CV_MASK (0xFFFFU)
#define ADC_CV1_CV_SHIFT (0U)
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
/*! @name CV2 - Compare Value Registers */
#define ADC_CV2_CV_MASK (0xFFFFU)
#define ADC_CV2_CV_SHIFT (0U)
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
/*! @name SC2 - Status and Control Register 2 */
#define ADC_SC2_REFSEL_MASK (0x3U)
#define ADC_SC2_REFSEL_SHIFT (0U)
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
#define ADC_SC2_ACREN_MASK (0x8U)
#define ADC_SC2_ACREN_SHIFT (3U)
#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
#define ADC_SC2_ACFGT_MASK (0x10U)
#define ADC_SC2_ACFGT_SHIFT (4U)
#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
#define ADC_SC2_ACFE_MASK (0x20U)
#define ADC_SC2_ACFE_SHIFT (5U)
#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
#define ADC_SC2_ADTRG_MASK (0x40U)
#define ADC_SC2_ADTRG_SHIFT (6U)
#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
#define ADC_SC2_ADACT_MASK (0x80U)
#define ADC_SC2_ADACT_SHIFT (7U)
#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
/*! @name SC3 - Status and Control Register 3 */
#define ADC_SC3_AVGS_MASK (0x3U)
#define ADC_SC3_AVGS_SHIFT (0U)
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK (0x4U)
#define ADC_SC3_AVGE_SHIFT (2U)
#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
#define ADC_SC3_ADCO_MASK (0x8U)
#define ADC_SC3_ADCO_SHIFT (3U)
#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
#define ADC_SC3_CALF_MASK (0x40U)
#define ADC_SC3_CALF_SHIFT (6U)
#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
#define ADC_SC3_CAL_MASK (0x80U)
#define ADC_SC3_CAL_SHIFT (7U)
#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
/*! @name OFS - ADC Offset Correction Register */
#define ADC_OFS_OFS_MASK (0xFFFFU)
#define ADC_OFS_OFS_SHIFT (0U)
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
/*! @name PG - ADC Plus-Side Gain Register */
#define ADC_PG_PG_MASK (0xFFFFU)
#define ADC_PG_PG_SHIFT (0U)
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
#define ADC_CLPD_CLPD_MASK (0x3FU)
#define ADC_CLPD_CLPD_SHIFT (0U)
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
#define ADC_CLPS_CLPS_MASK (0x3FU)
#define ADC_CLPS_CLPS_SHIFT (0U)
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP4_CLP4_MASK (0x3FFU)
#define ADC_CLP4_CLP4_SHIFT (0U)
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP3_CLP3_MASK (0x1FFU)
#define ADC_CLP3_CLP3_SHIFT (0U)
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP2_CLP2_MASK (0xFFU)
#define ADC_CLP2_CLP2_SHIFT (0U)
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP1_CLP1_MASK (0x7FU)
#define ADC_CLP1_CLP1_SHIFT (0U)
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP0_CLP0_MASK (0x3FU)
#define ADC_CLP0_CLP0_SHIFT (0U)
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { ADC0_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { ADC0 }
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS { ADC0_IRQn }
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Register Layout Typedef */
typedef struct {
__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/*! @name CR0 - CMP Control Register 0 */
#define CMP_CR0_HYSTCTR_MASK (0x3U)
#define CMP_CR0_HYSTCTR_SHIFT (0U)
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK (0x70U)
#define CMP_CR0_FILTER_CNT_SHIFT (4U)
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
/*! @name CR1 - CMP Control Register 1 */
#define CMP_CR1_EN_MASK (0x1U)
#define CMP_CR1_EN_SHIFT (0U)
#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define CMP_CR1_OPE_MASK (0x2U)
#define CMP_CR1_OPE_SHIFT (1U)
#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define CMP_CR1_COS_MASK (0x4U)
#define CMP_CR1_COS_SHIFT (2U)
#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define CMP_CR1_INV_MASK (0x8U)
#define CMP_CR1_INV_SHIFT (3U)
#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define CMP_CR1_PMODE_MASK (0x10U)
#define CMP_CR1_PMODE_SHIFT (4U)
#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define CMP_CR1_TRIGM_MASK (0x20U)
#define CMP_CR1_TRIGM_SHIFT (5U)
#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
#define CMP_CR1_WE_MASK (0x40U)
#define CMP_CR1_WE_SHIFT (6U)
#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define CMP_CR1_SE_MASK (0x80U)
#define CMP_CR1_SE_SHIFT (7U)
#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
/*! @name FPR - CMP Filter Period Register */
#define CMP_FPR_FILT_PER_MASK (0xFFU)
#define CMP_FPR_FILT_PER_SHIFT (0U)
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
/*! @name SCR - CMP Status and Control Register */
#define CMP_SCR_COUT_MASK (0x1U)
#define CMP_SCR_COUT_SHIFT (0U)
#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define CMP_SCR_CFF_MASK (0x2U)
#define CMP_SCR_CFF_SHIFT (1U)
#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define CMP_SCR_CFR_MASK (0x4U)
#define CMP_SCR_CFR_SHIFT (2U)
#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define CMP_SCR_IEF_MASK (0x8U)
#define CMP_SCR_IEF_SHIFT (3U)
#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define CMP_SCR_IER_MASK (0x10U)
#define CMP_SCR_IER_SHIFT (4U)
#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
/*! @name DACCR - DAC Control Register */
#define CMP_DACCR_VOSEL_MASK (0x3FU)
#define CMP_DACCR_VOSEL_SHIFT (0U)
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK (0x40U)
#define CMP_DACCR_VRSEL_SHIFT (6U)
#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define CMP_DACCR_DACEN_MASK (0x80U)
#define CMP_DACCR_DACEN_SHIFT (7U)
#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/*! @name MUXCR - MUX Control Register */
#define CMP_MUXCR_MSEL_MASK (0x7U)
#define CMP_MUXCR_MSEL_SHIFT (0U)
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK (0x38U)
#define CMP_MUXCR_PSEL_SHIFT (3U)
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base address */
#define CMP0_BASE (0x40073000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { CMP0_BASE }
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS { CMP0 }
/** Interrupt vectors for the CMP peripheral type */
#define CMP_IRQS { CMP0_IRQn }
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FGPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
* @{
*/
/** FGPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} FGPIO_Type;
/* ----------------------------------------------------------------------------
-- FGPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
* @{
*/
/*! @name PDOR - Port Data Output Register */
#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
#define FGPIO_PDOR_PDO_SHIFT (0U)
#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
/*! @name PSOR - Port Set Output Register */
#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
#define FGPIO_PSOR_PTSO_SHIFT (0U)
#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
/*! @name PCOR - Port Clear Output Register */
#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
#define FGPIO_PCOR_PTCO_SHIFT (0U)
#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
/*! @name PTOR - Port Toggle Output Register */
#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
#define FGPIO_PTOR_PTTO_SHIFT (0U)
#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
/*! @name PDIR - Port Data Input Register */
#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
#define FGPIO_PDIR_PDI_SHIFT (0U)
#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
/*! @name PDDR - Port Data Direction Register */
#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
#define FGPIO_PDDR_PDD_SHIFT (0U)
#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group FGPIO_Register_Masks */
/* FGPIO - Peripheral instance base addresses */
/** Peripheral FGPIOA base address */
#define FGPIOA_BASE (0xF8000000u)
/** Peripheral FGPIOA base pointer */
#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
/** Peripheral FGPIOB base address */
#define FGPIOB_BASE (0xF8000040u)
/** Peripheral FGPIOB base pointer */
#define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
/** Array initializer of FGPIO peripheral base addresses */
#define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE }
/** Array initializer of FGPIO peripheral base pointers */
#define FGPIO_BASE_PTRS { FGPIOA, FGPIOB }
/*!
* @}
*/ /* end of group FGPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FTFA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
* @{
*/
/** FTFA - Register Layout Typedef */
typedef struct {
__IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
__IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
__I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
__I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
__IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
__IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
__IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
__IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
__IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
__IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
__IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
__IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
__IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
__IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
__IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
__IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
__IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
__IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
__IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
__IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
} FTFA_Type;
/* ----------------------------------------------------------------------------
-- FTFA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Masks FTFA Register Masks
* @{
*/
/*! @name FSTAT - Flash Status Register */
#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
#define FTFA_FSTAT_ACCERR_MASK (0x20U)
#define FTFA_FSTAT_ACCERR_SHIFT (5U)
#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
#define FTFA_FSTAT_CCIF_MASK (0x80U)
#define FTFA_FSTAT_CCIF_SHIFT (7U)
#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
/*! @name FCNFG - Flash Configuration Register */
#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
#define FTFA_FCNFG_CCIE_MASK (0x80U)
#define FTFA_FCNFG_CCIE_SHIFT (7U)
#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
/*! @name FSEC - Flash Security Register */
#define FTFA_FSEC_SEC_MASK (0x3U)
#define FTFA_FSEC_SEC_SHIFT (0U)
#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
#define FTFA_FSEC_FSLACC_MASK (0xCU)
#define FTFA_FSEC_FSLACC_SHIFT (2U)
#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
#define FTFA_FSEC_MEEN_MASK (0x30U)
#define FTFA_FSEC_MEEN_SHIFT (4U)
#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
#define FTFA_FSEC_KEYEN_MASK (0xC0U)
#define FTFA_FSEC_KEYEN_SHIFT (6U)
#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
/*! @name FOPT - Flash Option Register */
#define FTFA_FOPT_OPT_MASK (0xFFU)
#define FTFA_FOPT_OPT_SHIFT (0U)
#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
/*! @name FCCOB3 - Flash Common Command Object Registers */
#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
/*! @name FCCOB2 - Flash Common Command Object Registers */
#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
/*! @name FCCOB1 - Flash Common Command Object Registers */
#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
/*! @name FCCOB0 - Flash Common Command Object Registers */
#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
/*! @name FCCOB7 - Flash Common Command Object Registers */
#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
/*! @name FCCOB6 - Flash Common Command Object Registers */
#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
/*! @name FCCOB5 - Flash Common Command Object Registers */
#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
/*! @name FCCOB4 - Flash Common Command Object Registers */
#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
/*! @name FCCOBB - Flash Common Command Object Registers */
#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
/*! @name FCCOBA - Flash Common Command Object Registers */
#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
/*! @name FCCOB9 - Flash Common Command Object Registers */
#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
/*! @name FCCOB8 - Flash Common Command Object Registers */
#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
/*! @name FPROT3 - Program Flash Protection Registers */
#define FTFA_FPROT3_PROT_MASK (0xFFU)
#define FTFA_FPROT3_PROT_SHIFT (0U)
#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
/*! @name FPROT2 - Program Flash Protection Registers */
#define FTFA_FPROT2_PROT_MASK (0xFFU)
#define FTFA_FPROT2_PROT_SHIFT (0U)
#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
/*! @name FPROT1 - Program Flash Protection Registers */
#define FTFA_FPROT1_PROT_MASK (0xFFU)
#define FTFA_FPROT1_PROT_SHIFT (0U)
#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
/*! @name FPROT0 - Program Flash Protection Registers */
#define FTFA_FPROT0_PROT_MASK (0xFFU)
#define FTFA_FPROT0_PROT_SHIFT (0U)
#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
/*!
* @}
*/ /* end of group FTFA_Register_Masks */
/* FTFA - Peripheral instance base addresses */
/** Peripheral FTFA base address */
#define FTFA_BASE (0x40020000u)
/** Peripheral FTFA base pointer */
#define FTFA ((FTFA_Type *)FTFA_BASE)
/** Array initializer of FTFA peripheral base addresses */
#define FTFA_BASE_ADDRS { FTFA_BASE }
/** Array initializer of FTFA peripheral base pointers */
#define FTFA_BASE_PTRS { FTFA }
/** Interrupt vectors for the FTFA peripheral type */
#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
/*!
* @}
*/ /* end of group FTFA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} GPIO_Type;
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/*! @name PDOR - Port Data Output Register */
#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
#define GPIO_PDOR_PDO_SHIFT (0U)
#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
/*! @name PSOR - Port Set Output Register */
#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
#define GPIO_PSOR_PTSO_SHIFT (0U)
#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
/*! @name PCOR - Port Clear Output Register */
#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
#define GPIO_PCOR_PTCO_SHIFT (0U)
#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
/*! @name PTOR - Port Toggle Output Register */
#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
#define GPIO_PTOR_PTTO_SHIFT (0U)
#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
/*! @name PDIR - Port Data Input Register */
#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
#define GPIO_PDIR_PDI_SHIFT (0U)
#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
/*! @name PDDR - Port Data Direction Register */
#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
#define GPIO_PDDR_PDD_SHIFT (0U)
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIOA base address */
#define GPIOA_BASE (0x400FF000u)
/** Peripheral GPIOA base pointer */
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
/** Peripheral GPIOB base address */
#define GPIOB_BASE (0x400FF040u)
/** Peripheral GPIOB base pointer */
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { GPIOA, GPIOB }
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
* @{
*/
/** I2C - Register Layout Typedef */
typedef struct {
__IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
__IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
__IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
__IO uint8_t S; /**< I2C Status register 1, offset: 0x3 */
__IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
__IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
__IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
__IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
__IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
__IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
__IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
__IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
__IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
} I2C_Type;
/* ----------------------------------------------------------------------------
-- I2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2C_Register_Masks I2C Register Masks
* @{
*/
/*! @name A1 - I2C Address Register 1 */
#define I2C_A1_AD_MASK (0xFEU)
#define I2C_A1_AD_SHIFT (1U)
#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
/*! @name F - I2C Frequency Divider register */
#define I2C_F_ICR_MASK (0x3FU)
#define I2C_F_ICR_SHIFT (0U)
#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
#define I2C_F_MULT_MASK (0xC0U)
#define I2C_F_MULT_SHIFT (6U)
#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
/*! @name C1 - I2C Control Register 1 */
#define I2C_C1_WUEN_MASK (0x2U)
#define I2C_C1_WUEN_SHIFT (1U)
#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
#define I2C_C1_RSTA_MASK (0x4U)
#define I2C_C1_RSTA_SHIFT (2U)
#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
#define I2C_C1_TXAK_MASK (0x8U)
#define I2C_C1_TXAK_SHIFT (3U)
#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
#define I2C_C1_TX_MASK (0x10U)
#define I2C_C1_TX_SHIFT (4U)
#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
#define I2C_C1_MST_MASK (0x20U)
#define I2C_C1_MST_SHIFT (5U)
#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
#define I2C_C1_IICIE_MASK (0x40U)
#define I2C_C1_IICIE_SHIFT (6U)
#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
#define I2C_C1_IICEN_MASK (0x80U)
#define I2C_C1_IICEN_SHIFT (7U)
#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
/*! @name S - I2C Status register 1 */
#define I2C_S_RXAK_MASK (0x1U)
#define I2C_S_RXAK_SHIFT (0U)
#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
#define I2C_S_IICIF_MASK (0x2U)
#define I2C_S_IICIF_SHIFT (1U)
#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
#define I2C_S_SRW_MASK (0x4U)
#define I2C_S_SRW_SHIFT (2U)
#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
#define I2C_S_RAM_MASK (0x8U)
#define I2C_S_RAM_SHIFT (3U)
#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
#define I2C_S_ARBL_MASK (0x10U)
#define I2C_S_ARBL_SHIFT (4U)
#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
#define I2C_S_BUSY_MASK (0x20U)
#define I2C_S_BUSY_SHIFT (5U)
#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
#define I2C_S_IAAS_MASK (0x40U)
#define I2C_S_IAAS_SHIFT (6U)
#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
#define I2C_S_TCF_MASK (0x80U)
#define I2C_S_TCF_SHIFT (7U)
#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
/*! @name D - I2C Data I/O register */
#define I2C_D_DATA_MASK (0xFFU)
#define I2C_D_DATA_SHIFT (0U)
#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
/*! @name C2 - I2C Control Register 2 */
#define I2C_C2_AD_MASK (0x7U)
#define I2C_C2_AD_SHIFT (0U)
#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
#define I2C_C2_RMEN_MASK (0x8U)
#define I2C_C2_RMEN_SHIFT (3U)
#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
#define I2C_C2_SBRC_MASK (0x10U)
#define I2C_C2_SBRC_SHIFT (4U)
#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
#define I2C_C2_ADEXT_MASK (0x40U)
#define I2C_C2_ADEXT_SHIFT (6U)
#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
#define I2C_C2_GCAEN_MASK (0x80U)
#define I2C_C2_GCAEN_SHIFT (7U)
#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
/*! @name FLT - I2C Programmable Input Glitch Filter register */
#define I2C_FLT_FLT_MASK (0xFU)
#define I2C_FLT_FLT_SHIFT (0U)
#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
#define I2C_FLT_STARTF_MASK (0x10U)
#define I2C_FLT_STARTF_SHIFT (4U)
#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
#define I2C_FLT_SSIE_MASK (0x20U)
#define I2C_FLT_SSIE_SHIFT (5U)
#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
#define I2C_FLT_STOPF_MASK (0x40U)
#define I2C_FLT_STOPF_SHIFT (6U)
#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
#define I2C_FLT_SHEN_MASK (0x80U)
#define I2C_FLT_SHEN_SHIFT (7U)
#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
/*! @name RA - I2C Range Address register */
#define I2C_RA_RAD_MASK (0xFEU)
#define I2C_RA_RAD_SHIFT (1U)
#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
/*! @name SMB - I2C SMBus Control and Status register */
#define I2C_SMB_SHTF2IE_MASK (0x1U)
#define I2C_SMB_SHTF2IE_SHIFT (0U)
#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
#define I2C_SMB_SHTF2_MASK (0x2U)
#define I2C_SMB_SHTF2_SHIFT (1U)
#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
#define I2C_SMB_SHTF1_MASK (0x4U)
#define I2C_SMB_SHTF1_SHIFT (2U)
#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
#define I2C_SMB_SLTF_MASK (0x8U)
#define I2C_SMB_SLTF_SHIFT (3U)
#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
#define I2C_SMB_TCKSEL_MASK (0x10U)
#define I2C_SMB_TCKSEL_SHIFT (4U)
#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
#define I2C_SMB_SIICAEN_MASK (0x20U)
#define I2C_SMB_SIICAEN_SHIFT (5U)
#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
#define I2C_SMB_ALERTEN_MASK (0x40U)
#define I2C_SMB_ALERTEN_SHIFT (6U)
#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
#define I2C_SMB_FACK_MASK (0x80U)
#define I2C_SMB_FACK_SHIFT (7U)
#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
/*! @name A2 - I2C Address Register 2 */
#define I2C_A2_SAD_MASK (0xFEU)
#define I2C_A2_SAD_SHIFT (1U)
#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
/*! @name SLTH - I2C SCL Low Timeout Register High */
#define I2C_SLTH_SSLT_MASK (0xFFU)
#define I2C_SLTH_SSLT_SHIFT (0U)
#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
/*! @name SLTL - I2C SCL Low Timeout Register Low */
#define I2C_SLTL_SSLT_MASK (0xFFU)
#define I2C_SLTL_SSLT_SHIFT (0U)
#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
/*! @name S2 - I2C Status register 2 */
#define I2C_S2_EMPTY_MASK (0x1U)
#define I2C_S2_EMPTY_SHIFT (0U)
#define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
#define I2C_S2_ERROR_MASK (0x2U)
#define I2C_S2_ERROR_SHIFT (1U)
#define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
/*!
* @}
*/ /* end of group I2C_Register_Masks */
/* I2C - Peripheral instance base addresses */
/** Peripheral I2C0 base address */
#define I2C0_BASE (0x40066000u)
/** Peripheral I2C0 base pointer */
#define I2C0 ((I2C_Type *)I2C0_BASE)
/** Array initializer of I2C peripheral base addresses */
#define I2C_BASE_ADDRS { I2C0_BASE }
/** Array initializer of I2C peripheral base pointers */
#define I2C_BASE_PTRS { I2C0 }
/** Interrupt vectors for the I2C peripheral type */
#define I2C_IRQS { I2C0_IRQn }
/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LLWU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
* @{
*/
/** LLWU - Register Layout Typedef */
typedef struct {
__IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
__IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
__IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x2 */
__IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x3 */
__I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x4 */
__IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x5 */
} LLWU_Type;
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Masks LLWU Register Masks
* @{
*/
/*! @name PE1 - LLWU Pin Enable 1 register */
#define LLWU_PE1_WUPE0_MASK (0x3U)
#define LLWU_PE1_WUPE0_SHIFT (0U)
#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
#define LLWU_PE1_WUPE1_MASK (0xCU)
#define LLWU_PE1_WUPE1_SHIFT (2U)
#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
#define LLWU_PE1_WUPE2_MASK (0x30U)
#define LLWU_PE1_WUPE2_SHIFT (4U)
#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
#define LLWU_PE1_WUPE3_MASK (0xC0U)
#define LLWU_PE1_WUPE3_SHIFT (6U)
#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
/*! @name PE2 - LLWU Pin Enable 2 register */
#define LLWU_PE2_WUPE4_MASK (0x3U)
#define LLWU_PE2_WUPE4_SHIFT (0U)
#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
#define LLWU_PE2_WUPE5_MASK (0xCU)
#define LLWU_PE2_WUPE5_SHIFT (2U)
#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
#define LLWU_PE2_WUPE6_MASK (0x30U)
#define LLWU_PE2_WUPE6_SHIFT (4U)
#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
#define LLWU_PE2_WUPE7_MASK (0xC0U)
#define LLWU_PE2_WUPE7_SHIFT (6U)
#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
/*! @name ME - LLWU Module Enable register */
#define LLWU_ME_WUME0_MASK (0x1U)
#define LLWU_ME_WUME0_SHIFT (0U)
#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
#define LLWU_ME_WUME1_MASK (0x2U)
#define LLWU_ME_WUME1_SHIFT (1U)
#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
#define LLWU_ME_WUME2_MASK (0x4U)
#define LLWU_ME_WUME2_SHIFT (2U)
#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
#define LLWU_ME_WUME3_MASK (0x8U)
#define LLWU_ME_WUME3_SHIFT (3U)
#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
#define LLWU_ME_WUME4_MASK (0x10U)
#define LLWU_ME_WUME4_SHIFT (4U)
#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
#define LLWU_ME_WUME5_MASK (0x20U)
#define LLWU_ME_WUME5_SHIFT (5U)
#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
#define LLWU_ME_WUME6_MASK (0x40U)
#define LLWU_ME_WUME6_SHIFT (6U)
#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
#define LLWU_ME_WUME7_MASK (0x80U)
#define LLWU_ME_WUME7_SHIFT (7U)
#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
/*! @name F1 - LLWU Flag 1 register */
#define LLWU_F1_WUF0_MASK (0x1U)
#define LLWU_F1_WUF0_SHIFT (0U)
#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
#define LLWU_F1_WUF1_MASK (0x2U)
#define LLWU_F1_WUF1_SHIFT (1U)
#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
#define LLWU_F1_WUF2_MASK (0x4U)
#define LLWU_F1_WUF2_SHIFT (2U)
#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
#define LLWU_F1_WUF3_MASK (0x8U)
#define LLWU_F1_WUF3_SHIFT (3U)
#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
#define LLWU_F1_WUF4_MASK (0x10U)
#define LLWU_F1_WUF4_SHIFT (4U)
#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
#define LLWU_F1_WUF5_MASK (0x20U)
#define LLWU_F1_WUF5_SHIFT (5U)
#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
#define LLWU_F1_WUF6_MASK (0x40U)
#define LLWU_F1_WUF6_SHIFT (6U)
#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
#define LLWU_F1_WUF7_MASK (0x80U)
#define LLWU_F1_WUF7_SHIFT (7U)
#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
/*! @name F3 - LLWU Flag 3 register */
#define LLWU_F3_MWUF0_MASK (0x1U)
#define LLWU_F3_MWUF0_SHIFT (0U)
#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
#define LLWU_F3_MWUF1_MASK (0x2U)
#define LLWU_F3_MWUF1_SHIFT (1U)
#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
#define LLWU_F3_MWUF2_MASK (0x4U)
#define LLWU_F3_MWUF2_SHIFT (2U)
#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
#define LLWU_F3_MWUF3_MASK (0x8U)
#define LLWU_F3_MWUF3_SHIFT (3U)
#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
#define LLWU_F3_MWUF4_MASK (0x10U)
#define LLWU_F3_MWUF4_SHIFT (4U)
#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
#define LLWU_F3_MWUF5_MASK (0x20U)
#define LLWU_F3_MWUF5_SHIFT (5U)
#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
#define LLWU_F3_MWUF6_MASK (0x40U)
#define LLWU_F3_MWUF6_SHIFT (6U)
#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
#define LLWU_F3_MWUF7_MASK (0x80U)
#define LLWU_F3_MWUF7_SHIFT (7U)
#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
/*! @name FILT1 - LLWU Pin Filter 1 register */
#define LLWU_FILT1_FILTSEL_MASK (0xFU)
#define LLWU_FILT1_FILTSEL_SHIFT (0U)
#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
#define LLWU_FILT1_FILTE_MASK (0x60U)
#define LLWU_FILT1_FILTE_SHIFT (5U)
#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
#define LLWU_FILT1_FILTF_MASK (0x80U)
#define LLWU_FILT1_FILTF_SHIFT (7U)
#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
/*!
* @}
*/ /* end of group LLWU_Register_Masks */
/* LLWU - Peripheral instance base addresses */
/** Peripheral LLWU base address */
#define LLWU_BASE (0x4007C000u)
/** Peripheral LLWU base pointer */
#define LLWU ((LLWU_Type *)LLWU_BASE)
/** Array initializer of LLWU peripheral base addresses */
#define LLWU_BASE_ADDRS { LLWU_BASE }
/** Array initializer of LLWU peripheral base pointers */
#define LLWU_BASE_PTRS { LLWU }
/** Interrupt vectors for the LLWU peripheral type */
#define LLWU_IRQS { LLWU_IRQn }
/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPTMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
* @{
*/
/** LPTMR - Register Layout Typedef */
typedef struct {
__IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
__IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
} LPTMR_Type;
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
* @{
*/
/*! @name CSR - Low Power Timer Control Status Register */
#define LPTMR_CSR_TEN_MASK (0x1U)
#define LPTMR_CSR_TEN_SHIFT (0U)
#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
#define LPTMR_CSR_TMS_MASK (0x2U)
#define LPTMR_CSR_TMS_SHIFT (1U)
#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
#define LPTMR_CSR_TFC_MASK (0x4U)
#define LPTMR_CSR_TFC_SHIFT (2U)
#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
#define LPTMR_CSR_TPP_MASK (0x8U)
#define LPTMR_CSR_TPP_SHIFT (3U)
#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
#define LPTMR_CSR_TPS_MASK (0x30U)
#define LPTMR_CSR_TPS_SHIFT (4U)
#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
#define LPTMR_CSR_TIE_MASK (0x40U)
#define LPTMR_CSR_TIE_SHIFT (6U)
#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
#define LPTMR_CSR_TCF_MASK (0x80U)
#define LPTMR_CSR_TCF_SHIFT (7U)
#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
/*! @name PSR - Low Power Timer Prescale Register */
#define LPTMR_PSR_PCS_MASK (0x3U)
#define LPTMR_PSR_PCS_SHIFT (0U)
#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
#define LPTMR_PSR_PBYP_MASK (0x4U)
#define LPTMR_PSR_PBYP_SHIFT (2U)
#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
#define LPTMR_PSR_PRESCALE_MASK (0x78U)
#define LPTMR_PSR_PRESCALE_SHIFT (3U)
#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
/*! @name CMR - Low Power Timer Compare Register */
#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
#define LPTMR_CMR_COMPARE_SHIFT (0U)
#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
/*! @name CNR - Low Power Timer Counter Register */
#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
#define LPTMR_CNR_COUNTER_SHIFT (0U)
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
/*!
* @}
*/ /* end of group LPTMR_Register_Masks */
/* LPTMR - Peripheral instance base addresses */
/** Peripheral LPTMR0 base address */
#define LPTMR0_BASE (0x40040000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
/** Array initializer of LPTMR peripheral base addresses */
#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
/** Array initializer of LPTMR peripheral base pointers */
#define LPTMR_BASE_PTRS { LPTMR0 }
/** Interrupt vectors for the LPTMR peripheral type */
#define LPTMR_IRQS { LPTMR0_IRQn }
/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPUART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
* @{
*/
/** LPUART - Register Layout Typedef */
typedef struct {
__IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
__IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
__IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
} LPUART_Type;
/* ----------------------------------------------------------------------------
-- LPUART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Masks LPUART Register Masks
* @{
*/
/*! @name BAUD - LPUART Baud Rate Register */
#define LPUART_BAUD_SBR_MASK (0x1FFFU)
#define LPUART_BAUD_SBR_SHIFT (0U)
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
#define LPUART_BAUD_SBNS_MASK (0x2000U)
#define LPUART_BAUD_SBNS_SHIFT (13U)
#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
#define LPUART_BAUD_LBKDIE_SHIFT (15U)
#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
#define LPUART_BAUD_MATCFG_SHIFT (18U)
#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
#define LPUART_BAUD_OSR_MASK (0x1F000000U)
#define LPUART_BAUD_OSR_SHIFT (24U)
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
#define LPUART_BAUD_M10_MASK (0x20000000U)
#define LPUART_BAUD_M10_SHIFT (29U)
#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
#define LPUART_BAUD_MAEN2_SHIFT (30U)
#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
#define LPUART_BAUD_MAEN1_SHIFT (31U)
#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
/*! @name STAT - LPUART Status Register */
#define LPUART_STAT_MA2F_MASK (0x4000U)
#define LPUART_STAT_MA2F_SHIFT (14U)
#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
#define LPUART_STAT_MA1F_MASK (0x8000U)
#define LPUART_STAT_MA1F_SHIFT (15U)
#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
#define LPUART_STAT_PF_MASK (0x10000U)
#define LPUART_STAT_PF_SHIFT (16U)
#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
#define LPUART_STAT_FE_MASK (0x20000U)
#define LPUART_STAT_FE_SHIFT (17U)
#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
#define LPUART_STAT_NF_MASK (0x40000U)
#define LPUART_STAT_NF_SHIFT (18U)
#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
#define LPUART_STAT_OR_MASK (0x80000U)
#define LPUART_STAT_OR_SHIFT (19U)
#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
#define LPUART_STAT_IDLE_MASK (0x100000U)
#define LPUART_STAT_IDLE_SHIFT (20U)
#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
#define LPUART_STAT_RDRF_MASK (0x200000U)
#define LPUART_STAT_RDRF_SHIFT (21U)
#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
#define LPUART_STAT_TC_MASK (0x400000U)
#define LPUART_STAT_TC_SHIFT (22U)
#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
#define LPUART_STAT_TDRE_MASK (0x800000U)
#define LPUART_STAT_TDRE_SHIFT (23U)
#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
#define LPUART_STAT_RAF_MASK (0x1000000U)
#define LPUART_STAT_RAF_SHIFT (24U)
#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
#define LPUART_STAT_LBKDE_MASK (0x2000000U)
#define LPUART_STAT_LBKDE_SHIFT (25U)
#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
#define LPUART_STAT_BRK13_MASK (0x4000000U)
#define LPUART_STAT_BRK13_SHIFT (26U)
#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
#define LPUART_STAT_RWUID_MASK (0x8000000U)
#define LPUART_STAT_RWUID_SHIFT (27U)
#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
#define LPUART_STAT_RXINV_MASK (0x10000000U)
#define LPUART_STAT_RXINV_SHIFT (28U)
#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
#define LPUART_STAT_MSBF_MASK (0x20000000U)
#define LPUART_STAT_MSBF_SHIFT (29U)
#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
#define LPUART_STAT_RXEDGIF_SHIFT (30U)
#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
#define LPUART_STAT_LBKDIF_SHIFT (31U)
#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
/*! @name CTRL - LPUART Control Register */
#define LPUART_CTRL_PT_MASK (0x1U)
#define LPUART_CTRL_PT_SHIFT (0U)
#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
#define LPUART_CTRL_PE_MASK (0x2U)
#define LPUART_CTRL_PE_SHIFT (1U)
#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
#define LPUART_CTRL_ILT_MASK (0x4U)
#define LPUART_CTRL_ILT_SHIFT (2U)
#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
#define LPUART_CTRL_WAKE_MASK (0x8U)
#define LPUART_CTRL_WAKE_SHIFT (3U)
#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
#define LPUART_CTRL_M_MASK (0x10U)
#define LPUART_CTRL_M_SHIFT (4U)
#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
#define LPUART_CTRL_RSRC_MASK (0x20U)
#define LPUART_CTRL_RSRC_SHIFT (5U)
#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
#define LPUART_CTRL_DOZEEN_MASK (0x40U)
#define LPUART_CTRL_DOZEEN_SHIFT (6U)
#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
#define LPUART_CTRL_LOOPS_MASK (0x80U)
#define LPUART_CTRL_LOOPS_SHIFT (7U)
#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
#define LPUART_CTRL_IDLECFG_MASK (0x700U)
#define LPUART_CTRL_IDLECFG_SHIFT (8U)
#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
#define LPUART_CTRL_MA2IE_MASK (0x4000U)
#define LPUART_CTRL_MA2IE_SHIFT (14U)
#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
#define LPUART_CTRL_MA1IE_MASK (0x8000U)
#define LPUART_CTRL_MA1IE_SHIFT (15U)
#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
#define LPUART_CTRL_SBK_MASK (0x10000U)
#define LPUART_CTRL_SBK_SHIFT (16U)
#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
#define LPUART_CTRL_RWU_MASK (0x20000U)
#define LPUART_CTRL_RWU_SHIFT (17U)
#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
#define LPUART_CTRL_RE_MASK (0x40000U)
#define LPUART_CTRL_RE_SHIFT (18U)
#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
#define LPUART_CTRL_TE_MASK (0x80000U)
#define LPUART_CTRL_TE_SHIFT (19U)
#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
#define LPUART_CTRL_ILIE_MASK (0x100000U)
#define LPUART_CTRL_ILIE_SHIFT (20U)
#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
#define LPUART_CTRL_RIE_MASK (0x200000U)
#define LPUART_CTRL_RIE_SHIFT (21U)
#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
#define LPUART_CTRL_TCIE_MASK (0x400000U)
#define LPUART_CTRL_TCIE_SHIFT (22U)
#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
#define LPUART_CTRL_TIE_MASK (0x800000U)
#define LPUART_CTRL_TIE_SHIFT (23U)
#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
#define LPUART_CTRL_PEIE_MASK (0x1000000U)
#define LPUART_CTRL_PEIE_SHIFT (24U)
#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
#define LPUART_CTRL_FEIE_MASK (0x2000000U)
#define LPUART_CTRL_FEIE_SHIFT (25U)
#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
#define LPUART_CTRL_NEIE_MASK (0x4000000U)
#define LPUART_CTRL_NEIE_SHIFT (26U)
#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
#define LPUART_CTRL_ORIE_MASK (0x8000000U)
#define LPUART_CTRL_ORIE_SHIFT (27U)
#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
#define LPUART_CTRL_TXINV_MASK (0x10000000U)
#define LPUART_CTRL_TXINV_SHIFT (28U)
#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
#define LPUART_CTRL_TXDIR_SHIFT (29U)
#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
#define LPUART_CTRL_R9T8_MASK (0x40000000U)
#define LPUART_CTRL_R9T8_SHIFT (30U)
#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
#define LPUART_CTRL_R8T9_MASK (0x80000000U)
#define LPUART_CTRL_R8T9_SHIFT (31U)
#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
/*! @name DATA - LPUART Data Register */
#define LPUART_DATA_R0T0_MASK (0x1U)
#define LPUART_DATA_R0T0_SHIFT (0U)
#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
#define LPUART_DATA_R1T1_MASK (0x2U)
#define LPUART_DATA_R1T1_SHIFT (1U)
#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
#define LPUART_DATA_R2T2_MASK (0x4U)
#define LPUART_DATA_R2T2_SHIFT (2U)
#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
#define LPUART_DATA_R3T3_MASK (0x8U)
#define LPUART_DATA_R3T3_SHIFT (3U)
#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
#define LPUART_DATA_R4T4_MASK (0x10U)
#define LPUART_DATA_R4T4_SHIFT (4U)
#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
#define LPUART_DATA_R5T5_MASK (0x20U)
#define LPUART_DATA_R5T5_SHIFT (5U)
#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
#define LPUART_DATA_R6T6_MASK (0x40U)
#define LPUART_DATA_R6T6_SHIFT (6U)
#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
#define LPUART_DATA_R7T7_MASK (0x80U)
#define LPUART_DATA_R7T7_SHIFT (7U)
#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
#define LPUART_DATA_R8T8_MASK (0x100U)
#define LPUART_DATA_R8T8_SHIFT (8U)
#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
#define LPUART_DATA_R9T9_MASK (0x200U)
#define LPUART_DATA_R9T9_SHIFT (9U)
#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
#define LPUART_DATA_IDLINE_MASK (0x800U)
#define LPUART_DATA_IDLINE_SHIFT (11U)
#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
#define LPUART_DATA_RXEMPT_MASK (0x1000U)
#define LPUART_DATA_RXEMPT_SHIFT (12U)
#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
#define LPUART_DATA_FRETSC_MASK (0x2000U)
#define LPUART_DATA_FRETSC_SHIFT (13U)
#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
#define LPUART_DATA_PARITYE_MASK (0x4000U)
#define LPUART_DATA_PARITYE_SHIFT (14U)
#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
#define LPUART_DATA_NOISY_MASK (0x8000U)
#define LPUART_DATA_NOISY_SHIFT (15U)
#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
/*! @name MATCH - LPUART Match Address Register */
#define LPUART_MATCH_MA1_MASK (0x3FFU)
#define LPUART_MATCH_MA1_SHIFT (0U)
#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
#define LPUART_MATCH_MA2_SHIFT (16U)
#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
/*!
* @}
*/ /* end of group LPUART_Register_Masks */
/* LPUART - Peripheral instance base addresses */
/** Peripheral LPUART0 base address */
#define LPUART0_BASE (0x40054000u)
/** Peripheral LPUART0 base pointer */
#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { LPUART0_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS { LPUART0 }
/** Interrupt vectors for the LPUART peripheral type */
#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
#define LPUART_ERR_IRQS { LPUART0_IRQn }
/*!
* @}
*/ /* end of group LPUART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
* @{
*/
/** MCG - Register Layout Typedef */
typedef struct {
__IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
__IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
uint8_t RESERVED_0[4];
__I uint8_t S; /**< MCG Status Register, offset: 0x6 */
uint8_t RESERVED_1[1];
__IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
uint8_t RESERVED_2[15];
__IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
} MCG_Type;
/* ----------------------------------------------------------------------------
-- MCG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCG_Register_Masks MCG Register Masks
* @{
*/
/*! @name C1 - MCG Control Register 1 */
#define MCG_C1_IREFSTEN_MASK (0x1U)
#define MCG_C1_IREFSTEN_SHIFT (0U)
#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
#define MCG_C1_IRCLKEN_MASK (0x2U)
#define MCG_C1_IRCLKEN_SHIFT (1U)
#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
#define MCG_C1_CLKS_MASK (0xC0U)
#define MCG_C1_CLKS_SHIFT (6U)
#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
/*! @name C2 - MCG Control Register 2 */
#define MCG_C2_IRCS_MASK (0x1U)
#define MCG_C2_IRCS_SHIFT (0U)
#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
#define MCG_C2_EREFS0_MASK (0x4U)
#define MCG_C2_EREFS0_SHIFT (2U)
#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
/*! @name S - MCG Status Register */
#define MCG_S_OSCINIT0_MASK (0x2U)
#define MCG_S_OSCINIT0_SHIFT (1U)
#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
#define MCG_S_CLKST_MASK (0xCU)
#define MCG_S_CLKST_SHIFT (2U)
#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
/*! @name SC - MCG Status and Control Register */
#define MCG_SC_FCRDIV_MASK (0xEU)
#define MCG_SC_FCRDIV_SHIFT (1U)
#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
/*! @name MC - MCG Miscellaneous Control Register */
#define MCG_MC_LIRC_DIV2_MASK (0x7U)
#define MCG_MC_LIRC_DIV2_SHIFT (0U)
#define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_LIRC_DIV2_SHIFT)) & MCG_MC_LIRC_DIV2_MASK)
#define MCG_MC_HIRCEN_MASK (0x80U)
#define MCG_MC_HIRCEN_SHIFT (7U)
#define MCG_MC_HIRCEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCEN_SHIFT)) & MCG_MC_HIRCEN_MASK)
/*!
* @}
*/ /* end of group MCG_Register_Masks */
/* MCG - Peripheral instance base addresses */
/** Peripheral MCG base address */
#define MCG_BASE (0x40064000u)
/** Peripheral MCG base pointer */
#define MCG ((MCG_Type *)MCG_BASE)
/** Array initializer of MCG peripheral base addresses */
#define MCG_BASE_ADDRS { MCG_BASE }
/** Array initializer of MCG peripheral base pointers */
#define MCG_BASE_PTRS { MCG }
/*!
* @}
*/ /* end of group MCG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
* @{
*/
/** MCM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
__I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
__IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
uint8_t RESERVED_1[48];
__IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
} MCM_Type;
/* ----------------------------------------------------------------------------
-- MCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Masks MCM Register Masks
* @{
*/
/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
#define MCM_PLASC_ASC_MASK (0xFFU)
#define MCM_PLASC_ASC_SHIFT (0U)
#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
#define MCM_PLAMC_AMC_MASK (0xFFU)
#define MCM_PLAMC_AMC_SHIFT (0U)
#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
/*! @name PLACR - Platform Control Register */
#define MCM_PLACR_EFDS_MASK (0x4000U)
#define MCM_PLACR_EFDS_SHIFT (14U)
#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
#define MCM_PLACR_DFCS_MASK (0x8000U)
#define MCM_PLACR_DFCS_SHIFT (15U)
#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
#define MCM_PLACR_ESFC_MASK (0x10000U)
#define MCM_PLACR_ESFC_SHIFT (16U)
#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
/*! @name CPO - Compute Operation Control Register */
#define MCM_CPO_CPOREQ_MASK (0x1U)
#define MCM_CPO_CPOREQ_SHIFT (0U)
#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
#define MCM_CPO_CPOACK_MASK (0x2U)
#define MCM_CPO_CPOACK_SHIFT (1U)
#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
#define MCM_CPO_CPOWOI_MASK (0x4U)
#define MCM_CPO_CPOWOI_SHIFT (2U)
#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
/*!
* @}
*/ /* end of group MCM_Register_Masks */
/* MCM - Peripheral instance base addresses */
/** Peripheral MCM base address */
#define MCM_BASE (0xF0003000u)
/** Peripheral MCM base pointer */
#define MCM ((MCM_Type *)MCM_BASE)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS { MCM_BASE }
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASE_PTRS { MCM }
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MTB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
* @{
*/
/** MTB - Register Layout Typedef */
typedef struct {
__IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
__IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
__IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
__I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
uint8_t RESERVED_0[3824];
__I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
uint8_t RESERVED_1[156];
__I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
__I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
uint8_t RESERVED_2[8];
__I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
__I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
__I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
__I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
uint8_t RESERVED_3[8];
__I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
__I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
__I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
__I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
__I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
__I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
__I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
__I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
__I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
__I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
} MTB_Type;
/* ----------------------------------------------------------------------------
-- MTB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Register_Masks MTB Register Masks
* @{
*/
/*! @name POSITION - MTB Position Register */
#define MTB_POSITION_WRAP_MASK (0x4U)
#define MTB_POSITION_WRAP_SHIFT (2U)
#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
#define MTB_POSITION_POINTER_SHIFT (3U)
#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
/*! @name MASTER - MTB Master Register */
#define MTB_MASTER_MASK_MASK (0x1FU)
#define MTB_MASTER_MASK_SHIFT (0U)
#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
#define MTB_MASTER_TSTARTEN_MASK (0x20U)
#define MTB_MASTER_TSTARTEN_SHIFT (5U)
#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
#define MTB_MASTER_TSTOPEN_MASK (0x40U)
#define MTB_MASTER_TSTOPEN_SHIFT (6U)
#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
#define MTB_MASTER_RAMPRIV_MASK (0x100U)
#define MTB_MASTER_RAMPRIV_SHIFT (8U)
#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
#define MTB_MASTER_HALTREQ_MASK (0x200U)
#define MTB_MASTER_HALTREQ_SHIFT (9U)
#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
#define MTB_MASTER_EN_MASK (0x80000000U)
#define MTB_MASTER_EN_SHIFT (31U)
#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
/*! @name FLOW - MTB Flow Register */
#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
#define MTB_FLOW_AUTOHALT_MASK (0x2U)
#define MTB_FLOW_AUTOHALT_SHIFT (1U)
#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
#define MTB_FLOW_WATERMARK_SHIFT (3U)
#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
/*! @name BASE - MTB Base Register */
#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
#define MTB_BASE_BASEADDR_SHIFT (0U)
#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
/*! @name MODECTRL - Integration Mode Control Register */
#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
#define MTB_MODECTRL_MODECTRL_SHIFT (0U)
#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
/*! @name TAGSET - Claim TAG Set Register */
#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
#define MTB_TAGSET_TAGSET_SHIFT (0U)
#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
/*! @name TAGCLEAR - Claim TAG Clear Register */
#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
/*! @name LOCKACCESS - Lock Access Register */
#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
/*! @name LOCKSTAT - Lock Status Register */
#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
/*! @name AUTHSTAT - Authentication Status Register */
#define MTB_AUTHSTAT_BIT0_MASK (0x1U)
#define MTB_AUTHSTAT_BIT0_SHIFT (0U)
#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
#define MTB_AUTHSTAT_BIT1_MASK (0x2U)
#define MTB_AUTHSTAT_BIT1_SHIFT (1U)
#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
#define MTB_AUTHSTAT_BIT2_MASK (0x4U)
#define MTB_AUTHSTAT_BIT2_SHIFT (2U)
#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
#define MTB_AUTHSTAT_BIT3_MASK (0x8U)
#define MTB_AUTHSTAT_BIT3_SHIFT (3U)
#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
/*! @name DEVICEARCH - Device Architecture Register */
#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
/*! @name DEVICECFG - Device Configuration Register */
#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
/*! @name DEVICETYPID - Device Type Identifier Register */
#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
/*! @name PERIPHID4 - Peripheral ID Register */
#define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID4_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
/*! @name PERIPHID5 - Peripheral ID Register */
#define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID5_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
/*! @name PERIPHID6 - Peripheral ID Register */
#define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID6_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
/*! @name PERIPHID7 - Peripheral ID Register */
#define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID7_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
/*! @name PERIPHID0 - Peripheral ID Register */
#define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID0_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
/*! @name PERIPHID1 - Peripheral ID Register */
#define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID1_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
/*! @name PERIPHID2 - Peripheral ID Register */
#define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID2_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
/*! @name PERIPHID3 - Peripheral ID Register */
#define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID3_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
/*! @name COMPID - Component ID Register */
#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
#define MTB_COMPID_COMPID_SHIFT (0U)
#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
/* The count of MTB_COMPID */
#define MTB_COMPID_COUNT (4U)
/*!
* @}
*/ /* end of group MTB_Register_Masks */
/* MTB - Peripheral instance base addresses */
/** Peripheral MTB base address */
#define MTB_BASE (0xF0000000u)
/** Peripheral MTB base pointer */
#define MTB ((MTB_Type *)MTB_BASE)
/** Array initializer of MTB peripheral base addresses */
#define MTB_BASE_ADDRS { MTB_BASE }
/** Array initializer of MTB peripheral base pointers */
#define MTB_BASE_PTRS { MTB }
/*!
* @}
*/ /* end of group MTB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MTBDWT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
* @{
*/
/** MTBDWT - Register Layout Typedef */
typedef struct {
__I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
uint8_t RESERVED_0[28];
struct { /* offset: 0x20, array step: 0x10 */
__IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
__IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
__IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
uint8_t RESERVED_0[4];
} COMPARATOR[2];
uint8_t RESERVED_1[448];
__IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
uint8_t RESERVED_2[3524];
__I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
__I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
__I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
__I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
__I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
__I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
__I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
__I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
__I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
__I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
} MTBDWT_Type;
/* ----------------------------------------------------------------------------
-- MTBDWT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
* @{
*/
/*! @name CTRL - MTB DWT Control Register */
#define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
#define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
#define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
/*! @name COMP - MTB_DWT Comparator Register */
#define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
#define MTBDWT_COMP_COMP_SHIFT (0U)
#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
/* The count of MTBDWT_COMP */
#define MTBDWT_COMP_COUNT (2U)
/*! @name MASK - MTB_DWT Comparator Mask Register */
#define MTBDWT_MASK_MASK_MASK (0x1FU)
#define MTBDWT_MASK_MASK_SHIFT (0U)
#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
/* The count of MTBDWT_MASK */
#define MTBDWT_MASK_COUNT (2U)
/*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
#define MTBDWT_FCT_FUNCTION_MASK (0xFU)
#define MTBDWT_FCT_FUNCTION_SHIFT (0U)
#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
#define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
#define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
#define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
#define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
#define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
#define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
#define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
#define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
#define MTBDWT_FCT_MATCHED_SHIFT (24U)
#define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
/* The count of MTBDWT_FCT */
#define MTBDWT_FCT_COUNT (2U)
/*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
#define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
#define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
#define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
#define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
#define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
#define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
#define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
#define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
/*! @name DEVICECFG - Device Configuration Register */
#define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
/*! @name DEVICETYPID - Device Type Identifier Register */
#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
/*! @name PERIPHID4 - Peripheral ID Register */
#define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
#define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U)
#define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
/*! @name PERIPHID5 - Peripheral ID Register */
#define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
#define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U)
#define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
/*! @name PERIPHID6 - Peripheral ID Register */
#define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
#define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U)
#define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
/*! @name PERIPHID7 - Peripheral ID Register */
#define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
#define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U)
#define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
/*! @name PERIPHID0 - Peripheral ID Register */
#define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
#define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U)
#define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
/*! @name PERIPHID1 - Peripheral ID Register */
#define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
#define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U)
#define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
/*! @name PERIPHID2 - Peripheral ID Register */
#define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
#define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U)
#define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
/*! @name PERIPHID3 - Peripheral ID Register */
#define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
#define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U)
#define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
/*! @name COMPID - Component ID Register */
#define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
#define MTBDWT_COMPID_COMPID_SHIFT (0U)
#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
/* The count of MTBDWT_COMPID */
#define MTBDWT_COMPID_COUNT (4U)
/*!
* @}
*/ /* end of group MTBDWT_Register_Masks */
/* MTBDWT - Peripheral instance base addresses */
/** Peripheral MTBDWT base address */
#define MTBDWT_BASE (0xF0001000u)
/** Peripheral MTBDWT base pointer */
#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
/** Array initializer of MTBDWT peripheral base addresses */
#define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
/** Array initializer of MTBDWT peripheral base pointers */
#define MTBDWT_BASE_PTRS { MTBDWT }
/*!
* @}
*/ /* end of group MTBDWT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- NV Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
* @{
*/
/** NV - Register Layout Typedef */
typedef struct {
__I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
__I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
__I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
__I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
__I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
__I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
__I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
__I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
__I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
__I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
__I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
__I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
__I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
} NV_Type;
/* ----------------------------------------------------------------------------
-- NV Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Masks NV Register Masks
* @{
*/
/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
#define NV_BACKKEY3_KEY_MASK (0xFFU)
#define NV_BACKKEY3_KEY_SHIFT (0U)
#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
#define NV_BACKKEY2_KEY_MASK (0xFFU)
#define NV_BACKKEY2_KEY_SHIFT (0U)
#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
#define NV_BACKKEY1_KEY_MASK (0xFFU)
#define NV_BACKKEY1_KEY_SHIFT (0U)
#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
#define NV_BACKKEY0_KEY_MASK (0xFFU)
#define NV_BACKKEY0_KEY_SHIFT (0U)
#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
#define NV_BACKKEY7_KEY_MASK (0xFFU)
#define NV_BACKKEY7_KEY_SHIFT (0U)
#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
#define NV_BACKKEY6_KEY_MASK (0xFFU)
#define NV_BACKKEY6_KEY_SHIFT (0U)
#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
#define NV_BACKKEY5_KEY_MASK (0xFFU)
#define NV_BACKKEY5_KEY_SHIFT (0U)
#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
#define NV_BACKKEY4_KEY_MASK (0xFFU)
#define NV_BACKKEY4_KEY_SHIFT (0U)
#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
#define NV_FPROT3_PROT_MASK (0xFFU)
#define NV_FPROT3_PROT_SHIFT (0U)
#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
#define NV_FPROT2_PROT_MASK (0xFFU)
#define NV_FPROT2_PROT_SHIFT (0U)
#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
#define NV_FPROT1_PROT_MASK (0xFFU)
#define NV_FPROT1_PROT_SHIFT (0U)
#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
#define NV_FPROT0_PROT_MASK (0xFFU)
#define NV_FPROT0_PROT_SHIFT (0U)
#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
/*! @name FSEC - Non-volatile Flash Security Register */
#define NV_FSEC_SEC_MASK (0x3U)
#define NV_FSEC_SEC_SHIFT (0U)
#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
#define NV_FSEC_FSLACC_MASK (0xCU)
#define NV_FSEC_FSLACC_SHIFT (2U)
#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
#define NV_FSEC_MEEN_MASK (0x30U)
#define NV_FSEC_MEEN_SHIFT (4U)
#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
#define NV_FSEC_KEYEN_MASK (0xC0U)
#define NV_FSEC_KEYEN_SHIFT (6U)
#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
/*! @name FOPT - Non-volatile Flash Option Register */
#define NV_FOPT_LPBOOT0_MASK (0x1U)
#define NV_FOPT_LPBOOT0_SHIFT (0U)
#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
#define NV_FOPT_BOOTPIN_OPT_MASK (0x2U)
#define NV_FOPT_BOOTPIN_OPT_SHIFT (1U)
#define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
#define NV_FOPT_NMI_DIS_MASK (0x4U)
#define NV_FOPT_NMI_DIS_SHIFT (2U)
#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
#define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
#define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
#define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
#define NV_FOPT_LPBOOT1_MASK (0x10U)
#define NV_FOPT_LPBOOT1_SHIFT (4U)
#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
#define NV_FOPT_FAST_INIT_MASK (0x20U)
#define NV_FOPT_FAST_INIT_SHIFT (5U)
#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
#define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U)
#define NV_FOPT_BOOTSRC_SEL_SHIFT (6U)
#define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
/*!
* @}
*/ /* end of group NV_Register_Masks */
/* NV - Peripheral instance base addresses */
/** Peripheral FTFA_FlashConfig base address */
#define FTFA_FlashConfig_BASE (0x400u)
/** Peripheral FTFA_FlashConfig base pointer */
#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
/** Array initializer of NV peripheral base addresses */
#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
/** Array initializer of NV peripheral base pointers */
#define NV_BASE_PTRS { FTFA_FlashConfig }
/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- OSC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
* @{
*/
/** OSC - Register Layout Typedef */
typedef struct {
__IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
} OSC_Type;
/* ----------------------------------------------------------------------------
-- OSC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_Register_Masks OSC Register Masks
* @{
*/
/*! @name CR - OSC Control Register */
#define OSC_CR_SC16P_MASK (0x1U)
#define OSC_CR_SC16P_SHIFT (0U)
#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
#define OSC_CR_SC8P_MASK (0x2U)
#define OSC_CR_SC8P_SHIFT (1U)
#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
#define OSC_CR_SC4P_MASK (0x4U)
#define OSC_CR_SC4P_SHIFT (2U)
#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
#define OSC_CR_SC2P_MASK (0x8U)
#define OSC_CR_SC2P_SHIFT (3U)
#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
#define OSC_CR_EREFSTEN_MASK (0x20U)
#define OSC_CR_EREFSTEN_SHIFT (5U)
#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
#define OSC_CR_ERCLKEN_MASK (0x80U)
#define OSC_CR_ERCLKEN_SHIFT (7U)
#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
/*!
* @}
*/ /* end of group OSC_Register_Masks */
/* OSC - Peripheral instance base addresses */
/** Peripheral OSC base address */
#define OSC_BASE (0x40065000u)
/** Peripheral OSC base pointer */
#define OSC ((OSC_Type *)OSC_BASE)
/** Array initializer of OSC peripheral base addresses */
#define OSC_BASE_ADDRS { OSC_BASE }
/** Array initializer of OSC peripheral base pointers */
#define OSC_BASE_PTRS { OSC }
/*!
* @}
*/ /* end of group OSC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
* @{
*/
/** PMC - Register Layout Typedef */
typedef struct {
__IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
__IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
__IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
} PMC_Type;
/* ----------------------------------------------------------------------------
-- PMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Masks PMC Register Masks
* @{
*/
/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
#define PMC_LVDSC1_LVDV_MASK (0x3U)
#define PMC_LVDSC1_LVDV_SHIFT (0U)
#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
#define PMC_LVDSC1_LVDRE_MASK (0x10U)
#define PMC_LVDSC1_LVDRE_SHIFT (4U)
#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
#define PMC_LVDSC1_LVDIE_MASK (0x20U)
#define PMC_LVDSC1_LVDIE_SHIFT (5U)
#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
#define PMC_LVDSC1_LVDACK_MASK (0x40U)
#define PMC_LVDSC1_LVDACK_SHIFT (6U)
#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
#define PMC_LVDSC1_LVDF_MASK (0x80U)
#define PMC_LVDSC1_LVDF_SHIFT (7U)
#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
#define PMC_LVDSC2_LVWV_MASK (0x3U)
#define PMC_LVDSC2_LVWV_SHIFT (0U)
#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
#define PMC_LVDSC2_LVWIE_MASK (0x20U)
#define PMC_LVDSC2_LVWIE_SHIFT (5U)
#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
#define PMC_LVDSC2_LVWACK_MASK (0x40U)
#define PMC_LVDSC2_LVWACK_SHIFT (6U)
#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
#define PMC_LVDSC2_LVWF_MASK (0x80U)
#define PMC_LVDSC2_LVWF_SHIFT (7U)
#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
/*! @name REGSC - Regulator Status And Control register */
#define PMC_REGSC_BGBE_MASK (0x1U)
#define PMC_REGSC_BGBE_SHIFT (0U)
#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
#define PMC_REGSC_REGONS_MASK (0x4U)
#define PMC_REGSC_REGONS_SHIFT (2U)
#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
#define PMC_REGSC_ACKISO_MASK (0x8U)
#define PMC_REGSC_ACKISO_SHIFT (3U)
#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
#define PMC_REGSC_BGEN_MASK (0x10U)
#define PMC_REGSC_BGEN_SHIFT (4U)
#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
/*!
* @}
*/ /* end of group PMC_Register_Masks */
/* PMC - Peripheral instance base addresses */
/** Peripheral PMC base address */
#define PMC_BASE (0x4007D000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
/** Array initializer of PMC peripheral base addresses */
#define PMC_BASE_ADDRS { PMC_BASE }
/** Array initializer of PMC peripheral base pointers */
#define PMC_BASE_PTRS { PMC }
/** Interrupt vectors for the PMC peripheral type */
#define PMC_IRQS { PMC_IRQn }
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PORT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
* @{
*/
/** PORT - Register Layout Typedef */
typedef struct {
__IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
__IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
} PORT_Type;
/* ----------------------------------------------------------------------------
-- PORT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Masks PORT Register Masks
* @{
*/
/*! @name PCR - Pin Control Register n */
#define PORT_PCR_PS_MASK (0x1U)
#define PORT_PCR_PS_SHIFT (0U)
#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
#define PORT_PCR_PE_MASK (0x2U)
#define PORT_PCR_PE_SHIFT (1U)
#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
#define PORT_PCR_SRE_MASK (0x4U)
#define PORT_PCR_SRE_SHIFT (2U)
#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
#define PORT_PCR_PFE_MASK (0x10U)
#define PORT_PCR_PFE_SHIFT (4U)
#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
#define PORT_PCR_DSE_MASK (0x40U)
#define PORT_PCR_DSE_SHIFT (6U)
#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
#define PORT_PCR_MUX_MASK (0x700U)
#define PORT_PCR_MUX_SHIFT (8U)
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
#define PORT_PCR_IRQC_MASK (0xF0000U)
#define PORT_PCR_IRQC_SHIFT (16U)
#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
#define PORT_PCR_ISF_MASK (0x1000000U)
#define PORT_PCR_ISF_SHIFT (24U)
#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
/* The count of PORT_PCR */
#define PORT_PCR_COUNT (32U)
/*! @name GPCLR - Global Pin Control Low Register */
#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
#define PORT_GPCLR_GPWD_SHIFT (0U)
#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
#define PORT_GPCLR_GPWE_SHIFT (16U)
#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
/*! @name GPCHR - Global Pin Control High Register */
#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
#define PORT_GPCHR_GPWD_SHIFT (0U)
#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
#define PORT_GPCHR_GPWE_SHIFT (16U)
#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
/*! @name ISFR - Interrupt Status Flag Register */
#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
#define PORT_ISFR_ISF_SHIFT (0U)
#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
/*!
* @}
*/ /* end of group PORT_Register_Masks */
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base address */
#define PORTA_BASE (0x40049000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4004A000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
/** Array initializer of PORT peripheral base addresses */
#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE }
/** Array initializer of PORT peripheral base pointers */
#define PORT_BASE_PTRS { PORTA, PORTB }
/** Interrupt vectors for the PORT peripheral type */
#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn }
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
* @{
*/
/** RCM - Register Layout Typedef */
typedef struct {
__I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
__I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
uint8_t RESERVED_0[2];
__IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
__IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
__IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
__IO uint8_t MR; /**< Mode Register, offset: 0x7 */
__IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
__IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
} RCM_Type;
/* ----------------------------------------------------------------------------
-- RCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Masks RCM Register Masks
* @{
*/
/*! @name SRS0 - System Reset Status Register 0 */
#define RCM_SRS0_WAKEUP_MASK (0x1U)
#define RCM_SRS0_WAKEUP_SHIFT (0U)
#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
#define RCM_SRS0_LVD_MASK (0x2U)
#define RCM_SRS0_LVD_SHIFT (1U)
#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
#define RCM_SRS0_WDOG_MASK (0x20U)
#define RCM_SRS0_WDOG_SHIFT (5U)
#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
#define RCM_SRS0_PIN_MASK (0x40U)
#define RCM_SRS0_PIN_SHIFT (6U)
#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
#define RCM_SRS0_POR_MASK (0x80U)
#define RCM_SRS0_POR_SHIFT (7U)
#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
/*! @name SRS1 - System Reset Status Register 1 */
#define RCM_SRS1_LOCKUP_MASK (0x2U)
#define RCM_SRS1_LOCKUP_SHIFT (1U)
#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
#define RCM_SRS1_SW_MASK (0x4U)
#define RCM_SRS1_SW_SHIFT (2U)
#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
#define RCM_SRS1_MDM_AP_MASK (0x8U)
#define RCM_SRS1_MDM_AP_SHIFT (3U)
#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
#define RCM_SRS1_SACKERR_MASK (0x20U)
#define RCM_SRS1_SACKERR_SHIFT (5U)
#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
/*! @name RPFC - Reset Pin Filter Control register */
#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
/*! @name RPFW - Reset Pin Filter Width register */
#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
/*! @name FM - Force Mode Register */
#define RCM_FM_FORCEROM_MASK (0x6U)
#define RCM_FM_FORCEROM_SHIFT (1U)
#define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
/*! @name MR - Mode Register */
#define RCM_MR_BOOTROM_MASK (0x6U)
#define RCM_MR_BOOTROM_SHIFT (1U)
#define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
/*! @name SSRS0 - Sticky System Reset Status Register 0 */
#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
#define RCM_SSRS0_SLVD_MASK (0x2U)
#define RCM_SSRS0_SLVD_SHIFT (1U)
#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
#define RCM_SSRS0_SWDOG_MASK (0x20U)
#define RCM_SSRS0_SWDOG_SHIFT (5U)
#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
#define RCM_SSRS0_SPIN_MASK (0x40U)
#define RCM_SSRS0_SPIN_SHIFT (6U)
#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
#define RCM_SSRS0_SPOR_MASK (0x80U)
#define RCM_SSRS0_SPOR_SHIFT (7U)
#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
/*! @name SSRS1 - Sticky System Reset Status Register 1 */
#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
#define RCM_SSRS1_SSW_MASK (0x4U)
#define RCM_SSRS1_SSW_SHIFT (2U)
#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
#define RCM_SSRS1_SSACKERR_MASK (0x20U)
#define RCM_SSRS1_SSACKERR_SHIFT (5U)
#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
/*!
* @}
*/ /* end of group RCM_Register_Masks */
/* RCM - Peripheral instance base addresses */
/** Peripheral RCM base address */
#define RCM_BASE (0x4007F000u)
/** Peripheral RCM base pointer */
#define RCM ((RCM_Type *)RCM_BASE)
/** Array initializer of RCM peripheral base addresses */
#define RCM_BASE_ADDRS { RCM_BASE }
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASE_PTRS { RCM }
/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RFSYS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
* @{
*/
/** RFSYS - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[4]; /**< Register file register, array offset: 0x0, array step: 0x4 */
} RFSYS_Type;
/* ----------------------------------------------------------------------------
-- RFSYS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFSYS_Register_Masks RFSYS Register Masks
* @{
*/
/*! @name REG - Register file register */
#define RFSYS_REG_LL_MASK (0xFFU)
#define RFSYS_REG_LL_SHIFT (0U)
#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
#define RFSYS_REG_LH_MASK (0xFF00U)
#define RFSYS_REG_LH_SHIFT (8U)
#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
#define RFSYS_REG_HL_MASK (0xFF0000U)
#define RFSYS_REG_HL_SHIFT (16U)
#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
#define RFSYS_REG_HH_MASK (0xFF000000U)
#define RFSYS_REG_HH_SHIFT (24U)
#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
/* The count of RFSYS_REG */
#define RFSYS_REG_COUNT (4U)
/*!
* @}
*/ /* end of group RFSYS_Register_Masks */
/* RFSYS - Peripheral instance base addresses */
/** Peripheral RFSYS base address */
#define RFSYS_BASE (0x40041000u)
/** Peripheral RFSYS base pointer */
#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
/** Array initializer of RFSYS peripheral base addresses */
#define RFSYS_BASE_ADDRS { RFSYS_BASE }
/** Array initializer of RFSYS peripheral base pointers */
#define RFSYS_BASE_PTRS { RFSYS }
/*!
* @}
*/ /* end of group RFSYS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ROM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
* @{
*/
/** ROM - Register Layout Typedef */
typedef struct {
__I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
__I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
uint8_t RESERVED_0[4028];
__I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
__I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
__I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
__I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
__I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
__I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
__I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
__I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
__I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
} ROM_Type;
/* ----------------------------------------------------------------------------
-- ROM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ROM_Register_Masks ROM Register Masks
* @{
*/
/*! @name ENTRY - Entry */
#define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
#define ROM_ENTRY_ENTRY_SHIFT (0U)
#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
/* The count of ROM_ENTRY */
#define ROM_ENTRY_COUNT (3U)
/*! @name TABLEMARK - End of Table Marker Register */
#define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
#define ROM_TABLEMARK_MARK_SHIFT (0U)
#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
/*! @name SYSACCESS - System Access Register */
#define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
#define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
/*! @name PERIPHID4 - Peripheral ID Register */
#define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
#define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
/*! @name PERIPHID5 - Peripheral ID Register */
#define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
#define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
/*! @name PERIPHID6 - Peripheral ID Register */
#define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
#define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
/*! @name PERIPHID7 - Peripheral ID Register */
#define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
#define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
/*! @name PERIPHID0 - Peripheral ID Register */
#define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
#define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
/*! @name PERIPHID1 - Peripheral ID Register */
#define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
#define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
/*! @name PERIPHID2 - Peripheral ID Register */
#define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
#define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
/*! @name PERIPHID3 - Peripheral ID Register */
#define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
#define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
/*! @name COMPID - Component ID Register */
#define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
#define ROM_COMPID_COMPID_SHIFT (0U)
#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
/* The count of ROM_COMPID */
#define ROM_COMPID_COUNT (4U)
/*!
* @}
*/ /* end of group ROM_Register_Masks */
/* ROM - Peripheral instance base addresses */
/** Peripheral ROM base address */
#define ROM_BASE (0xF0002000u)
/** Peripheral ROM base pointer */
#define ROM ((ROM_Type *)ROM_BASE)
/** Array initializer of ROM peripheral base addresses */
#define ROM_BASE_ADDRS { ROM_BASE }
/** Array initializer of ROM peripheral base pointers */
#define ROM_BASE_PTRS { ROM }
/*!
* @}
*/ /* end of group ROM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RTC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
* @{
*/
/** RTC - Register Layout Typedef */
typedef struct {
__IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
__IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
__IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
__IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
__IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
__IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
__IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
} RTC_Type;
/* ----------------------------------------------------------------------------
-- RTC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Masks RTC Register Masks
* @{
*/
/*! @name TSR - RTC Time Seconds Register */
#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
#define RTC_TSR_TSR_SHIFT (0U)
#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
/*! @name TPR - RTC Time Prescaler Register */
#define RTC_TPR_TPR_MASK (0xFFFFU)
#define RTC_TPR_TPR_SHIFT (0U)
#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
/*! @name TAR - RTC Time Alarm Register */
#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
#define RTC_TAR_TAR_SHIFT (0U)
#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
/*! @name TCR - RTC Time Compensation Register */
#define RTC_TCR_TCR_MASK (0xFFU)
#define RTC_TCR_TCR_SHIFT (0U)
#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
#define RTC_TCR_CIR_MASK (0xFF00U)
#define RTC_TCR_CIR_SHIFT (8U)
#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
#define RTC_TCR_TCV_MASK (0xFF0000U)
#define RTC_TCR_TCV_SHIFT (16U)
#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
#define RTC_TCR_CIC_MASK (0xFF000000U)
#define RTC_TCR_CIC_SHIFT (24U)
#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
/*! @name CR - RTC Control Register */
#define RTC_CR_SWR_MASK (0x1U)
#define RTC_CR_SWR_SHIFT (0U)
#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
#define RTC_CR_WPE_MASK (0x2U)
#define RTC_CR_WPE_SHIFT (1U)
#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
#define RTC_CR_SUP_MASK (0x4U)
#define RTC_CR_SUP_SHIFT (2U)
#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
#define RTC_CR_UM_MASK (0x8U)
#define RTC_CR_UM_SHIFT (3U)
#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
#define RTC_CR_WPS_MASK (0x10U)
#define RTC_CR_WPS_SHIFT (4U)
#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
#define RTC_CR_OSCE_MASK (0x100U)
#define RTC_CR_OSCE_SHIFT (8U)
#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
#define RTC_CR_CLKO_MASK (0x200U)
#define RTC_CR_CLKO_SHIFT (9U)
#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
#define RTC_CR_SC16P_MASK (0x400U)
#define RTC_CR_SC16P_SHIFT (10U)
#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
#define RTC_CR_SC8P_MASK (0x800U)
#define RTC_CR_SC8P_SHIFT (11U)
#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
#define RTC_CR_SC4P_MASK (0x1000U)
#define RTC_CR_SC4P_SHIFT (12U)
#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
#define RTC_CR_SC2P_MASK (0x2000U)
#define RTC_CR_SC2P_SHIFT (13U)
#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
/*! @name SR - RTC Status Register */
#define RTC_SR_TIF_MASK (0x1U)
#define RTC_SR_TIF_SHIFT (0U)
#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
#define RTC_SR_TOF_MASK (0x2U)
#define RTC_SR_TOF_SHIFT (1U)
#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
#define RTC_SR_TAF_MASK (0x4U)
#define RTC_SR_TAF_SHIFT (2U)
#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
#define RTC_SR_TCE_MASK (0x10U)
#define RTC_SR_TCE_SHIFT (4U)
#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
/*! @name LR - RTC Lock Register */
#define RTC_LR_TCL_MASK (0x8U)
#define RTC_LR_TCL_SHIFT (3U)
#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
#define RTC_LR_CRL_MASK (0x10U)
#define RTC_LR_CRL_SHIFT (4U)
#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
#define RTC_LR_SRL_MASK (0x20U)
#define RTC_LR_SRL_SHIFT (5U)
#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
#define RTC_LR_LRL_MASK (0x40U)
#define RTC_LR_LRL_SHIFT (6U)
#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
/*! @name IER - RTC Interrupt Enable Register */
#define RTC_IER_TIIE_MASK (0x1U)
#define RTC_IER_TIIE_SHIFT (0U)
#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
#define RTC_IER_TOIE_MASK (0x2U)
#define RTC_IER_TOIE_SHIFT (1U)
#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
#define RTC_IER_TAIE_MASK (0x4U)
#define RTC_IER_TAIE_SHIFT (2U)
#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
#define RTC_IER_TSIE_MASK (0x10U)
#define RTC_IER_TSIE_SHIFT (4U)
#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
#define RTC_IER_WPON_MASK (0x80U)
#define RTC_IER_WPON_SHIFT (7U)
#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
/*!
* @}
*/ /* end of group RTC_Register_Masks */
/* RTC - Peripheral instance base addresses */
/** Peripheral RTC base address */
#define RTC_BASE (0x4003D000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS { RTC_BASE }
/** Array initializer of RTC peripheral base pointers */
#define RTC_BASE_PTRS { RTC }
/** Interrupt vectors for the RTC peripheral type */
#define RTC_IRQS { RTC_IRQn }
#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
* @{
*/
/** SIM - Register Layout Typedef */
typedef struct {
__IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
uint8_t RESERVED_0[4096];
__IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
uint8_t RESERVED_1[4];
__IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
__IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
uint8_t RESERVED_2[4];
__IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
uint8_t RESERVED_3[8];
__I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint8_t RESERVED_4[12];
__IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
__IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
__IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
uint8_t RESERVED_5[4];
__IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
uint8_t RESERVED_6[4];
__IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
__I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
uint8_t RESERVED_7[4];
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
uint8_t RESERVED_8[156];
__IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
__O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
} SIM_Type;
/* ----------------------------------------------------------------------------
-- SIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Masks SIM Register Masks
* @{
*/
/*! @name SOPT1 - System Options Register 1 */
#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
#define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
/*! @name SOPT2 - System Options Register 2 */
#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
#define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
#define SIM_SOPT2_TPMSRC_SHIFT (24U)
#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
#define SIM_SOPT2_LPUART0SRC_MASK (0xC000000U)
#define SIM_SOPT2_LPUART0SRC_SHIFT (26U)
#define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK)
/*! @name SOPT4 - System Options Register 4 */
#define SIM_SOPT4_TPM1CH0SRC_MASK (0x40000U)
#define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
#define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
#define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
#define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
#define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
#define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
#define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
/*! @name SOPT5 - System Options Register 5 */
#define SIM_SOPT5_LPUART0TXSRC_MASK (0x1U)
#define SIM_SOPT5_LPUART0TXSRC_SHIFT (0U)
#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
#define SIM_SOPT5_LPUART0RXSRC_MASK (0x4U)
#define SIM_SOPT5_LPUART0RXSRC_SHIFT (2U)
#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
#define SIM_SOPT5_LPUART0ODE_MASK (0x10000U)
#define SIM_SOPT5_LPUART0ODE_SHIFT (16U)
#define SIM_SOPT5_LPUART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK)
/*! @name SOPT7 - System Options Register 7 */
#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
/*! @name SDID - System Device Identification Register */
#define SIM_SDID_PINID_MASK (0xFU)
#define SIM_SDID_PINID_SHIFT (0U)
#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
#define SIM_SDID_DIEID_MASK (0xF80U)
#define SIM_SDID_DIEID_SHIFT (7U)
#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
#define SIM_SDID_REVID_MASK (0xF000U)
#define SIM_SDID_REVID_SHIFT (12U)
#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
#define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
#define SIM_SDID_SRAMSIZE_SHIFT (16U)
#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
#define SIM_SDID_SERIESID_MASK (0xF00000U)
#define SIM_SDID_SERIESID_SHIFT (20U)
#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
#define SIM_SDID_SUBFAMID_SHIFT (24U)
#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
#define SIM_SDID_FAMID_MASK (0xF0000000U)
#define SIM_SDID_FAMID_SHIFT (28U)
#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
/*! @name SCGC4 - System Clock Gating Control Register 4 */
#define SIM_SCGC4_I2C0_MASK (0x40U)
#define SIM_SCGC4_I2C0_SHIFT (6U)
#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
#define SIM_SCGC4_CMP_MASK (0x80000U)
#define SIM_SCGC4_CMP_SHIFT (19U)
#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
#define SIM_SCGC4_VREF_MASK (0x100000U)
#define SIM_SCGC4_VREF_SHIFT (20U)
#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
#define SIM_SCGC4_SPI0_MASK (0x400000U)
#define SIM_SCGC4_SPI0_SHIFT (22U)
#define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
/*! @name SCGC5 - System Clock Gating Control Register 5 */
#define SIM_SCGC5_LPTMR_MASK (0x1U)
#define SIM_SCGC5_LPTMR_SHIFT (0U)
#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
#define SIM_SCGC5_PORTA_MASK (0x200U)
#define SIM_SCGC5_PORTA_SHIFT (9U)
#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
#define SIM_SCGC5_PORTB_MASK (0x400U)
#define SIM_SCGC5_PORTB_SHIFT (10U)
#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
#define SIM_SCGC5_LPUART0_MASK (0x100000U)
#define SIM_SCGC5_LPUART0_SHIFT (20U)
#define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK)
/*! @name SCGC6 - System Clock Gating Control Register 6 */
#define SIM_SCGC6_FTF_MASK (0x1U)
#define SIM_SCGC6_FTF_SHIFT (0U)
#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
#define SIM_SCGC6_TPM0_MASK (0x1000000U)
#define SIM_SCGC6_TPM0_SHIFT (24U)
#define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
#define SIM_SCGC6_TPM1_MASK (0x2000000U)
#define SIM_SCGC6_TPM1_SHIFT (25U)
#define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
#define SIM_SCGC6_ADC0_MASK (0x8000000U)
#define SIM_SCGC6_ADC0_SHIFT (27U)
#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
#define SIM_SCGC6_RTC_MASK (0x20000000U)
#define SIM_SCGC6_RTC_SHIFT (29U)
#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
/*! @name CLKDIV1 - System Clock Divider Register 1 */
#define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
/*! @name FCFG1 - Flash Configuration Register 1 */
#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
#define SIM_FCFG1_PFSIZE_SHIFT (24U)
#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
/*! @name FCFG2 - Flash Configuration Register 2 */
#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
/*! @name UIDMH - Unique Identification Register Mid-High */
#define SIM_UIDMH_UID_MASK (0xFFFFU)
#define SIM_UIDMH_UID_SHIFT (0U)
#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
/*! @name UIDML - Unique Identification Register Mid Low */
#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
#define SIM_UIDML_UID_SHIFT (0U)
#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
/*! @name UIDL - Unique Identification Register Low */
#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
#define SIM_UIDL_UID_SHIFT (0U)
#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
/*! @name COPC - COP Control Register */
#define SIM_COPC_COPW_MASK (0x1U)
#define SIM_COPC_COPW_SHIFT (0U)
#define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
#define SIM_COPC_COPCLKS_MASK (0x2U)
#define SIM_COPC_COPCLKS_SHIFT (1U)
#define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
#define SIM_COPC_COPT_MASK (0xCU)
#define SIM_COPC_COPT_SHIFT (2U)
#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
#define SIM_COPC_COPSTPEN_MASK (0x10U)
#define SIM_COPC_COPSTPEN_SHIFT (4U)
#define SIM_COPC_COPSTPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK)
#define SIM_COPC_COPDBGEN_MASK (0x20U)
#define SIM_COPC_COPDBGEN_SHIFT (5U)
#define SIM_COPC_COPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK)
#define SIM_COPC_COPCLKSEL_MASK (0xC0U)
#define SIM_COPC_COPCLKSEL_SHIFT (6U)
#define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK)
/*! @name SRVCOP - Service COP */
#define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
#define SIM_SRVCOP_SRVCOP_SHIFT (0U)
#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
/*!
* @}
*/ /* end of group SIM_Register_Masks */
/* SIM - Peripheral instance base addresses */
/** Peripheral SIM base address */
#define SIM_BASE (0x40047000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS { SIM_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS { SIM }
/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
* @{
*/
/** SMC - Register Layout Typedef */
typedef struct {
__IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
__IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
__IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
__I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
} SMC_Type;
/* ----------------------------------------------------------------------------
-- SMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Masks SMC Register Masks
* @{
*/
/*! @name PMPROT - Power Mode Protection register */
#define SMC_PMPROT_AVLLS_MASK (0x2U)
#define SMC_PMPROT_AVLLS_SHIFT (1U)
#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
#define SMC_PMPROT_AVLP_MASK (0x20U)
#define SMC_PMPROT_AVLP_SHIFT (5U)
#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
/*! @name PMCTRL - Power Mode Control register */
#define SMC_PMCTRL_STOPM_MASK (0x7U)
#define SMC_PMCTRL_STOPM_SHIFT (0U)
#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
#define SMC_PMCTRL_STOPA_MASK (0x8U)
#define SMC_PMCTRL_STOPA_SHIFT (3U)
#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
#define SMC_PMCTRL_RUNM_MASK (0x60U)
#define SMC_PMCTRL_RUNM_SHIFT (5U)
#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
/*! @name STOPCTRL - Stop Control Register */
#define SMC_STOPCTRL_VLLSM_MASK (0x7U)
#define SMC_STOPCTRL_VLLSM_SHIFT (0U)
#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
#define SMC_STOPCTRL_LPOPO_MASK (0x8U)
#define SMC_STOPCTRL_LPOPO_SHIFT (3U)
#define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK)
#define SMC_STOPCTRL_PORPO_MASK (0x20U)
#define SMC_STOPCTRL_PORPO_SHIFT (5U)
#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
/*! @name PMSTAT - Power Mode Status register */
#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
/*!
* @}
*/ /* end of group SMC_Register_Masks */
/* SMC - Peripheral instance base addresses */
/** Peripheral SMC base address */
#define SMC_BASE (0x4007E000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
/** Array initializer of SMC peripheral base addresses */
#define SMC_BASE_ADDRS { SMC_BASE }
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASE_PTRS { SMC }
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
* @{
*/
/** SPI - Register Layout Typedef */
typedef struct {
__IO uint8_t S; /**< SPI Status Register, offset: 0x0 */
__IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
__IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
__IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
__IO uint8_t M; /**< SPI Match Register, offset: 0x4 */
uint8_t RESERVED_0[1];
__IO uint8_t D; /**< SPI Data Register, offset: 0x6 */
} SPI_Type;
/* ----------------------------------------------------------------------------
-- SPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPI_Register_Masks SPI Register Masks
* @{
*/
/*! @name S - SPI Status Register */
#define SPI_S_MODF_MASK (0x10U)
#define SPI_S_MODF_SHIFT (4U)
#define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
#define SPI_S_SPTEF_MASK (0x20U)
#define SPI_S_SPTEF_SHIFT (5U)
#define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
#define SPI_S_SPMF_MASK (0x40U)
#define SPI_S_SPMF_SHIFT (6U)
#define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
#define SPI_S_SPRF_MASK (0x80U)
#define SPI_S_SPRF_SHIFT (7U)
#define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
/*! @name BR - SPI Baud Rate Register */
#define SPI_BR_SPR_MASK (0xFU)
#define SPI_BR_SPR_SHIFT (0U)
#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
#define SPI_BR_SPPR_MASK (0x70U)
#define SPI_BR_SPPR_SHIFT (4U)
#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
/*! @name C2 - SPI Control Register 2 */
#define SPI_C2_SPC0_MASK (0x1U)
#define SPI_C2_SPC0_SHIFT (0U)
#define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
#define SPI_C2_SPISWAI_MASK (0x2U)
#define SPI_C2_SPISWAI_SHIFT (1U)
#define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
#define SPI_C2_BIDIROE_MASK (0x8U)
#define SPI_C2_BIDIROE_SHIFT (3U)
#define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
#define SPI_C2_MODFEN_MASK (0x10U)
#define SPI_C2_MODFEN_SHIFT (4U)
#define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
#define SPI_C2_SPMIE_MASK (0x80U)
#define SPI_C2_SPMIE_SHIFT (7U)
#define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
/*! @name C1 - SPI Control Register 1 */
#define SPI_C1_LSBFE_MASK (0x1U)
#define SPI_C1_LSBFE_SHIFT (0U)
#define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
#define SPI_C1_SSOE_MASK (0x2U)
#define SPI_C1_SSOE_SHIFT (1U)
#define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
#define SPI_C1_CPHA_MASK (0x4U)
#define SPI_C1_CPHA_SHIFT (2U)
#define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
#define SPI_C1_CPOL_MASK (0x8U)
#define SPI_C1_CPOL_SHIFT (3U)
#define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
#define SPI_C1_MSTR_MASK (0x10U)
#define SPI_C1_MSTR_SHIFT (4U)
#define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
#define SPI_C1_SPTIE_MASK (0x20U)
#define SPI_C1_SPTIE_SHIFT (5U)
#define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
#define SPI_C1_SPE_MASK (0x40U)
#define SPI_C1_SPE_SHIFT (6U)
#define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
#define SPI_C1_SPIE_MASK (0x80U)
#define SPI_C1_SPIE_SHIFT (7U)
#define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
/*! @name M - SPI Match Register */
#define SPI_M_Bits_MASK (0xFFU)
#define SPI_M_Bits_SHIFT (0U)
#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_M_Bits_SHIFT)) & SPI_M_Bits_MASK)
/*! @name D - SPI Data Register */
#define SPI_D_Bits_MASK (0xFFU)
#define SPI_D_Bits_SHIFT (0U)
#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_D_Bits_SHIFT)) & SPI_D_Bits_MASK)
/*!
* @}
*/ /* end of group SPI_Register_Masks */
/* SPI - Peripheral instance base addresses */
/** Peripheral SPI0 base address */
#define SPI0_BASE (0x40076000u)
/** Peripheral SPI0 base pointer */
#define SPI0 ((SPI_Type *)SPI0_BASE)
/** Array initializer of SPI peripheral base addresses */
#define SPI_BASE_ADDRS { SPI0_BASE }
/** Array initializer of SPI peripheral base pointers */
#define SPI_BASE_PTRS { SPI0 }
/** Interrupt vectors for the SPI peripheral type */
#define SPI_IRQS { SPI0_IRQn }
/*!
* @}
*/ /* end of group SPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TPM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
* @{
*/
/** TPM - Register Layout Typedef */
typedef struct {
__IO uint32_t SC; /**< Status and Control, offset: 0x0 */
__IO uint32_t CNT; /**< Counter, offset: 0x4 */
__IO uint32_t MOD; /**< Modulo, offset: 0x8 */
struct { /* offset: 0xC, array step: 0x8 */
__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
} CONTROLS[2];
uint8_t RESERVED_0[52];
__IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
uint8_t RESERVED_1[48];
__IO uint32_t CONF; /**< Configuration, offset: 0x84 */
} TPM_Type;
/* ----------------------------------------------------------------------------
-- TPM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Register_Masks TPM Register Masks
* @{
*/
/*! @name SC - Status and Control */
#define TPM_SC_PS_MASK (0x7U)
#define TPM_SC_PS_SHIFT (0U)
#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
#define TPM_SC_CMOD_MASK (0x18U)
#define TPM_SC_CMOD_SHIFT (3U)
#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
#define TPM_SC_CPWMS_MASK (0x20U)
#define TPM_SC_CPWMS_SHIFT (5U)
#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
#define TPM_SC_TOIE_MASK (0x40U)
#define TPM_SC_TOIE_SHIFT (6U)
#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
#define TPM_SC_TOF_MASK (0x80U)
#define TPM_SC_TOF_SHIFT (7U)
#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
/*! @name CNT - Counter */
#define TPM_CNT_COUNT_MASK (0xFFFFU)
#define TPM_CNT_COUNT_SHIFT (0U)
#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
/*! @name MOD - Modulo */
#define TPM_MOD_MOD_MASK (0xFFFFU)
#define TPM_MOD_MOD_SHIFT (0U)
#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
/*! @name CnSC - Channel (n) Status and Control */
#define TPM_CnSC_ELSA_MASK (0x4U)
#define TPM_CnSC_ELSA_SHIFT (2U)
#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
#define TPM_CnSC_ELSB_MASK (0x8U)
#define TPM_CnSC_ELSB_SHIFT (3U)
#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
#define TPM_CnSC_MSA_MASK (0x10U)
#define TPM_CnSC_MSA_SHIFT (4U)
#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
#define TPM_CnSC_MSB_MASK (0x20U)
#define TPM_CnSC_MSB_SHIFT (5U)
#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
#define TPM_CnSC_CHIE_MASK (0x40U)
#define TPM_CnSC_CHIE_SHIFT (6U)
#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
#define TPM_CnSC_CHF_MASK (0x80U)
#define TPM_CnSC_CHF_SHIFT (7U)
#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
/* The count of TPM_CnSC */
#define TPM_CnSC_COUNT (2U)
/*! @name CnV - Channel (n) Value */
#define TPM_CnV_VAL_MASK (0xFFFFU)
#define TPM_CnV_VAL_SHIFT (0U)
#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
/* The count of TPM_CnV */
#define TPM_CnV_COUNT (2U)
/*! @name STATUS - Capture and Compare Status */
#define TPM_STATUS_CH0F_MASK (0x1U)
#define TPM_STATUS_CH0F_SHIFT (0U)
#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
#define TPM_STATUS_CH1F_MASK (0x2U)
#define TPM_STATUS_CH1F_SHIFT (1U)
#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
#define TPM_STATUS_TOF_MASK (0x100U)
#define TPM_STATUS_TOF_SHIFT (8U)
#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
/*! @name CONF - Configuration */
#define TPM_CONF_DOZEEN_MASK (0x20U)
#define TPM_CONF_DOZEEN_SHIFT (5U)
#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
#define TPM_CONF_DBGMODE_MASK (0xC0U)
#define TPM_CONF_DBGMODE_SHIFT (6U)
#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
#define TPM_CONF_GTBEEN_MASK (0x200U)
#define TPM_CONF_GTBEEN_SHIFT (9U)
#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
#define TPM_CONF_CSOT_MASK (0x10000U)
#define TPM_CONF_CSOT_SHIFT (16U)
#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
#define TPM_CONF_CSOO_MASK (0x20000U)
#define TPM_CONF_CSOO_SHIFT (17U)
#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
#define TPM_CONF_CROT_MASK (0x40000U)
#define TPM_CONF_CROT_SHIFT (18U)
#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
#define TPM_CONF_TRGSEL_MASK (0xF000000U)
#define TPM_CONF_TRGSEL_SHIFT (24U)
#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
/*!
* @}
*/ /* end of group TPM_Register_Masks */
/* TPM - Peripheral instance base addresses */
/** Peripheral TPM0 base address */
#define TPM0_BASE (0x40038000u)
/** Peripheral TPM0 base pointer */
#define TPM0 ((TPM_Type *)TPM0_BASE)
/** Peripheral TPM1 base address */
#define TPM1_BASE (0x40039000u)
/** Peripheral TPM1 base pointer */
#define TPM1 ((TPM_Type *)TPM1_BASE)
/** Array initializer of TPM peripheral base addresses */
#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE }
/** Array initializer of TPM peripheral base pointers */
#define TPM_BASE_PTRS { TPM0, TPM1 }
/** Interrupt vectors for the TPM peripheral type */
#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn }
/*!
* @}
*/ /* end of group TPM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VREF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
* @{
*/
/** VREF - Register Layout Typedef */
typedef struct {
__IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
__IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
} VREF_Type;
/* ----------------------------------------------------------------------------
-- VREF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VREF_Register_Masks VREF Register Masks
* @{
*/
/*! @name TRM - VREF Trim Register */
#define VREF_TRM_TRIM_MASK (0x3FU)
#define VREF_TRM_TRIM_SHIFT (0U)
#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
#define VREF_TRM_CHOPEN_MASK (0x40U)
#define VREF_TRM_CHOPEN_SHIFT (6U)
#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
/*! @name SC - VREF Status and Control Register */
#define VREF_SC_MODE_LV_MASK (0x3U)
#define VREF_SC_MODE_LV_SHIFT (0U)
#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
#define VREF_SC_VREFST_MASK (0x4U)
#define VREF_SC_VREFST_SHIFT (2U)
#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
#define VREF_SC_ICOMPEN_MASK (0x20U)
#define VREF_SC_ICOMPEN_SHIFT (5U)
#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
#define VREF_SC_REGEN_MASK (0x40U)
#define VREF_SC_REGEN_SHIFT (6U)
#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
#define VREF_SC_VREFEN_MASK (0x80U)
#define VREF_SC_VREFEN_SHIFT (7U)
#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
/*!
* @}
*/ /* end of group VREF_Register_Masks */
/* VREF - Peripheral instance base addresses */
/** Peripheral VREF base address */
#define VREF_BASE (0x40074000u)
/** Peripheral VREF base pointer */
#define VREF ((VREF_Type *)VREF_BASE)
/** Array initializer of VREF peripheral base addresses */
#define VREF_BASE_ADDRS { VREF_BASE }
/** Array initializer of VREF peripheral base pointers */
#define VREF_BASE_PTRS { VREF }
/*!
* @}
*/ /* end of group VREF_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma pop
#elif defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
#define I2C_S1_REG(base) I2C_S_REG(base)
#define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK
#define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT
#define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK
#define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFT
#define I2C_S1_SRW_MASK I2C_S_SRW_MASK
#define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT
#define I2C_S1_RAM_MASK I2C_S_RAM_MASK
#define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT
#define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK
#define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT
#define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK
#define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT
#define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK
#define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT
#define I2C_S1_TCF_MASK I2C_S_TCF_MASK
#define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT
#define I2C0_S1 I2C0_S
#define I2C_FLT_STOPIE_MASK This_symbol_has_been_deprecated
#define I2C_FLT_STOPIE_SHIFT This_symbol_has_been_deprecated
#define MCG_HCTRIM_COARSE_TRIM_MASK This_symbol_has_been_deprecated
#define MCG_HCTRIM_COARSE_TRIM_SHIFT This_symbol_has_been_deprecated
#define MCG_HCTRIM_COARSE_TRIM(x) This_symbol_has_been_deprecated
#define MCG_HTTRIM_TEMPCO_TRIM_MASK This_symbol_has_been_deprecated
#define MCG_HTTRIM_TEMPCO_TRIM_SHIFT This_symbol_has_been_deprecated
#define MCG_HTTRIM_TEMPCO_TRIM(x) This_symbol_has_been_deprecated
#define MCG_HFTRIM_FINE_TRIM_MASK This_symbol_has_been_deprecated
#define MCG_HFTRIM_FINE_TRIM_SHIFT This_symbol_has_been_deprecated
#define MCG_HFTRIM_FINE_TRIM(x) This_symbol_has_been_deprecated
#define MCG_LTRIMRNG_STRIMRNG_MASK This_symbol_has_been_deprecated
#define MCG_LTRIMRNG_STRIMRNG_SHIFT This_symbol_has_been_deprecated
#define MCG_LTRIMRNG_STRIMRNG(x) This_symbol_has_been_deprecated
#define MCG_LTRIMRNG_FTRIMRNG_MASK This_symbol_has_been_deprecated
#define MCG_LTRIMRNG_FTRIMRNG_SHIFT This_symbol_has_been_deprecated
#define MCG_LTRIMRNG_FTRIMRNG(x) This_symbol_has_been_deprecated
#define MCG_LFTRIM_LIRC_FTRIM_MASK This_symbol_has_been_deprecated
#define MCG_LFTRIM_LIRC_FTRIM_SHIFT This_symbol_has_been_deprecated
#define MCG_LFTRIM_LIRC_FTRIM(x) This_symbol_has_been_deprecated
#define MCG_LSTRIM_LIRC_STRIM_MASK This_symbol_has_been_deprecated
#define MCG_LSTRIM_LIRC_STRIM_SHIFT This_symbol_has_been_deprecated
#define MCG_LSTRIM_LIRC_STRIM(x) This_symbol_has_been_deprecated
#define PTA_BASE GPIOA_BASE
#define PTB_BASE GPIOB_BASE
#define PTA GPIOA
#define PTB GPIOB
#define FPTA_BASE FGPIOA_BASE
#define FPTB_BASE FGPIOB_BASE
#define FPTA FGPIOA
#define FPTB FGPIOB
/*!
* @}
*/ /* end of group SDK_Compatibility_Symbols */
#endif /* _MKL03Z4_H_ */
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