220 lines
11 KiB
C
220 lines
11 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_smc.h"
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#include "clock_config.h"
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#include "fsl_rtc.h"
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
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* and flash clock are in allowed range during clock mode switch.
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*
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* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
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*
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* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
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* internal reference clock(MCGIRCLK). Follow the steps to setup:
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*
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* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
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*
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* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
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* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
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* explicitly to setup MCGIRCLK.
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*
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* 3). Don't need to configure FLL explicitly, because if target mode is FLL
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* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
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* if the target mode is not FLL mode, the FLL is disabled.
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*
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* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
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* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
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* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
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*
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* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
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#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
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#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
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#define RTC_OSC_CAP_LOAD_12PF 0x1800U /*!< RTC oscillator capacity load: 12pF */
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#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */
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#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U /*!< CLKOUT pin clock select: FlexBus clock */
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#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
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#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
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#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
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#define SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK 0U /*!< RTC clock output select: RTC1HzCLK clock */
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#define SIM_RTC_CLKOUT_SEL_RTC32KCLK_CLK 1U /*!< RTC clock output select: RTC32KCLK clock (32.768kHz) */
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#define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK 1U /*!< Trace clock select: Core/system clock */
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#define SIM_USB_CLK_120000000HZ 120000000U /*!< Input SIM frequency for USB: 120000000Hz */
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#define SIM_USB_CLK_48000000HZ 48000000U /*!< Input SIM frequency for USB: 48000000Hz */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetRtcClock
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* Description : This function is used to configuring RTC clock including
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* enabling RTC oscillator.
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* Param capLoad : RTC oscillator capacity load
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* Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph)
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{
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/* RTC clock gate enable */
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CLOCK_EnableClock(kCLOCK_Rtc0);
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if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */
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/* Set the specified capacitor configuration for the RTC oscillator */
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RTC_SetOscCapLoad(RTC, capLoad);
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/* Enable the RTC 32KHz oscillator */
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RTC->CR |= RTC_CR_OSCE_MASK;
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}
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/* Output to other peripherals */
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if (enableOutPeriph) {
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RTC->CR &= ~RTC_CR_CLKO_MASK;
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}
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else {
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RTC->CR |= RTC_CR_CLKO_MASK;
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}
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/* Set the XTAL32/RTC_CLKIN frequency based on board setting. */
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CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
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/* Set RTC_TSR if there is fault value in RTC */
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if (RTC->SR & RTC_SR_TIF_MASK) {
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RTC -> TSR = RTC -> TSR;
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}
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/* RTC clock gate disable */
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CLOCK_DisableClock(kCLOCK_Rtc0);
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
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* Description : Configure FLL external reference divider (FRDIV).
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* Param frdiv : The value to set FRDIV.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
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{
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MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const mcg_config_t mcgConfig_BOARD_BootClockRUN =
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{
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.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
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.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
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.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
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.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
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.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
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.drs = kMCG_DrsLow, /* Low frequency range */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
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.oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */
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.pll0Config =
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{
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.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
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.prdiv = 0xbU, /* PLL Reference divider: divided by 12 */
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.vdiv = 0x6U, /* VCO divider: multiplied by 30 */
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},
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};
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const sim_clock_config_t simConfig_BOARD_BootClockRUN =
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{
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.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
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.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
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.clkdiv1 = 0x1340000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /5 */
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};
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const osc_config_t oscConfig_BOARD_BootClockRUN =
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{
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.freq = 0U, /* Oscillator frequency: 0Hz */
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.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
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.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
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.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
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}
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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{
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/* Set HSRUN power mode */
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SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
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SMC_SetPowerModeHsrun(SMC);
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while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
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{
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}
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/* Set the system clock dividers in SIM to safe value. */
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CLOCK_SetSimSafeDivs();
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/* Configure RTC clock including enabling RTC oscillator. */
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CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_12PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED);
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/* Configure the Internal Reference clock (MCGIRCLK). */
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CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
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mcgConfig_BOARD_BootClockRUN.ircs,
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mcgConfig_BOARD_BootClockRUN.fcrdiv);
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/* Configure FLL external reference divider (FRDIV). */
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CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
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/* Set MCG to PEE mode. */
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CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
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kMCG_PllClkSelPll0,
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&mcgConfig_BOARD_BootClockRUN.pll0Config);
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/* Set the clock configuration in SIM module. */
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CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
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/* Set RTC_CLKOUT source. */
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CLOCK_SetRtcClkOutClock(SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK);
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/* Enable USB FS clock. */
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CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcExt, SIM_USB_CLK_48000000HZ);
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/* Set CLKOUT source. */
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CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
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/* Set debug trace clock source. */
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CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK);
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}
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