From 5936129ebc8eae88b036b8a2140f9d10f7130cf8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?L=C3=A1szl=C3=B3=20Monda?= Date: Tue, 4 Oct 2016 18:36:01 +0200 Subject: [PATCH] Remove the include directory. Add init_clock.[ch] --- right/src/include/README.md | 4 - right/src/include/board/README.md | 5 - right/src/include/board/clock_config.c | 219 ------------------------- right/src/include/board/clock_config.h | 45 ----- right/src/init_clock.c | 148 +++++++++++++++++ right/src/init_clock.h | 8 + right/src/main.c | 4 +- 7 files changed, 158 insertions(+), 275 deletions(-) delete mode 100644 right/src/include/README.md delete mode 100644 right/src/include/board/README.md delete mode 100644 right/src/include/board/clock_config.c delete mode 100644 right/src/include/board/clock_config.h create mode 100644 right/src/init_clock.c create mode 100644 right/src/init_clock.h diff --git a/right/src/include/README.md b/right/src/include/README.md deleted file mode 100644 index 97b59e5..0000000 --- a/right/src/include/README.md +++ /dev/null @@ -1,4 +0,0 @@ -# Included files - -This directory contains included files upon which the firmware of the right keyboard half depends. -These dependencies are from external projects, and not supposed to be modified. diff --git a/right/src/include/board/README.md b/right/src/include/board/README.md deleted file mode 100644 index 5845c51..0000000 --- a/right/src/include/board/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# Development board specific files - -This directory contains files that are specific to the -[FRDM-K22F development board](http://www.nxp.com/products/software-and-tools/hardware-development-tools/freedom-development-boards/freescale-freedom-development-platform-for-kinetis-k22-mcus:FRDM-K22F) -upon which the firmware runs. diff --git a/right/src/include/board/clock_config.c b/right/src/include/board/clock_config.c deleted file mode 100644 index 5824491..0000000 --- a/right/src/include/board/clock_config.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -#include "fsl_smc.h" -#include "clock_config.h" -#include "fsl_rtc.h" -/* - * How to setup clock using clock driver functions: - * - * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock - * and flash clock are in allowed range during clock mode switch. - * - * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. - * - * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and - * internal reference clock(MCGIRCLK). Follow the steps to setup: - * - * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. - * - * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured - * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig - * explicitly to setup MCGIRCLK. - * - * 3). Don't need to configure FLL explicitly, because if target mode is FLL - * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, - * if the target mode is not FLL mode, the FLL is disabled. - * - * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been - * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could - * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. - * - * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ -#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ -#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ -#define RTC_OSC_CAP_LOAD_12PF 0x1800U /*!< RTC oscillator capacity load: 12pF */ -#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */ -#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U /*!< CLKOUT pin clock select: FlexBus clock */ -#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ -#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */ -#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ -#define SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK 0U /*!< RTC clock output select: RTC1HzCLK clock */ -#define SIM_RTC_CLKOUT_SEL_RTC32KCLK_CLK 1U /*!< RTC clock output select: RTC32KCLK clock (32.768kHz) */ -#define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK 1U /*!< Trace clock select: Core/system clock */ -#define SIM_USB_CLK_120000000HZ 120000000U /*!< Input SIM frequency for USB: 120000000Hz */ -#define SIM_USB_CLK_48000000HZ 48000000U /*!< Input SIM frequency for USB: 48000000Hz */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_CONFIG_SetRtcClock - * Description : This function is used to configuring RTC clock including - * enabling RTC oscillator. - * Param capLoad : RTC oscillator capacity load - * Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals - * - *END**************************************************************************/ -static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph) -{ - /* RTC clock gate enable */ - CLOCK_EnableClock(kCLOCK_Rtc0); - if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */ - /* Set the specified capacitor configuration for the RTC oscillator */ - RTC_SetOscCapLoad(RTC, capLoad); - /* Enable the RTC 32KHz oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; - } - /* Output to other peripherals */ - if (enableOutPeriph) { - RTC->CR &= ~RTC_CR_CLKO_MASK; - } - else { - RTC->CR |= RTC_CR_CLKO_MASK; - } - /* Set the XTAL32/RTC_CLKIN frequency based on board setting. */ - CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ); - /* Set RTC_TSR if there is fault value in RTC */ - if (RTC->SR & RTC_SR_TIF_MASK) { - RTC -> TSR = RTC -> TSR; - } - /* RTC clock gate disable */ - CLOCK_DisableClock(kCLOCK_Rtc0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_CONFIG_SetFllExtRefDiv - * Description : Configure FLL external reference divider (FRDIV). - * Param frdiv : The value to set FRDIV. - * - *END**************************************************************************/ -static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) -{ - MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ - - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const mcg_config_t mcgConfig_BOARD_BootClockRUN = - { - .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ - .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ - .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ - .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ - .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ - .drs = kMCG_DrsLow, /* Low frequency range */ - .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ - .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ - .pll0Config = - { - .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ - .prdiv = 0xbU, /* PLL Reference divider: divided by 12 */ - .vdiv = 0x6U, /* VCO divider: multiplied by 30 */ - }, - }; -const sim_clock_config_t simConfig_BOARD_BootClockRUN = - { - .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ - .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ - .clkdiv1 = 0x1340000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /5 */ - }; -const osc_config_t oscConfig_BOARD_BootClockRUN = - { - .freq = 0U, /* Oscillator frequency: 0Hz */ - .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ - .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */ - .oscerConfig = - { - .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */ - .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ - } - }; - -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Set HSRUN power mode */ - SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); - SMC_SetPowerModeHsrun(SMC); - while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) - { - } - /* Set the system clock dividers in SIM to safe value. */ - CLOCK_SetSimSafeDivs(); - /* Configure RTC clock including enabling RTC oscillator. */ - CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_12PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); - /* Configure the Internal Reference clock (MCGIRCLK). */ - CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, - mcgConfig_BOARD_BootClockRUN.ircs, - mcgConfig_BOARD_BootClockRUN.fcrdiv); - /* Configure FLL external reference divider (FRDIV). */ - CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); - /* Set MCG to PEE mode. */ - CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, - kMCG_PllClkSelPll0, - &mcgConfig_BOARD_BootClockRUN.pll0Config); - /* Set the clock configuration in SIM module. */ - CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; - /* Set RTC_CLKOUT source. */ - CLOCK_SetRtcClkOutClock(SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK); - /* Enable USB FS clock. */ - CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcExt, SIM_USB_CLK_48000000HZ); - /* Set CLKOUT source. */ - CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK); - /* Set debug trace clock source. */ - CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK); -} diff --git a/right/src/include/board/clock_config.h b/right/src/include/board/clock_config.h deleted file mode 100644 index 6e4af45..0000000 --- a/right/src/include/board/clock_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ -#include "fsl_common.h" - -#define BOARD_XTAL0_CLK_HZ 8000000U /*!< Board xtal0 frequency in Hz */ -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board RTC xtal frequency in Hz */ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */ - -extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; -extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; -extern const osc_config_t oscConfig_BOARD_BootClockRUN; - -void BOARD_BootClockRUN(void); - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/right/src/init_clock.c b/right/src/init_clock.c new file mode 100644 index 0000000..e8db090 --- /dev/null +++ b/right/src/init_clock.c @@ -0,0 +1,148 @@ +#include "fsl_smc.h" +#include "init_clock.h" +#include "fsl_rtc.h" + +// How to setup clock using clock driver functions: +// +// 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock +// and flash clock are in allowed range during clock mode switch. +// +// 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. +// +// 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and +// internal reference clock(MCGIRCLK). Follow the steps to setup: +// +// 1). Call CLOCK_BootToXxxMode to set MCG to target mode. +// +// 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured +// correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig +// explicitly to setup MCGIRCLK. +// +// 3). Don't need to configure FLL explicitly, because if target mode is FLL +// mode, then FLL has been configured by the function CLOCK_BootToXxxMode, +// if the target mode is not FLL mode, the FLL is disabled. +// +// 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been +// setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could +// be enabled independently, call CLOCK_EnablePll0 explicitly in this case. +// +// 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + +#define BOARD_XTAL32K_CLK_HZ 32768U // Board RTC xtal frequency in Hz +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U // Core clock frequency: 120000000Hz + +#define MCG_PLL_DISABLE 0U // MCGPLLCLK disabled +#define OSC_CAP0P 0U // Oscillator 0pF capacitor load +#define OSC_ER_CLK_DISABLE 0U // Disable external reference clock +#define RTC_OSC_CAP_LOAD_12PF 0x1800U // RTC oscillator capacity load: 12pF +#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U // RTC32KCLK to other peripherals: enabled +#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U // CLKOUT pin clock select: FlexBus clock +#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U // OSC32KSEL select: RTC32KCLK clock (32.768kHz) +#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U // PLLFLL select: IRC48MCLK clock +#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U // PLLFLL select: MCGPLLCLK clock +#define SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK 0U // RTC clock output select: RTC1HzCLK clock +#define SIM_RTC_CLKOUT_SEL_RTC32KCLK_CLK 1U // RTC clock output select: RTC32KCLK clock (32.768kHz) +#define SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK 1U // Trace clock select: Core/system clock +#define SIM_USB_CLK_120000000HZ 120000000U // Input SIM frequency for USB: 120000000Hz +#define SIM_USB_CLK_48000000HZ 48000000U // Input SIM frequency for USB: 48000000Hz + +extern uint32_t SystemCoreClock; // System clock frequency + +// Description: This function is used to configuring RTC clock including enabling RTC oscillator. +// Param capLoad: RTC oscillator capacity load +// Param enableOutPeriph: Enable (1U)/Disable (0U) clock to peripherals +static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph) +{ + // Enable RTC clock gate. + CLOCK_EnableClock(kCLOCK_Rtc0); + + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { // Only if the RTC oscillator is not already enabled. + RTC_SetOscCapLoad(RTC, capLoad); // Set the specified capacitor configuration for the RTC oscillator. + RTC->CR |= RTC_CR_OSCE_MASK; // Enable the RTC 32KHz oscillator. + } + + // Output to other peripherals. + if (enableOutPeriph) { + RTC->CR &= ~RTC_CR_CLKO_MASK; + } else { + RTC->CR |= RTC_CR_CLKO_MASK; + } + + CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ); // Set the XTAL32/RTC_CLKIN frequency based on board setting. + + // Set RTC_TSR if there is fault value in RTC. + if (RTC->SR & RTC_SR_TIF_MASK) { + RTC -> TSR = RTC -> TSR; + } + + // Disable RTC clock gate. + CLOCK_DisableClock(kCLOCK_Rtc0); +} + +// Description: Configure FLL external reference divider (FRDIV). +// Param frdiv: The value to set FRDIV. +static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) +{ + MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); +} + +const mcg_config_t mcgConfig_BOARD_BootClockRUN = + { + .mcgMode = kMCG_ModePEE, // PEE - PLL Engaged External + .irclkEnableMode = kMCG_IrclkEnable, // MCGIRCLK enabled, MCGIRCLK disabled in STOP mode + .ircs = kMCG_IrcSlow, // Slow internal reference clock selected + .fcrdiv = 0x0U, // Fast IRC divider: divided by 1 + .frdiv = 0x0U, // FLL reference clock divider: divided by 32 + .drs = kMCG_DrsLow, // Low frequency range + .dmx32 = kMCG_Dmx32Default, // DCO has a default range of 25% + .oscsel = kMCG_OscselIrc, // Selects 48 MHz IRC Oscillator + .pll0Config = + { + .enableMode = MCG_PLL_DISABLE, // MCGPLLCLK disabled + .prdiv = 0xbU, // PLL Reference divider: divided by 12 + .vdiv = 0x6U, // VCO divider: multiplied by 30 + }, + }; + +const sim_clock_config_t simConfig_BOARD_BootClockRUN = + { + .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, // PLLFLL select: MCGPLLCLK clock + .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, // OSC32KSEL select: RTC32KCLK clock (32.768kHz) + .clkdiv1 = 0x1340000U, // SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /5 + }; + +void InitClock(void) +{ + // Set HSRUN power mode. + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeHsrun(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) + { + } + // Set the system clock dividers in SIM to safe value. + CLOCK_SetSimSafeDivs(); + // Configure RTC clock including enabling RTC oscillator. + CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_12PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); + // Configure the Internal Reference clock (MCGIRCLK). + CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, + mcgConfig_BOARD_BootClockRUN.ircs, + mcgConfig_BOARD_BootClockRUN.fcrdiv); + // Configure FLL external reference divider (FRDIV). + CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); + // Set MCG to PEE mode. + CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, + kMCG_PllClkSelPll0, + &mcgConfig_BOARD_BootClockRUN.pll0Config); + // Set the clock configuration in SIM module. + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); + // Set SystemCoreClock variable. + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; + // Set RTC_CLKOUT source. + CLOCK_SetRtcClkOutClock(SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK); + // Enable USB FS clock. + CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcExt, SIM_USB_CLK_48000000HZ); + // Set CLKOUT source. + CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK); + // Set debug trace clock source. + CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_CORE_SYSTEM_CLK); +} diff --git a/right/src/init_clock.h b/right/src/init_clock.h new file mode 100644 index 0000000..1b0681f --- /dev/null +++ b/right/src/init_clock.h @@ -0,0 +1,8 @@ +#ifndef __INIT_CLOCK_H__ +#define __INIT_CLOCK_H__ + +// Functions: + + void InitClock(); + +#endif diff --git a/right/src/main.c b/right/src/main.c index 12b9b56..c9ba028 100644 --- a/right/src/main.c +++ b/right/src/main.c @@ -1,11 +1,11 @@ -#include "include/board/clock_config.h" +#include "init_clock.h" #include "init_peripherials.h" #include "usb_composite_device.h" #include "led_driver.h" void main() { InitPeripherials(); - BOARD_BootClockRUN(); + InitClock(); LedDriver_EnableAllLeds(); InitUsb();