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Remove const members.

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This commit is contained in:
László Monda
2017-06-16 11:51:08 +02:00
parent bdb94ac0ca
commit 30b30bf9c3
3 changed files with 5 additions and 5 deletions
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right/src/config/parse_keymap.c
+1 -1
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@@ -171,7 +171,7 @@ static void clearModule(uint8_t layer, uint8_t moduleId) {
memset(&CurrentKeymap[layer][moduleId], 0, MAX_KEY_COUNT_PER_MODULE * sizeof(key_action_t)); memset(&CurrentKeymap[layer][moduleId], 0, MAX_KEY_COUNT_PER_MODULE * sizeof(key_action_t));
} }
void ParseLayer(const uint8_t *data, uint8_t layer) { void ParseLayer(uint8_t *data, uint8_t layer) {
serialized_buffer_t buffer; serialized_buffer_t buffer;
buffer.buffer = data; buffer.buffer = data;
buffer.offset = 0; buffer.offset = 0;
right/src/config/parse_keymap.h
+2 -2
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@@ -33,12 +33,12 @@
} serialized_key_action_type_t; } serialized_key_action_type_t;
typedef struct { typedef struct {
const uint8_t *buffer; uint8_t *buffer;
uint16_t offset; uint16_t offset;
} serialized_buffer_t; } serialized_buffer_t;
// Functions: // Functions:
void ParseLayer(const uint8_t *data, uint8_t targetLayer); void ParseLayer(uint8_t *data, uint8_t layer);
#endif #endif
right/src/init_clock.c
+2 -2
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@@ -87,7 +87,7 @@ static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
} }
const mcg_config_t mcgConfig_BOARD_BootClockRUN = mcg_config_t mcgConfig_BOARD_BootClockRUN =
{ {
.mcgMode = kMCG_ModePEE, // PEE - PLL Engaged External .mcgMode = kMCG_ModePEE, // PEE - PLL Engaged External
.irclkEnableMode = kMCG_IrclkEnable, // MCGIRCLK enabled, MCGIRCLK disabled in STOP mode .irclkEnableMode = kMCG_IrclkEnable, // MCGIRCLK enabled, MCGIRCLK disabled in STOP mode
@@ -105,7 +105,7 @@ const mcg_config_t mcgConfig_BOARD_BootClockRUN =
}, },
}; };
const sim_clock_config_t simConfig_BOARD_BootClockRUN = sim_clock_config_t simConfig_BOARD_BootClockRUN =
{ {
.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, // PLLFLL select: MCGPLLCLK clock .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, // PLLFLL select: MCGPLLCLK clock
.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, // OSC32KSEL select: RTC32KCLK clock (32.768kHz) .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, // OSC32KSEL select: RTC32KCLK clock (32.768kHz)