659 lines
27 KiB
C
659 lines
27 KiB
C
/*
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* Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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////////////////////////////////////////////////////////////////////////////////
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// Variables
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////////////////////////////////////////////////////////////////////////////////
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#include "bootloader_common.h"
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#include "bootloader/bl_context.h"
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#include "fsl_device_registers.h"
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#include "port/fsl_port.h"
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#include "gpio/fsl_gpio.h"
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#include "peripherals_pinmux.h"
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#if (BL_CONFIG_LPUART || BL_CONFIG_SCUART || BL_CONFIG_UART)
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#if BL_ENABLE_PINMUX_UART4
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#define BL_ENABLED_MAX_UART_INSTANCE (4)
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#elif BL_ENABLE_PINMUX_UART3
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#define BL_ENABLED_MAX_UART_INSTANCE (3)
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#elif BL_ENABLE_PINMUX_UART2
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#define BL_ENABLED_MAX_UART_INSTANCE (2)
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#elif BL_ENABLE_PINMUX_UART1
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#define BL_ENABLED_MAX_UART_INSTANCE (1)
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#elif BL_ENABLE_PINMUX_UART0
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#define BL_ENABLED_MAX_UART_INSTANCE (0)
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#endif
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//! UART autobaud port irq configurations
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#define PORT_IRQC_INTERRUPT_ENABLED_PRIORITY 1
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#define PORT_IRQC_INTERRUPT_RESTORED_PRIORITY 0
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#define PORT_IRQC_INTERRUPT_FALLING_EDGE 0xA
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#define PORT_IRQC_INTERRUPT_DISABLE 0
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//! this is to store the function pointer for calling back to the function that wants
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//! the UART RX instance pin that triggered the interrupt. This only supports 1 pin
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//! for UART0 because UART1 is on PORTC which does not support interrupts :(
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static pin_irq_callback_t s_pin_irq_func[BL_ENABLED_MAX_UART_INSTANCE + 1] = { 0 };
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#endif // BL_CONFIG_LPUART
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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uint32_t PORT_GetPinIsf(PORT_Type *base, uint32_t pin)
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{
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return (base->PCR[pin] & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT;
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}
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static inline void PORT_RestoreDefault(PORT_Type *base, uint32_t pin)
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{
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base->PCR[pin] = 0;
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}
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#if (BL_CONFIG_LPUART || BL_CONFIG_SCUART || BL_CONFIG_UART)
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//! @brief Configure the GPIO mode for auto baud detection.
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static inline void PORT_SetUartAutoBaudPinMode(PORT_Type *portBase, GPIO_Type *gpioBase, uint32_t pin)
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{
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#if BL_FEATURE_UART_RX_PULLUP
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// Configure the UART RX pin to GPIO mode, with pull-up resistor enabled.
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portBase->PCR[pin] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
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#else
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// Configure the UART RX pin to GPIO mode
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portBase->PCR[pin] = PORT_PCR_MUX(1);
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#endif // BL_FEATURE_UART_RX_PULLUP
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// Configure UART RX pin to digital input mode.
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gpioBase->PDDR &= (uint32_t) ~(1 << pin);
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}
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static inline void PORT_SetUartPinMode(PORT_Type *base, uint32_t pin, uint32_t mux)
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{
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base->PCR[pin] = PORT_PCR_MUX(mux);
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}
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#endif
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#if (BL_CONFIG_I2C || BL_CONFIG_LPI2C)
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static inline void PORT_SetI2cPinMode(PORT_Type *base, uint32_t pin, uint32_t mux)
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{
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#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && (FSL_FEATURE_PORT_HAS_OPEN_DRAIN > 0)
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base->PCR[pin] = PORT_PCR_MUX(mux) | PORT_PCR_ODE(1);
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#else
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base->PCR[pin] = PORT_PCR_MUX(mux);
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#endif // //#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && (FSL_FEATURE_PORT_HAS_OPEN_DRAIN > 0)
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}
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#endif
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#if (BL_CONFIG_DSPI || BL_CONFIG_SPI || BL_CONFIG_LPSPI)
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static inline void PORT_SetSpiPinMode(PORT_Type *base, uint32_t pin, uint32_t mux)
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{
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base->PCR[pin] = PORT_PCR_MUX(mux);
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}
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#endif
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#if BL_CONFIG_CAN
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static inline void PORT_SetCanPinMode(PORT_Type *base, uint32_t pin, uint32_t mux)
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{
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base->PCR[pin] = PORT_PCR_MUX(mux);
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}
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#endif
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/*!
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* @brief Configure pinmux for uart module.
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*
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* This function only support switching default or gpio or fixed-ALTx mode on fixed pins
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* (Although there are many ALTx-pinmux configuration choices on various pins for the same
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* peripheral module)
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*/
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void uart_pinmux_config(uint32_t instance, pinmux_type_t pinmux)
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{
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switch (instance)
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{
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#if BL_ENABLE_PINMUX_UART0
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case 0:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(UART0_RX_PORT_BASE, UART0_RX_GPIO_PIN_NUM);
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PORT_RestoreDefault(UART0_TX_PORT_BASE, UART0_TX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_GPIO:
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PORT_SetUartAutoBaudPinMode(UART0_RX_PORT_BASE, UART0_RX_GPIO_BASE, UART0_RX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for UART0.
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PORT_SetUartPinMode(UART0_RX_PORT_BASE, UART0_RX_GPIO_PIN_NUM,
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UART0_RX_FUNC_ALT_MODE); // Set UART0_RX pin to UART0_RX functionality
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PORT_SetUartPinMode(UART0_TX_PORT_BASE, UART0_TX_GPIO_PIN_NUM,
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UART0_TX_FUNC_ALT_MODE); // Set UART0_TX pin to UART0_TX functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_UART0
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#if BL_ENABLE_PINMUX_UART1
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case 1:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(UART1_RX_PORT_BASE, UART1_RX_GPIO_PIN_NUM);
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PORT_RestoreDefault(UART1_TX_PORT_BASE, UART1_TX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_GPIO:
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PORT_SetUartAutoBaudPinMode(UART1_RX_PORT_BASE, UART1_RX_GPIO_BASE, UART1_RX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for UART1.
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PORT_SetUartPinMode(UART1_RX_PORT_BASE, UART1_RX_GPIO_PIN_NUM,
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UART1_RX_FUNC_ALT_MODE); // Set UART1_RX pin to UART1_RX functionality
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PORT_SetUartPinMode(UART1_TX_PORT_BASE, UART1_TX_GPIO_PIN_NUM,
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UART1_TX_FUNC_ALT_MODE); // Set UART1_TX pin to UART1_TX functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_UART1
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#if BL_ENABLE_PINMUX_UART2
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case 2:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(UART2_RX_PORT_BASE, UART2_RX_GPIO_PIN_NUM);
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PORT_RestoreDefault(UART2_TX_PORT_BASE, UART2_TX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_GPIO:
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PORT_SetUartAutoBaudPinMode(UART2_RX_PORT_BASE, UART2_RX_GPIO_BASE, UART2_RX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for UART2.
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PORT_SetUartPinMode(UART2_RX_PORT_BASE, UART2_RX_GPIO_PIN_NUM,
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UART2_RX_FUNC_ALT_MODE); // Set UART2_RX pin to UART2_RX functionality
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PORT_SetUartPinMode(UART2_TX_PORT_BASE, UART2_TX_GPIO_PIN_NUM,
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UART2_TX_FUNC_ALT_MODE); // Set UART2_TX pin to UART2_TX functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_UART2
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#if BL_ENABLE_PINMUX_UART3
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case 3:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(UART3_RX_PORT_BASE, UART3_RX_GPIO_PIN_NUM);
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PORT_RestoreDefault(UART3_TX_PORT_BASE, UART3_TX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_GPIO:
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PORT_SetUartAutoBaudPinMode(UART3_RX_PORT_BASE, UART3_RX_GPIO_BASE, UART3_RX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for UART3.
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PORT_SetUartPinMode(UART3_RX_PORT_BASE, UART3_RX_GPIO_PIN_NUM,
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UART3_RX_FUNC_ALT_MODE); // Set UART3_RX pin to UART3_RX functionality
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PORT_SetUartPinMode(UART3_TX_PORT_BASE, UART3_TX_GPIO_PIN_NUM,
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UART3_TX_FUNC_ALT_MODE); // Set UART3_TX pin to UART3_TX functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_UART3
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#if BL_ENABLE_PINMUX_UART4
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case 4:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(UART4_RX_PORT_BASE, UART4_RX_GPIO_PIN_NUM);
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PORT_RestoreDefault(UART4_TX_PORT_BASE, UART4_TX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_GPIO:
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PORT_SetUartAutoBaudPinMode(UART4_RX_PORT_BASE, UART4_RX_GPIO_BASE, UART4_RX_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for UART4.
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PORT_SetUartPinMode(UART4_RX_PORT_BASE, UART4_RX_GPIO_PIN_NUM,
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UART4_RX_FUNC_ALT_MODE); // Set UART4_RX pin to UART4_RX functionality
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PORT_SetUartPinMode(UART4_TX_PORT_BASE, UART4_TX_GPIO_PIN_NUM,
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UART4_TX_FUNC_ALT_MODE); // Set UART4_TX pin to UART4_TX functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_UART4
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default:
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break;
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}
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}
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/*!
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* @brief Configure pinmux for i2c module.
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*
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* This function only support switching default or gpio or fixed-ALTx mode on fixed pins
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* (Although there are many ALTx-pinmux configuration choices on various pins for the same
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* peripheral module)
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*/
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void i2c_pinmux_config(uint32_t instance, pinmux_type_t pinmux)
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{
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switch (instance)
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{
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#if BL_ENABLE_PINMUX_I2C0
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case 0:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(I2C0_SCL_PORT_BASE, I2C0_SCL_GPIO_PIN_NUM);
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PORT_RestoreDefault(I2C0_SDA_PORT_BASE, I2C0_SDA_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for I2C0.
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PORT_SetI2cPinMode(I2C0_SDA_PORT_BASE, I2C0_SDA_GPIO_PIN_NUM,
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I2C0_SDA_FUNC_ALT_MODE); // Set I2C0_SDA pin to I2C0_SDA functionality
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PORT_SetI2cPinMode(I2C0_SCL_PORT_BASE, I2C0_SCL_GPIO_PIN_NUM,
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I2C0_SCL_FUNC_ALT_MODE); // Set I2C0_SCL pin to I2C0_SCL functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_I2C0
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#if BL_ENABLE_PINMUX_I2C1
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case 1:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(I2C1_SCL_PORT_BASE, I2C1_SCL_GPIO_PIN_NUM);
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PORT_RestoreDefault(I2C1_SDA_PORT_BASE, I2C1_SDA_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for I2C1.
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PORT_SetI2cPinMode(I2C1_SDA_PORT_BASE, I2C1_SDA_GPIO_PIN_NUM,
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I2C1_SDA_FUNC_ALT_MODE); // Set I2C1_SDA pin to I2C1_SDA functionality
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PORT_SetI2cPinMode(I2C1_SCL_PORT_BASE, I2C1_SCL_GPIO_PIN_NUM,
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I2C1_SCL_FUNC_ALT_MODE); // Set I2C1_SCL pin to I2C1_SCL functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_I2C1
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#if BL_ENABLE_PINMUX_I2C2
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case 2:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(I2C2_SCL_PORT_BASE, I2C2_SCL_GPIO_PIN_NUM);
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PORT_RestoreDefault(I2C2_SDA_PORT_BASE, I2C2_SDA_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for I2C2.
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PORT_SetI2cPinMode(I2C2_SDA_PORT_BASE, I2C2_SDA_GPIO_PIN_NUM,
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I2C2_SDA_FUNC_ALT_MODE); // Set I2C2_SDA pin to I2C2_SDA functionality
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PORT_SetI2cPinMode(I2C2_SCL_PORT_BASE, I2C2_SCL_GPIO_PIN_NUM,
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I2C2_SCL_FUNC_ALT_MODE); // Set I2C2_SCL pin to I2C2_SCL functionality
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break;
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default:
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break;
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}
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#endif // #if BL_ENABLE_PINMUX_I2C2
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default:
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break;
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}
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}
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/*!
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* @brief Configure pinmux for SPI module.
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*
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* This function only support switching default or gpio or fixed-ALTx mode on fixed pins
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* (Although there are many ALTx-pinmux configuration choices on various pins for the same
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* peripheral module)
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*/
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void spi_pinmux_config(uint32_t instance, pinmux_type_t pinmux)
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{
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switch (instance)
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{
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#if BL_ENABLE_PINMUX_SPI0
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case 0:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(SPI0_PCS_PORT_BASE, SPI0_PCS_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI0_SCK_PORT_BASE, SPI0_SCK_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI0_SOUT_PORT_BASE, SPI0_SOUT_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI0_SIN_PORT_BASE, SPI0_SIN_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for SPI0
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PORT_SetSpiPinMode(SPI0_PCS_PORT_BASE, SPI0_PCS_GPIO_PIN_NUM,
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SPI0_PCS_FUNC_ALT_MODE); // Set SPI0_PCS pin to SPI0_PCS functionality
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PORT_SetSpiPinMode(SPI0_SCK_PORT_BASE, SPI0_SCK_GPIO_PIN_NUM,
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SPI0_SCK_FUNC_ALT_MODE); // Set SPI0_SCK pin to SPI0_SCK functionality
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PORT_SetSpiPinMode(SPI0_SOUT_PORT_BASE, SPI0_SOUT_GPIO_PIN_NUM,
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SPI0_SOUT_FUNC_ALT_MODE); // Set SPI0_SOUT pin to SPI0_SOUT functionality
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PORT_SetSpiPinMode(SPI0_SIN_PORT_BASE, SPI0_SIN_GPIO_PIN_NUM,
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SPI0_SIN_FUNC_ALT_MODE); // Set SPI0_SIN pin to SPI0_SIN functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_SPI0
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#if BL_ENABLE_PINMUX_SPI1
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case 1:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(SPI1_PCS_PORT_BASE, SPI1_PCS_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI1_SCK_PORT_BASE, SPI1_SCK_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI1_SOUT_PORT_BASE, SPI1_SOUT_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI1_SIN_PORT_BASE, SPI1_SIN_GPIO_PIN_NUM);
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break;
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case kPinmuxType_Peripheral:
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// Enable pins for SPI1
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PORT_SetSpiPinMode(SPI1_PCS_PORT_BASE, SPI1_PCS_GPIO_PIN_NUM,
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SPI1_PCS_FUNC_ALT_MODE); // Set SPI1_PCS pin to SPI1_PCS functionality
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PORT_SetSpiPinMode(SPI1_SCK_PORT_BASE, SPI1_SCK_GPIO_PIN_NUM,
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SPI1_SCK_FUNC_ALT_MODE); // Set SPI1_SCK pin to SPI1_SCK functionality
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PORT_SetSpiPinMode(SPI1_SOUT_PORT_BASE, SPI1_SOUT_GPIO_PIN_NUM,
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SPI1_SOUT_FUNC_ALT_MODE); // Set SPI1_SOUT pin to SPI1_SOUT functionality
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PORT_SetSpiPinMode(SPI1_SIN_PORT_BASE, SPI1_SIN_GPIO_PIN_NUM,
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SPI1_SIN_FUNC_ALT_MODE); // Set SPI1_SIN pin to SPI1_SIN functionality
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break;
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default:
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break;
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}
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break;
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#endif // #if BL_ENABLE_PINMUX_SPI1
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#if BL_ENABLE_PINMUX_SPI2
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case 2:
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switch (pinmux)
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{
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case kPinmuxType_Default:
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PORT_RestoreDefault(SPI2_PCS_PORT_BASE, SPI2_PCS_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI2_SCK_PORT_BASE, SPI2_SCK_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI2_SOUT_PORT_BASE, SPI2_SOUT_GPIO_PIN_NUM);
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PORT_RestoreDefault(SPI2_SIN_PORT_BASE, SPI2_SIN_GPIO_PIN_NUM);
|
|
break;
|
|
case kPinmuxType_Peripheral:
|
|
// Enable pins for SPI1
|
|
PORT_SetSpiPinMode(SPI2_PCS_PORT_BASE, SPI2_PCS_GPIO_PIN_NUM,
|
|
SPI2_PCS_FUNC_ALT_MODE); // Set SPI1_PCS pin to SPI1_PCS functionality
|
|
PORT_SetSpiPinMode(SPI2_SCK_PORT_BASE, SPI2_SCK_GPIO_PIN_NUM,
|
|
SPI2_SCK_FUNC_ALT_MODE); // Set SPI1_SCK pin to SPI1_SCK functionality
|
|
PORT_SetSpiPinMode(SPI2_SOUT_PORT_BASE, SPI2_SOUT_GPIO_PIN_NUM,
|
|
SPI2_SOUT_FUNC_ALT_MODE); // Set SPI1_SOUT pin to SPI1_SOUT functionality
|
|
PORT_SetSpiPinMode(SPI2_SIN_PORT_BASE, SPI2_SIN_GPIO_PIN_NUM,
|
|
SPI2_SIN_FUNC_ALT_MODE); // Set SPI1_SIN pin to SPI1_SIN functionality
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_SPI2
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* @brief Configure pinmux for CAN module.
|
|
*
|
|
* This function only support switching default or gpio or fixed-ALTx mode on fixed pins
|
|
* (Although there are many ALTx-pinmux configuration choices on various pins for the same
|
|
* peripheral module)
|
|
*/
|
|
void can_pinmux_config(uint32_t instance, pinmux_type_t pinmux)
|
|
{
|
|
switch (instance)
|
|
{
|
|
#if BL_ENABLE_PINMUX_CAN0
|
|
case 0:
|
|
switch (pinmux)
|
|
{
|
|
case kPinmuxType_Default:
|
|
PORT_RestoreDefault(CAN0_RX_PORT_BASE, CAN0_RX_GPIO_PIN_NUM);
|
|
PORT_RestoreDefault(CAN0_TX_PORT_BASE, CAN0_TX_GPIO_PIN_NUM);
|
|
break;
|
|
case kPinmuxType_Peripheral:
|
|
// Enable pins for CAN0
|
|
PORT_SetCanPinMode(CAN0_RX_PORT_BASE, CAN0_RX_GPIO_PIN_NUM,
|
|
CAN0_RX_FUNC_ALT_MODE); // Set CAN0_RX pin to CAN0_RX functionality
|
|
PORT_SetCanPinMode(CAN0_TX_PORT_BASE, CAN0_TX_GPIO_PIN_NUM,
|
|
CAN0_TX_FUNC_ALT_MODE); // Set CAN0_TX pin to CAN0_TX functionality
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_CAN0
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
//! @brief this is going to be used for autobaud IRQ handling for UART0
|
|
#if BL_ENABLE_PINMUX_UART0
|
|
void UART0_RX_GPIO_IRQHandler(void)
|
|
{
|
|
// Check if the pin for UART0 is what triggered the RX PORT interrupt
|
|
if (PORT_GetPinIsf(UART0_RX_PORT_BASE, UART0_RX_GPIO_PIN_NUM) && s_pin_irq_func[0])
|
|
{
|
|
s_pin_irq_func[0](0);
|
|
PORT_ClearPinsInterruptFlags(UART0_RX_PORT_BASE, ~0U);
|
|
}
|
|
}
|
|
#endif // #if BL_ENABLE_PINMUX_UART0
|
|
|
|
//! @brief this is going to be used for autobaud IRQ handling for UART1
|
|
#if BL_ENABLE_PINMUX_UART1
|
|
void UART1_RX_GPIO_IRQHandler(void)
|
|
{
|
|
// Check if the pin for UART1 is what triggered the RX PORT interrupt
|
|
if (PORT_GetPinIsf(UART1_RX_PORT_BASE, UART1_RX_GPIO_PIN_NUM) && s_pin_irq_func[1])
|
|
{
|
|
s_pin_irq_func[1](1);
|
|
PORT_ClearPinsInterruptFlags(UART1_RX_PORT_BASE, ~0U);
|
|
}
|
|
}
|
|
#endif // #if BL_ENABLE_PINMUX_UART1
|
|
|
|
//! @brief this is going to be used for autobaud IRQ handling for UART2
|
|
#if BL_ENABLE_PINMUX_UART2
|
|
void UART2_RX_GPIO_IRQHandler(void)
|
|
{
|
|
// Check if the pin for UART2 is what triggered the RX PORT interrupt
|
|
if (PORT_GetPinIsf(UART2_RX_PORT_BASE, UART2_RX_GPIO_PIN_NUM) && s_pin_irq_func[2])
|
|
{
|
|
s_pin_irq_func[2](2);
|
|
PORT_ClearPinsInterruptFlags(UART2_RX_PORT_BASE, ~0U);
|
|
}
|
|
}
|
|
#endif // #if BL_ENABLE_PINMUX_UART2
|
|
|
|
//! @brief this is going to be used for autobaud IRQ handling for UART3
|
|
#if BL_ENABLE_PINMUX_UART3
|
|
void UART3_RX_GPIO_IRQHandler(void)
|
|
{
|
|
// Check if the pin for UART3 is what triggered the RX PORT interrupt
|
|
if (PORT_GetPinIsf(UART3_RX_PORT_BASE, UART3_RX_GPIO_PIN_NUM) && s_pin_irq_func[3])
|
|
{
|
|
s_pin_irq_func[3](3);
|
|
PORT_ClearPinsInterruptFlags(UART3_RX_PORT_BASE, ~0U);
|
|
}
|
|
}
|
|
#endif // #if BL_ENABLE_PINMUX_UART3
|
|
|
|
//! @brief this is going to be used for autobaud IRQ handling for UART4
|
|
#if BL_ENABLE_PINMUX_UART4
|
|
void UART4_RX_GPIO_IRQHandler(void)
|
|
{
|
|
// Check if the pin for UART4 is what triggered the RX PORT interrupt
|
|
if (PORT_GetPinIsf(UART4_RX_PORT_BASE, UART4_RX_GPIO_PIN_NUM) && s_pin_irq_func[4])
|
|
{
|
|
s_pin_irq_func[4](4);
|
|
PORT_ClearPinsInterruptFlags(UART4_RX_PORT_BASE, ~0U);
|
|
}
|
|
}
|
|
#endif // #if BL_ENABLE_PINMUX_UART4
|
|
|
|
void enable_autobaud_pin_irq(uint32_t instance, pin_irq_callback_t func)
|
|
{
|
|
switch (instance)
|
|
{
|
|
#if BL_ENABLE_PINMUX_UART0
|
|
case 0:
|
|
NVIC_SetPriority(UART0_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_ENABLED_PRIORITY);
|
|
NVIC_EnableIRQ(UART0_RX_GPIO_IRQn);
|
|
// Only look for a falling edge for our interrupts
|
|
PORT_SetPinInterruptConfig(UART0_RX_PORT_BASE, UART0_RX_GPIO_PIN_NUM, kPORT_InterruptFallingEdge);
|
|
s_pin_irq_func[0] = func;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART0
|
|
|
|
#if BL_ENABLE_PINMUX_UART1
|
|
case 1:
|
|
NVIC_SetPriority(UART1_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_ENABLED_PRIORITY);
|
|
NVIC_EnableIRQ(UART1_RX_GPIO_IRQn);
|
|
// Only look for a falling edge for our interrupts
|
|
PORT_SetPinInterruptConfig(UART1_RX_PORT_BASE, UART1_RX_GPIO_PIN_NUM, kPORT_InterruptFallingEdge);
|
|
s_pin_irq_func[1] = func;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART1
|
|
|
|
#if BL_ENABLE_PINMUX_UART2
|
|
case 2:
|
|
NVIC_SetPriority(UART2_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_ENABLED_PRIORITY);
|
|
NVIC_EnableIRQ(UART2_RX_GPIO_IRQn);
|
|
// Only look for a falling edge for our interrupts
|
|
PORT_SetPinInterruptConfig(UART2_RX_PORT_BASE, UART2_RX_GPIO_PIN_NUM, kPORT_InterruptFallingEdge);
|
|
s_pin_irq_func[2] = func;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART2
|
|
|
|
#if BL_ENABLE_PINMUX_UART3
|
|
case 3:
|
|
NVIC_SetPriority(UART3_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_ENABLED_PRIORITY);
|
|
NVIC_EnableIRQ(UART3_RX_GPIO_IRQn);
|
|
// Only look for a falling edge for our interrupts
|
|
PORT_SetPinInterruptConfig(UART3_RX_PORT_BASE, UART3_RX_GPIO_PIN_NUM, kPORT_InterruptFallingEdge);
|
|
s_pin_irq_func[3] = func;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART3
|
|
|
|
#if BL_ENABLE_PINMUX_UART4
|
|
case 4:
|
|
NVIC_SetPriority(UART4_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_ENABLED_PRIORITY);
|
|
NVIC_EnableIRQ(UART4_RX_GPIO_IRQn);
|
|
// Only look for a falling edge for our interrupts
|
|
PORT_SetPinInterruptConfig(UART4_RX_PORT_BASE, UART4_RX_GPIO_PIN_NUM, kPORT_InterruptFallingEdge);
|
|
s_pin_irq_func[4] = func;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART4
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void disable_autobaud_pin_irq(uint32_t instance)
|
|
{
|
|
switch (instance)
|
|
{
|
|
#if BL_ENABLE_PINMUX_UART0
|
|
case 0:
|
|
NVIC_DisableIRQ(UART0_RX_GPIO_IRQn);
|
|
NVIC_SetPriority(UART0_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_RESTORED_PRIORITY);
|
|
PORT_SetPinInterruptConfig(UART0_RX_PORT_BASE, UART0_RX_GPIO_PIN_NUM, kPORT_InterruptOrDMADisabled);
|
|
s_pin_irq_func[0] = 0;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART0
|
|
|
|
#if BL_ENABLE_PINMUX_UART1
|
|
case 1:
|
|
NVIC_DisableIRQ(UART1_RX_GPIO_IRQn);
|
|
NVIC_SetPriority(UART1_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_RESTORED_PRIORITY);
|
|
PORT_SetPinInterruptConfig(UART1_RX_PORT_BASE, UART1_RX_GPIO_PIN_NUM, kPORT_InterruptOrDMADisabled);
|
|
s_pin_irq_func[1] = 0;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART1
|
|
|
|
#if BL_ENABLE_PINMUX_UART2
|
|
case 2:
|
|
NVIC_DisableIRQ(UART2_RX_GPIO_IRQn);
|
|
NVIC_SetPriority(UART2_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_RESTORED_PRIORITY);
|
|
PORT_SetPinInterruptConfig(UART2_RX_PORT_BASE, UART2_RX_GPIO_PIN_NUM, kPORT_InterruptOrDMADisabled);
|
|
s_pin_irq_func[2] = 0;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART2
|
|
|
|
#if BL_ENABLE_PINMUX_UART3
|
|
case 3:
|
|
NVIC_DisableIRQ(UART3_RX_GPIO_IRQn);
|
|
NVIC_SetPriority(UART3_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_RESTORED_PRIORITY);
|
|
PORT_SetPinInterruptConfig(UART3_RX_PORT_BASE, UART3_RX_GPIO_PIN_NUM, kPORT_InterruptOrDMADisabled);
|
|
s_pin_irq_func[3] = 0;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART3
|
|
|
|
#if BL_ENABLE_PINMUX_UART4
|
|
case 4:
|
|
NVIC_DisableIRQ(UART4_RX_GPIO_IRQn);
|
|
NVIC_SetPriority(UART4_RX_GPIO_IRQn, PORT_IRQC_INTERRUPT_RESTORED_PRIORITY);
|
|
PORT_SetPinInterruptConfig(UART4_RX_PORT_BASE, UART4_RX_GPIO_PIN_NUM, kPORT_InterruptOrDMADisabled);
|
|
s_pin_irq_func[4] = 0;
|
|
break;
|
|
#endif // #if BL_ENABLE_PINMUX_UART4
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// EOF
|
|
////////////////////////////////////////////////////////////////////////////////
|