331 lines
16 KiB
C
331 lines
16 KiB
C
/*
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** ###################################################################
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** GNU C Compiler - CodeSourcery Sourcery G++
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** IAR ANSI C/C++ Compiler for ARM
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**
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** Reference manual: KV31P100M120SF8RM, Rev. 1, March 24, 2014
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** Version: rev. 1.7, 2015-02-19
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** Build: b150225
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright (c) 2015 Freescale Semiconductor, Inc.
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 1.0 (2013-11-01)
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** Initial version.
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** - rev. 1.1 (2013-12-20)
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** Update according to reference manual rev. 0.6,
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** - rev. 1.2 (2014-02-06)
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** Update according to reference manual rev. 0.61,
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** - rev. 1.3 (2014-02-10)
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** The declaration of clock configurations has been moved to separate header file system_MKV31F25612.h
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** - rev. 1.4 (2014-04-30)
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** Update of MCM module according to the RM rev. 1.
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** Update of system and startup files.
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** Module access macro module_BASES replaced by module_BASE_PTRS.
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** - rev. 1.5 (2014-08-28)
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** Update of system files - default clock configuration changed.
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** Update of startup files - possibility to override DefaultISR added.
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** - rev. 1.6 (2014-10-14)
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** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
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** - rev. 1.7 (2015-02-19)
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** Renamed interrupt vector LLW to LLWU.
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**
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** ###################################################################
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*/
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/*!
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* @file MKV31F25612
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* @version 1.7
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* @date 2015-02-19
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* @brief Device specific configuration file for MKV31F25612 (header file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#ifndef _SYSTEM_MKV31F25612_H_
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#define _SYSTEM_MKV31F25612_H_ /**< Symbol preventing repeated inclusion */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#ifndef DISABLE_WDOG
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#define DISABLE_WDOG 1
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#endif
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/* MCG mode constants */
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#define MCG_MODE_FEI 0U
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#define MCG_MODE_FBI 1U
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#define MCG_MODE_BLPI 2U
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#define MCG_MODE_FEE 3U
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#define MCG_MODE_FBE 4U
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#define MCG_MODE_BLPE 5U
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#define MCG_MODE_PBE 6U
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#define MCG_MODE_PEE 7U
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/* Predefined clock setups
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0 ... Default part configuration
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Multipurpose Clock Generator (MCG) in FEI mode.
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Reference clock source for MCG module: Slow internal reference clock
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Core clock = 20.97152MHz
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Bus clock = 20.97152MHz
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1 ... Maximum achievable clock frequency configuration
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Multipurpose Clock Generator (MCG) in PEE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 120MHz
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Bus clock = 60MHz
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2 ... Chip internaly clocked, ready for Very Low Power Run mode.
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Multipurpose Clock Generator (MCG) in BLPI mode.
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Reference clock source for MCG module: Fast internal reference clock
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Core clock = 4MHz
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Bus clock = 4MHz
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3 ... Chip externally clocked, ready for Very Low Power Run mode.
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Multipurpose Clock Generator (MCG) in BLPE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 4MHz
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Bus clock = 4MHz
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4 ... Maximum achievable clock frequency configuration in RUN mode
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Multipurpose Clock Generator (MCG) in PEE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 80MHz
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Bus clock = 40MHz
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*/
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/* Define clock source values */
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#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 0u /* No RTC clock available */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
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/* RTC oscillator setting */
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/* Low power mode enable */
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/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
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#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
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/* Internal reference clock trim */
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/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
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#ifdef CLOCK_SETUP
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#if (CLOCK_SETUP == 0)
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#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
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#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
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/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
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/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
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#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
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/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
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#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
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/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
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/* SIM_SOPT2: LPUARTSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 1)
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#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
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#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
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/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
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/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
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#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
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/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
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#define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
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/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
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/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=4 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x01040000U /* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
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/* SIM_SOPT2: LPUARTSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,CLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 2)
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#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
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#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
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/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
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#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
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/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
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#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
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/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
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#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
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/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=4 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
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/* SIM_SOPT2: LPUARTSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 3)
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#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
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#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
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/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
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#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
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/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
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#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
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/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
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#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
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/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV4=7 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x11070000U /* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
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/* SIM_SOPT2: LPUARTSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 4)
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#define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
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#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
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/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
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/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
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#define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
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/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
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#define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
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/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x01030000U /* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
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/* SIM_SOPT2: LPUARTSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,CLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
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#endif
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#else
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#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
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#endif
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/**
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* @brief System clock frequency (core clock)
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*
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* The system clock frequency supplied to the SysTick timer and the processor
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* core clock. This variable can be used by the user application to setup the
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* SysTick timer or configure other parameters. It may also be used by debugger to
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* query the frequency of the debug timer or configure the trace clock speed
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* SystemCoreClock is initialized with a correct predefined value.
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*/
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extern uint32_t SystemCoreClock;
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/**
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* @brief Setup the microcontroller system.
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*
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* Typically this function configures the oscillator (PLL) that is part of the
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* microcontroller device. For systems with variable clock speed it also updates
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* the variable SystemCoreClock. SystemInit is called from startup_device file.
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*/
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void SystemInit(void);
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/**
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* @brief Updates the SystemCoreClock variable.
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*
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* It must be called whenever the core clock is changed during program
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* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
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* the current core clock.
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*/
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void SystemCoreClockUpdate(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* #if !defined(_SYSTEM_MKV31F25612_H_) */
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