202 lines
7.6 KiB
C
202 lines
7.6 KiB
C
/*
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* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "bootloader_common.h"
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#include "bootloader/bl_context.h"
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#include "property/property.h"
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#include "fsl_device_registers.h"
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#include <assert.h>
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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// Clock mode types
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typedef enum _target_clock_mode
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{
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kClockMode_FEI = 0,
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kClockMode_FEE = 1,
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kClockMode_Default = kClockMode_FEI,
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} target_clock_mode_t;
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////////////////////////////////////////////////////////////////////////////////
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// Prototypes
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////////////////////////////////////////////////////////////////////////////////
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// This function implements clock mode switch between FEI and PEE mode used in this bootloader
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void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode);
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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// See bootloader_common.h for documentation on this function.
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void configure_clocks(bootloader_clock_option_t option)
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{
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#if BL_TARGET_FLASH
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static target_clock_mode_t s_currentClockMode = kClockMode_FEI;
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static uint32_t s_defaultClockDivider;
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if (option == kClockOption_EnterBootloader)
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{
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s_defaultClockDivider = SIM->CLKDIV1;
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// General procedure to be implemented:
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// 1. Read clock flags and divider from bootloader config in property store
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bootloader_configuration_data_t *config = &g_bootloaderContext.propertyInterface->store->configurationData;
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uint8_t options = config->clockFlags;
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// 2. If NOT High Speed, do nothing (use reset clock config)
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if (options & kClockFlag_HighSpeed)
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{
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// High speed flag is set (meaning disabled), so just use default clocks.
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uint32_t coreClockDivider = (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1);
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SystemCoreClock = kDefaultClock / coreClockDivider;
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return;
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}
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// 3. Set OUTDIV1 based on divider in config. OUTDIV4 starts out at /1.
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// The divider values are masked by the maximum bits per divider.
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uint32_t div1 = ((~config->clockDivider) & (SIM_CLKDIV1_OUTDIV1_MASK >> SIM_CLKDIV1_OUTDIV1_SHIFT)) + 1;
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uint32_t div2 = 1;
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uint32_t div4 = 1;
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// 4. Get MCGOUTCLK
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uint32_t McgOutClk = kHIRC;
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// 5. Update SystemCoreClock global.
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SystemCoreClock = kHIRC / div1;
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// 6. Keep bus freq below max.
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//
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// The bus clock is divided by OUTDIV2:
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// MCGOUTCLK -> OUTDIV2 -> bus_clk
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uint32_t freq = McgOutClk;
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while ((freq / div2) > kMaxBusClock)
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{
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// Increase bus clock divider.
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++div2;
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}
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assert((div2 >= kDivider_Min) && (div2 <= kDivider_Max));
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// 7. Keep flash freq below max.
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//
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// The flash clock is diveded by OUTDIV4:
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// MCGOUTCLK -> OUTDIV4 ->flash_clk
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freq = McgOutClk;
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while ((freq / div4) > kMaxFlashClock)
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{
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// Increase bus/flash clock divider.
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++div4;
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}
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assert((div4 >= kDivider_Min) && (div4 <= kDivider_Max));
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if ((div1 == 1) && ((div2 > 8) || (div4 > 8)))
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{
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return;
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}
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// 8. Now set the dividers
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(div1 - 1) | SIM_CLKDIV1_OUTDIV2(div2 - 1) |
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SIM_CLKDIV1_OUTDIV4(div4 - 1); /* Update system prescalers */
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// 9. Switch to FEE mode.
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clock_mode_switch(s_currentClockMode, kClockMode_FEE);
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s_currentClockMode = kClockMode_FEE;
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}
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else if (option == kClockOption_ExitBootloader)
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{
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// Restore from FEE mode to FEI mode
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clock_mode_switch(s_currentClockMode, kClockMode_FEI);
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// Restore clock divider
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SIM->CLKDIV1 = s_defaultClockDivider;
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}
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#endif // BL_TARGET_FLASH
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}
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void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode)
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{
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// Note: here only implements clock switch between FEI and FEE,
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// The other modes are not supported.
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assert(currentMode == kClockMode_FEE || currentMode == kClockMode_FEI);
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assert(expectedMode == kClockMode_FEE || expectedMode == kClockMode_FEI);
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if (currentMode == expectedMode)
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{
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return;
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}
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if (expectedMode == kClockMode_FEE)
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{
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uint8_t tmp;
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/* Switch to FEE mode */
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tmp = MCG->C2;
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tmp &= (uint8_t)~MCG_C2_RANGE_MASK;
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tmp |= MCG_C2_RANGE(2);
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MCG->C2 = tmp; /* MCG_C2: RANGE = 2 */
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tmp = MCG->C1;
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tmp &= (uint8_t) ~(MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK);
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tmp |= MCG_C1_FRDIV(6);
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MCG->C1 = tmp; // FRDIV=6, RANGE=2, divide IRC48M with 1280, switch to external reference clock.
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tmp = MCG->C4;
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tmp &= (uint8_t)~MCG_C4_DRST_DRS_MASK;
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tmp |= MCG_C4_DRST_DRS(1);
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MCG->C4 = tmp; // Multiply with 1280, MCGOUTCLK is 48Mhz
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tmp = MCG->C7;
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tmp &= (uint8_t)~MCG_C7_OSCSEL_MASK;
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tmp |= MCG_C7_OSCSEL(2);
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MCG->C7 = tmp; // Select IRC48M as Oscillator.
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while (MCG->S & MCG_S_IREFST_MASK)
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; // Wait until external reference clock is ready.
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}
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else if (expectedMode == kClockMode_FEI)
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{
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MCG->C1 |= MCG_C1_IREFS_MASK; // Switch to internal reference clock.
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while (!(MCG->S & MCG_S_IREFST_MASK))
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; // Wait until internal reference clock is ready.
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// Restore registers to default value out of reset.
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MCG->C1 = 0x04U;
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MCG->C2 = 0x80U;
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MCG->C4 &= (uint8_t)MCG_C4_DRST_DRS_MASK;
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MCG->C7 = 0;
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}
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}
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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