228 lines
9.6 KiB
C
228 lines
9.6 KiB
C
/*
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** ###################################################################
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** Processors: MKL03Z32CAF4
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** MKL03Z32VFG4
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** MKL03Z16VFG4
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** MKL03Z8VFG4
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** MKL03Z32VFK4
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** MKL03Z16VFK4
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** MKL03Z8VFK4
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**
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** GNU C Compiler - CodeSourcery Sourcery G++
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** IAR ANSI C/C++ Compiler for ARM
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**
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** Reference manual: KL03P24M48SF0RM, Rev 2, Apr 2014
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** Version: rev. 1.4, 2014-08-28
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** Build: b141218
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright (c) 2014 Freescale Semiconductor, Inc.
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 1.0 (2013-12-11)
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** Initial version.
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** - rev. 1.1 (2014-04-16)
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** Update of the I2C module (SMBUS feature).
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** Update of the MCG_Light module.
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** Added register file system (RFSYS).
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** - rev. 1.2 (2014-04-30)
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** PEx compatibility macros has been added.
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** - rev. 1.3 (2014-06-27)
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** I2C_S1 register was renamed.
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** GPIO - Modules PTA,PTB renamed to GPIOA,GPIOB.
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** - rev. 1.4 (2014-08-28)
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** Update of system files - default clock configuration changed.
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** Update of startup files - possibility to override DefaultISR added.
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**
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** ###################################################################
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*/
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/*!
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* @file MKL03Z4
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* @version 1.4
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* @date 2014-08-28
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* @brief Device specific configuration file for MKL03Z4 (implementation file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "system_MKL03Z4.h"
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#include "fsl_device_registers.h"
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit(void)
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{
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#if (ACK_ISOLATION)
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if (PMC->REGSC & PMC_REGSC_ACKISO_MASK)
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{
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PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
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}
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#endif
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#if (DISABLE_WDOG)
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/* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
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SIM->COPC = (uint32_t)0x00u;
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#endif /* (DISABLE_WDOG) */
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#ifdef CLOCK_SETUP
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/* Power mode protection initialization */
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#ifdef SYSTEM_SMC_PMPROT_VALUE
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SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
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#endif
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/* System clock initialization */
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/* Set system prescalers and clock sources */
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SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
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SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) |
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((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
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SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_TPMSRC_MASK | SIM_SOPT2_LPUART0SRC_MASK))) |
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((SYSTEM_SIM_SOPT2_VALUE) &
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(SIM_SOPT2_TPMSRC_MASK | SIM_SOPT2_LPUART0SRC_MASK)); /* Select TPM and LPUART0 clock sources. */
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#if (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M || MCG_MODE == MCG_MODE_HIRC)
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/* Set MCG and OSC */
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#if (((OSC_CR_VALUE)&OSC_CR_ERCLKEN_MASK) != 0x00U)
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/* SIM_SCGC5: PORTA=1 */
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SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
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/* PORTA_PCR3: ISF=0,MUX=0 */
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PORTA_PCR3 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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if (((MCG_C2_VALUE)&MCG_C2_EREFS0_MASK) != 0x00U)
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{
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PORTA_PCR4 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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}
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#endif
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MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
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MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
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MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
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MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
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OSC->CR = OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
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#else /* MCG_MODE */
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/* Set MCG and OSC */
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/* SIM_SCGC5: PORTA=1 */
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SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
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/* PORTA_PCR3: ISF=0,MUX=0 */
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PORTA_PCR3 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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if (((MCG_C2_VALUE)&MCG_C2_EREFS0_MASK) != 0x00U)
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{
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PORTA_PCR4 &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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}
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MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
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MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
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OSC->CR = OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
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MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
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MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
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if (((MCG_C2_VALUE)&MCG_C2_EREFS0_MASK) != 0U)
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{
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while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U)
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{ /* Check that the oscillator is running */
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}
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}
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#endif /* MCG_MODE */
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/* Common for all MCG modes */
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#if (MCG_MODE == MCG_MODE_HIRC)
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while ((MCG->S & MCG_S_CLKST_MASK) != 0x00U)
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{ /* Wait until high internal reference clock is selected as MCG_Lite output */
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}
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#elif(MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M)
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while ((MCG->S & MCG_S_CLKST_MASK) != 0x04U)
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{ /* Wait until low internal reference clock is selected as MCG_Lite output */
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}
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#elif(MCG_MODE == MCG_MODE_EXT)
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while ((MCG->S & MCG_S_CLKST_MASK) != 0x08U)
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{ /* Wait until external reference clock is selected as MCG_Lite output */
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}
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#endif
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if (((SMC_PMCTRL_VALUE)&SMC_PMCTRL_RUNM_MASK) == SMC_PMCTRL_RUNM(0x02U))
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{
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SMC->PMCTRL = (uint8_t)((SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
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while (SMC->PMSTAT != 0x04U)
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{ /* Wait until the system is in VLPR mode */
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}
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}
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#endif
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate(void)
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{
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uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
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uint16_t Divider;
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if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U)
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{
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/* High internal reference clock is selected */
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MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
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}
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else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U)
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{
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/* Internal reference clock is selected */
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Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
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MCGOUTClock = (uint32_t)(CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
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}
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else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U)
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{
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/* External reference clock is selected */
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MCGOUTClock = CPU_XTAL_CLK_HZ;
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}
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else
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{
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/* Reserved value */
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return;
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} /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
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SystemCoreClock =
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(MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
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}
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