Add KBOOT.

validation/embedded_host/MK65F18/src/board.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include "port/fsl_port.h"
+#include "board.h"
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize Switch. */
+void BOARD_InitSwitch(void)
+{
+    gpio_pin_config_t switch_config = { kGPIO_DigitalInput, 0 };
+
+    GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_GPIO_PIN, &switch_config);
+    GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_GPIO_PIN, &switch_config);
+}
+
+/* Read Switch value. */
+bool BOARD_ReadSwitch(uint32_t switch_num)
+{
+    if (switch_num == kSwitch2)
+    {
+        return !(GPIO_ReadPinInput(BOARD_SW2_GPIO, BOARD_SW2_GPIO_PIN));
+    }
+    else if (switch_num == kSwitch3)
+    {
+        return !(GPIO_ReadPinInput(BOARD_SW3_GPIO, BOARD_SW3_GPIO_PIN));
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/* Initialize led. */
+void BOARD_InitLED(void)
+{
+    gpio_pin_config_t LED_config = { kGPIO_DigitalOutput, 1 };
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, &LED_config);
+    GPIO_PinInit(BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, &LED_config);
+    GPIO_PinInit(BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, &LED_config);
+    GPIO_PinInit(BOARD_LED_YELLOW_GPIO_PORT, BOARD_LED_YELLOW_GPIO_PIN, &LED_config);
+}

validation/embedded_host/MK65F18/src/board.h

@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "gpio/fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The board name */
+#define BOARD_NAME "TWR-K65F180M"
+
+/*! @brief The UART to use for debug messages. */
+#define BOARD_USE_UART
+#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_UART
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) UART2
+#define BOARD_DEBUG_UART_CLKSRC BUS_CLK
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/*! @brief The CAN instance used for board */
+#define BOARD_CAN_BASEADDR CAN0
+
+/*! @brief The i2c instance used for i2c connection by default */
+#define BOARD_I2C_BASEADDR I2C0
+
+/*! @brief The Flextimer instance/channel used for board */
+#define BOARD_FTM_BASEADDR FTM0
+#define BOARD_FTM_CHANNEL 2
+
+/*! @brief The TPM instance/channel used for board */
+#define BOARD_TPM_BASEADDR TPM2
+#define BOARD_TPM_CHANNEL 0
+
+/*! @brief The Enet instance used for board. */
+#define BOARD_ENET_BASEADDR ENET
+
+/*! @brief The FlexBus instance used for board.*/
+#define BOARD_FLEXBUS_BASEADDR FB
+
+#define BOARD_TSI_ELECTRODE_CNT 2
+
+/*! @brief Indexes of the TSI channels for on board electrodes */
+#define BOARD_TSI_ELECTRODE_1 11
+#define BOARD_TSI_ELECTRODE_2 12
+
+/*! @brief The SDHC instance/channel used for board */
+#define BOARD_SDHC_BASEADDR SDHC
+#define BOARD_SDHC_CD_GPIO_IRQ_HANDLER PORTA_IRQHandler
+
+/*! @brief The CMP instance/channel used for board. */
+#define BOARD_CMP_BASEADDR CMP2
+#define BOARD_CMP_CHANNEL 2
+
+/*! @brief The i2c instance used for sai demo */
+#define BOARD_SAI_DEMO_I2C_BASEADDR I2C0
+
+/*! @brief The rtc instance used for rtc_func */
+#define BOARD_RTC_FUNC_BASEADDR RTC
+
+/*! @brief If connected the TWR_MEM, this is spi sd card */
+#define BOARD_SDCARD_CARD_DETECTION_GPIO_PORT GPIOD
+#define SDCARD_CARD_DETECTION_GPIO_PIN 15
+#define SDCARD_CARD_WRITE_PROTECTION_GPIO_PORT GPIOC
+#define SDCARD_CARD_WRITE_PROTECTION_GPIO_PIN 13
+#define SDCARD_SPI_HW_BASEADDR SPI1
+#define SDCARD_CARD_INSERTED 0
+
+/*! @brief Define the port interrupt number for the board switches */
+enum
+{
+    kSwitch1,
+    kSwitch2,
+    kSwitch3,
+};
+#define BOARD_SW2_GPIO GPIOA
+#define BOARD_SW2_PORT PORTA
+#define BOARD_SW2_GPIO_PIN 4
+#define BOARD_SW2_IRQ PORTA_IRQn
+#define BOARD_SW2_IRQ_HANDLER PORTA_IRQHandler
+#define BOARD_SW2_NAME "SW2"
+#define BOARD_SW2_MASK (1u << BOARD_SW2_GPIO_PIN)
+
+#define BOARD_SW3_GPIO GPIOA
+#define BOARD_SW3_PORT PORTA
+#define BOARD_SW3_GPIO_PIN 10
+#define BOARD_SW3_IRQ PORTA_IRQn
+#define BOARD_SW3_IRQ_HANDLER PORTA_IRQHandler
+#define BOARD_SW3_NAME "SW3"
+#define BOARD_SW3_MASK (1u << BOARD_SW3_GPIO_PIN)
+
+#define BOARD_SW_IRQ_HANDLER PORTA_IRQHandler
+
+#define BOARD_LED_RED_GPIO_PORT GPIOB
+#define BOARD_LED_RED_GPIO_PIN 5
+#define BOARD_LED_RED_MASK (1u << BOARD_LED_RED_GPIO_PIN)
+#define BOARD_LED_GREEN_GPIO_PORT GPIOA
+#define BOARD_LED_GREEN_GPIO_PIN 28
+#define BOARD_LED_GREEN_MASK (1u << BOARD_LED_GREEN_GPIO_PIN)
+#define BOARD_LED_BLUE_GPIO_PORT GPIOA
+#define BOARD_LED_BLUE_GPIO_PIN 29
+#define BOARD_LED_BLUE_MASK (1u << BOARD_LED_BLUE_GPIO_PIN)
+#define BOARD_LED_YELLOW_GPIO_PORT GPIOB
+#define BOARD_LED_YELLOW_GPIO_PIN 4
+#define BOARD_LED_YELLOW_MASK (1u << BOARD_LED_YELLOW_GPIO_PIN)
+
+#define LED_RED_ON GPIO_ClearPinsOutput(BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_MASK)
+#define LED_RED_OFF GPIO_SetPinsOutput(BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_MASK)
+#define LED_GREEN_ON GPIO_ClearPinsOutput(BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_MASK)
+#define LED_GREEN_OFF GPIO_SetPinsOutput(BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_MASK)
+#define LED_BLUE_ON GPIO_ClearPinsOutput(BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_MASK)
+#define LED_BLUE_OFF GPIO_SetPinsOutput(BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_MASK)
+#define LED_YELLOW_ON GPIO_ClearPinsOutput(BOARD_LED_YELLOW_GPIO_PORT, BOARD_LED_YELLOW_MASK)
+#define LED_YELLOW_OFF GPIO_SetPinsOutput(BOARD_LED_YELLOW_GPIO_PORT, BOARD_LED_YELLOW_MASK)
+/*! @brief Define the port interrupt number for the usb id gpio pin */
+#define BOARD_ID_GPIO GPIOE
+#define BOARD_ID_PORT PORTE
+#define BOARD_ID_GPIO_PIN 10U
+#define BOARD_ID_IRQ PORTE_IRQn
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+extern void BOARD_InitHardware(void);
+void BOARD_InitSwitch(void);
+void BOARD_InitLED(void);
+bool BOARD_ReadSwitch(uint32_t switch_num);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

validation/embedded_host/MK65F18/src/host_hardware.h

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__HOST_HARDWARE_H__)
+#define __HOST_HARDWARE_H__
+
+#include "bootloader_common.h"
+#include "microseconds/microseconds.h"
+#include "dspi/fsl_dspi.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define UART_INSTANCE 4
+#define SPI_INSTANCE 2
+#define I2C_INSTANCE 0
+#define FLEXCAN_INSTANCE 0
+
+/*! @brief uart baud rate value limit */
+enum _uart_baud_value
+{
+    kUART_MIN_BAUD = 19200,
+    kUART_MAX_BAUD = 230400,
+    kUART_DEFAULT_BAUD = 57600
+};
+
+/*! @brief FelxCAN frequency */
+enum _flexcan_freq_value
+{
+    kFLEXCAN_125K = 125,
+    kFLEXCAN_250K = 250,
+    kFLEXCAN_500K = 500,
+    kFLEXCAN_750K = 750,
+    kFLEXCAN_1000K = 1000,
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @brief initialize all hardware */
+void hardware_init(void);
+
+/*! @brief receiving host char command process */
+bool wait_uart_char(uint8_t *data);
+uint8_t wait_uart_char_blocking(void);
+
+/*! @brief spi config speed process */
+void configure_spi_speed(uint32_t speedkhz);
+
+/*! @brief spi receiving data process */
+status_t receive_spi_data(uint8_t *dest, uint32_t readLength);
+
+/*! @brief spi send data process */
+status_t send_spi_data(uint8_t *src, uint32_t writeLength);
+
+/*! @brief i2c config speed process */
+void configure_i2c_speed(uint32_t speedkhz);
+
+/*! @brief i2c sending data process */
+status_t send_i2c_data(uint8_t *src, uint32_t writeLength);
+
+/*! @brief i2c receiving data process */
+status_t receive_i2c_data(uint8_t *dest, uint32_t readLength);
+
+/*! @brief uart config speed process */
+void configure_uart_speed(uint32_t baud);
+
+/*! @brief uart send data process */
+status_t send_uart_data(uint8_t *src, uint32_t writeLength);
+
+/*! @brief uart receiving data process */
+status_t receive_uart_data(uint8_t *dest, uint32_t readLength);
+
+/*! @brief flexCAN config speed process */
+void configure_can_speed(uint32_t speed);
+
+/*! @brief flexCAN sending data process */
+status_t send_can_data(uint8_t *src, uint32_t writeLength);
+
+/*! @brief flexCAN receiving data process */
+status_t receive_can_data(uint8_t *dest, uint32_t readLength);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* __HOST_HARDWARE_H__ */

validation/embedded_host/MK65F18/src/pin_mux.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "port/fsl_port.h"
+#include "pin_mux.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Initialize all pins used in this example
+ *
+ * @param disablePortClockAfterInit disable port clock after pin
+ * initialization or not.
+ */
+void BOARD_InitPins(void)
+{
+    port_pin_config_t pinConfig;
+    pinConfig.pullSelect = kPORT_PullUp;
+    pinConfig.openDrainEnable = kPORT_OpenDrainEnable;
+
+    /* Ungate the port clock */
+    SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
+                   SIM_SCGC5_PORTE_MASK);
+
+    /* Initialize UART2(OpenSDA) pins below */
+    PORT_SetPinMux(PORTE, 16u, kPORT_MuxAlt3); /* Affects PORTE_PCR16 register */
+    PORT_SetPinMux(PORTE, 17u, kPORT_MuxAlt3); /* Affects PORTE_PCR17 register */
+
+    /* Enable pins for UART4 on PTE24 - PTE25. */
+    PORT_SetPinMux(PORTE, 25u, kPORT_MuxAlt3); /* UART4_RX is ALT3 for pin PTE25 */
+    PORT_SetPinMux(PORTE, 24u, kPORT_MuxAlt3); /* UART4_TX is ALT3 for pin PTE24 */
+
+    /* Enable pins for I2C0 on PTE18 - PTE19. */
+    PORT_SetPinConfig(PORTE, 18u, &pinConfig); /* I2C0_SCL set for open drain */
+    PORT_SetPinConfig(PORTE, 19u, &pinConfig); /* I2C0_SDA set for open drain */
+    PORT_SetPinMux(PORTE, 18u, kPORT_MuxAlt4); /* I2C0_SCL is ALT4 for pin PTE18 */
+    PORT_SetPinMux(PORTE, 19u, kPORT_MuxAlt4); /* I2C0_SDA is ALT4 for pin PTE19 */
+
+    /* Enable pins for SPI0 on PTD0 - PTD3. */
+    PORT_SetPinMux(PORTD, 11u, kPORT_MuxAlt2); /* SPI0_PCS0 is ALT2 for pin PTD11 */
+    PORT_SetPinMux(PORTD, 12u, kPORT_MuxAlt2); /* SPI0_SCK  is ALT2 for pin PTD12 */
+    PORT_SetPinMux(PORTD, 13u, kPORT_MuxAlt2); /* SPI0_SOUT is ALT2 for pin PTD13 */
+    PORT_SetPinMux(PORTD, 14u, kPORT_MuxAlt2); /* SPI0_SIN  is ALT2 for pin PTD14 */
+
+    /* LED PTA28 */
+    PORT_SetPinMux(PORTA, 28u, kPORT_MuxAsGpio);
+    PORT_SetPinMux(PORTA, 29u, kPORT_MuxAsGpio);
+    PORT_SetPinMux(PORTB, 4u, kPORT_MuxAsGpio);
+    PORT_SetPinMux(PORTB, 5u, kPORT_MuxAsGpio);
+
+    /* SW2 PTA4 */
+    PORT_SetPinMux(PORTA, 4u, kPORT_MuxAsGpio);
+    /* SW3 PTA10 */
+    PORT_SetPinMux(PORTA, 10u, kPORT_MuxAsGpio);
+
+    /* Enable pins for FLEXCAN0 on PTA30 - PTA31. */
+    PORT_SetPinMux(PORTA, 30u, kPORT_MuxAlt2); /* FLEXCAN0_TX is ALT2 for pin PTA30 */
+    PORT_SetPinMux(PORTA, 31u, kPORT_MuxAlt2); /* FLEXCAN0_RX is ALT2 for pin PTA31 */
+}

validation/embedded_host/MK65F18/src/pin_mux.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include <stdbool.h>
+#include "fsl_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+       /*!
+       * @brief configure all pins for this demo/example
+       */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _PIN_MUX_H_ */

validation/embedded_host/MK65F18/src/system_MK65F18.h

@@ -0,0 +1,433 @@
+/*
+** ###################################################################
+**     Processors:          MK65FN2M0CAC18
+**                          MK65FX1M0CAC18
+**                          MK65FN2M0VMI18
+**                          MK65FX1M0VMI18
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K65P169M180SF5RMV2, Rev. 1, Mar 2015
+**     Version:             rev. 3.0, 2015-03-25
+**     Build:               b151215
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-09-02)
+**         Initial version.
+**     - rev. 2.0 (2014-02-17)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**         Update according to reference manual rev. 2
+**     - rev. 2.1 (2014-04-16)
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.2 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.3 (2014-11-20)
+**         Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
+**         Update of SystemInit() to use 16MHz external crystal.
+**     - rev. 2.4 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 3.0 (2015-03-25)
+**         Registers updated according to the reference manual revision 1, March 2015
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK65F18
+ * @version 3.0
+ * @date 2015-03-25
+ * @brief Device specific configuration file for MK65F18 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MK65F18_H_
+#define _SYSTEM_MK65F18_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef DISABLE_WDOG
+#define DISABLE_WDOG 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximal speed configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 180MHz
+         Bus clock  = 60MHz
+   2 ... Chip internally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+   5 ... Maximum achievable clock frequency configuration in RUN mode
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ \
+    16000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ                                                                       \
+    32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
+              */
+#define CPU_INT_SLOW_CLK_HZ 32768U   /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */      /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */      /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
+#define MCG_MODE MCG_MODE_FEI          /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
+#define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
+/* MCG_C11: PLLCS=0 */
+#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x02U /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+                                           /* SIM_SOPT2:
+                                            * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
+                                            */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 1)
+#define DEFAULT_SYSTEM_CLOCK 180000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE      /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U  /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U  /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U  /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U  /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
+#define SYSTEM_MCG_C5_VALUE 0x01U  /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x1D */
+#define SYSTEM_MCG_C6_VALUE 0x5DU  /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U  /* MCG_C7 */
+/* MCG_C9: PLL_CME=1,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
+#define SYSTEM_MCG_C9_VALUE 0x20U  /* MCG_C9 */
+/* MCG_C11: PLLCS=0 */
+#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U  /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=2,OUTDIV3=2,OUTDIV4=6 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x02260000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=6,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x0CU       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 2)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPI     /* Clock generator mode */
+/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x46U  /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U  /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U  /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U  /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U  /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U  /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U  /* MCG_C7 */
+/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
+#define SYSTEM_MCG_C9_VALUE 0x00U  /* MCG_C9 */
+/* MCG_C11: PLLCS=0 */
+#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U  /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x00U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 3)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPE     /* Clock generator mode */
+/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0xA2U  /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U  /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U  /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x02U  /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U  /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U  /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U  /* MCG_C7 */
+/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
+#define SYSTEM_MCG_C9_VALUE 0x00U  /* MCG_C9 */
+/* MCG_C11: PLLCS=0 */
+#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U  /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=3,OUTDIV2=3,OUTDIV3=3,OUTDIV4=0x0F */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x333F0000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x00U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 4)
+#define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE      /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U  /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U  /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U  /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U  /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
+#define SYSTEM_MCG_C5_VALUE 0x01U  /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x0E */
+#define SYSTEM_MCG_C6_VALUE 0x4EU  /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U  /* MCG_C7 */
+/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
+#define SYSTEM_MCG_C9_VALUE 0x00U  /* MCG_C9 */
+/* MCG_C11: PLLCS=0 */
+#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U  /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x12U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 5)
+#define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE      /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U  /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U  /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U  /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U  /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
+#define SYSTEM_MCG_C5_VALUE 0x01U  /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x0E */
+#define SYSTEM_MCG_C6_VALUE 0x4EU  /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U  /* MCG_C7 */
+/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
+#define SYSTEM_MCG_C9_VALUE 0x00U  /* MCG_C9 */
+/* MCG_C11: PLLCS=0 */
+#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U  /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x12U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#else
+#error The selected clock setup is not supported.
+#endif
+#else
+#define DEFAULT_SYSTEM_CLOCK 20971520u
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MK65F18_H_ */

validation/embedded_host/MK65F18/src/target_config.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__TARGET_CONFIG_H__)
+#define __TARGET_CONFIG_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+//! @brief Constants for clock frequencies.
+enum _target_clocks
+{
+    kDefaultClock = 20971520u,
+    kMcgOutWithFullSpeedUsb = 48000000u,
+    kMcgOutWithHighSpeedUsb = 120000000u,
+    kMinCoreClockWithFsUsbSupport = 20000000u,
+    kMaxCoreClock = 180000000u,
+    kMaxBusClock = 60000000u,
+    kMaxFlexBusClock = 60000000u,
+    kMaxFlashClock = 28000000u,
+
+    kDivider_Min = 1,
+    kDivider_Max = 16,
+};
+
+//! @brief Constants for sram partition
+enum _sram_partition
+{
+    kSram_LowerPart = 1,
+    kSram_UpperPart = 3,
+};
+
+//! @brief Version constants for the target.
+enum _target_version_constants
+{
+    kTarget_Version_Name = 'T',
+    kTarget_Version_Major = 1,
+    kTarget_Version_Minor = 0,
+    kTarget_Version_Bugfix = 0
+};
+
+#endif // __TARGET_CONFIG_H__