Add KBOOT.

targets/MKV58F22/src/bootloader_config.h

@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __BOOTLOADER_CONFIG_H__
+#define __BOOTLOADER_CONFIG_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//
+// Bootloader configuration options
+//
+
+//! @name Peripheral configuration macros
+//@{
+
+#if !defined(BL_CONFIG_SCUART)
+#define BL_CONFIG_SCUART (1)
+#endif
+#if !defined(BL_CONFIG_I2C)
+#define BL_CONFIG_I2C (1)
+#endif
+#if !defined(BL_CONFIG_DSPI)
+#define BL_CONFIG_DSPI (1)
+#endif
+#if !defined(BL_CONFIG_CAN)
+#define BL_CONFIG_CAN (1)
+#endif
+
+//@}
+
+#if !defined(BL_TARGET_FLASH) && !defined(BL_TARGET_RAM)
+#define BL_TARGET_FLASH (1)
+#endif
+
+#if defined(BL_TARGET_RAM)
+#define BL_FEATURE_FLASH_SECURITY (0)
+#else
+#define BL_FEATURE_FLASH_SECURITY (1)
+#endif
+
+#define BL_FEATURE_CRC_CHECK (0)
+
+#define BL_FEATURE_QSPI_MODULE (0)
+#define BL_FEATURE_ENCRYPTION_MMCAU (1)
+#define BL_FEATURE_ENCRYPTION (BL_FEATURE_ENCRYPTION_MMCAU)
+#define BL_FEATURE_ENCRYPTION_KEY_ADDRESS 0xb000 // NOTE: this address must be 4-byte aligned.
+
+#define BL_FEATURE_UART_AUTOBAUD_IRQ (1)
+
+#define BL_FEATURE_CAN (BL_CONFIG_CAN)
+
+#define BL_FEATURE_READ_MEMORY (1)
+#define BL_FEATURE_FILL_MEMORY (1)
+
+#define BL_FEATURE_MIN_PROFILE (0)
+
+#define BL_FEATURE_ERASEALL_UNSECURE (1)
+
+#define BL_FEATURE_ENABLE_FLASH_PROGRAM_SECTION (1)
+
+// Bootloader peripheral detection default timeout in milliseconds
+// After coming out of reset the bootloader will spin in a peripheral detection
+// loop for this amount of time. A zero value means no time out.
+#if DEBUG
+#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 0
+#else
+#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 5000
+#endif // DEBUG
+
+#define BL_FEATURE_POWERDOWN (0)
+
+// Bootloader powerdown timeout in milliseconds
+// The bootloader enters a low power mode after waiting for this amount of time. A zero value means // no time out. Only
+// applicable if BL_FEATURE_POWERDOWN is enabled.
+#if DEBUG
+#define BL_DEFAULT_POWERDOWN_TIMEOUT 10000
+#else
+#define BL_DEFAULT_POWERDOWN_TIMEOUT 600000
+#endif // DEBUG
+
+// The bootloader will check this address for the application vector table upon startup.
+#if !defined(BL_APP_VECTOR_TABLE_ADDRESS)
+#define BL_APP_VECTOR_TABLE_ADDRESS 0x1000a000
+#endif
+
+/* Serial Port Info */
+
+/**************************************************************************
+ * Note:
+ *
+ * Because of the changes to the UART modules, we can no longer define
+ * the TERM_PORT as a base pointer.  The uart functions have been modified
+ * accommodate this change.  Now, TERM_PORT_NUM must be defined as the
+ * number of the UART port desired to use
+ *
+ * TERM_PORT_NUM = 0  -- This allows you to use UART0; default pins are
+ *                        PTA14 and PTA15
+ *
+ * TERM_PORT_NUM = 1  -- This allows you to use UART1; default pins are
+ *                        PTC3 and PTC4
+ *
+ * TERM_PORT_NUM = 2  -- This allows you to use UART2; default pins are
+ *                        PTD2 and PTD3
+ *
+ *************************************************************************/
+#define TERM_PORT_NUM 0
+
+#define TERMINAL_BAUD 19200
+#undef HW_FLOW_CONTROL
+
+#endif // __BOOTLOADER_CONFIG_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

targets/MKV58F22/src/clock_config_KV58F22.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bootloader_common.h"
+#include "bootloader/bl_context.h"
+#include "property/property.h"
+#include "fsl_device_registers.h"
+#include <assert.h>
+
+////////////////////////////////////////////////////////////////////////////////
+// Declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+// See bootloader_common.h for documentation on this function.
+void configure_clocks(bootloader_clock_option_t option)
+{
+#if BL_TARGET_ROM
+    static uint32_t s_defaultClockDivider;
+    if (option == kClockOption_EnterBootloader)
+    {
+        s_defaultClockDivider = SIM->CLKDIV1;
+        // General procedure to be implemented:
+        // 1. Read clock flags and divider from bootloader config in property store
+        bootloader_configuration_data_t *config = &g_bootloaderContext.propertyInterface->store->configurationData;
+        uint8_t options = config->clockFlags;
+
+        // 2. If NOT High Speed, do nothing (use reset clock config)
+        if (options & kClockFlag_HighSpeed)
+        {
+            // High speed flag is set (meaning disabled), so just use default clocks.
+            uint32_t coreClockDivider = (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1);
+            SystemCoreClock = kDefaultClock / coreClockDivider;
+            return;
+        }
+
+        // 3. Set OUTDIV1 based on divider in config. OUTDIV4 starts out at /1.
+        // The divider values are masked by the maximum bits per divider.
+        uint32_t div1 = ((~config->clockDivider) & (SIM_CLKDIV1_OUTDIV1_MASK >> SIM_CLKDIV1_OUTDIV1_SHIFT)) + 1;
+
+        // 4. Get MCGOUTCLK
+        uint32_t McgOutClk = kDefaultClock;
+
+        // 5. Keep core clock up kMinCoreClockWithUsbSupport if usb is supported.
+        uint32_t freq = McgOutClk;
+
+        // 6. Keep core clock below kMaxCoreClock
+        while ((freq / div1) > kMaxCoreClock)
+        {
+            ++div1;
+        }
+
+        assert((div1 >= kDivider_Min) && (div1 <= kDivider_Max));
+
+        uint32_t div2 = div1;
+        uint32_t div4 = div1;
+
+        // 7. Keep bus freq below max.
+        //
+        // The bus clock is divided by OUTDIV2:
+        //      MCGOUTCLK -> OUTDIV2 -> bus_clk
+        freq = McgOutClk;
+        while ((freq / div2) > kMaxBusClock)
+        {
+            // Increase bus clock divider.
+            ++div2;
+        }
+        assert((div2 >= kDivider_Min) && (div2 <= kDivider_Max));
+
+        // 8. Keep flash freq below max.
+        //
+        // The flash clock is diveded by OUTDIV4:
+        //      MCGOUTCLK -> OUTDIV4 ->flash_clk
+        freq = McgOutClk;
+        while ((freq / div4) > kMaxFlashClock)
+        {
+            // Increase bus/flash clock divider.
+            ++div4;
+        }
+        assert((div4 >= kDivider_Min) && (div4 <= kDivider_Max));
+
+        if ((div1 == 1) && ((div2 > 8) || (div4 > 8)))
+        {
+            return;
+        }
+
+        // 9. Now set the dividers
+        SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(div1 - 1) | SIM_CLKDIV1_OUTDIV2(div2 - 1) |
+                       SIM_CLKDIV1_OUTDIV4(div4 - 1); // Update system prescalers
+
+        // 10. Update SystemCoreClock global.
+        SystemCoreClock = McgOutClk / div1;
+    }
+    else if (option == kClockOption_ExitBootloader)
+    {
+        SIM->CLKDIV1 = s_defaultClockDivider;
+    }
+#endif // BL_TARGET_FLASH
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

targets/MKV58F22/src/hardware_init_KV58F22.c

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bootloader/bl_context.h"
+#include "bootloader_common.h"
+#include "fsl_device_registers.h"
+#include "uart/fsl_uart.h"
+#include "utilities/kinetis_family.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+#define BOOT_PIN_NUMBER 4
+#define BOOT_PIN_PORT PORTE
+#define BOOT_PIN_GPIO GPIOE
+#define BOOT_PIN_ALT_MODE 1
+
+#define BOOT_PIN_DEBOUNCE_READ_COUNT 500
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+void init_hardware(void)
+{
+    // Enable all the ports
+    SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
+                   SIM_SCGC5_PORTE_MASK);
+}
+
+void deinit_hardware(void)
+{
+    SIM->SCGC5 &= (uint32_t) ~(SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |
+                               SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
+}
+
+uint32_t get_bus_clock(void)
+{
+    uint32_t coreClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1;
+    uint32_t busClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1;
+    return (SystemCoreClock * coreClockDivider) / busClockDivider;
+}
+
+uint32_t get_fast_peripheral_clock(void)
+{
+    uint32_t coreClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1;
+    uint32_t fastClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1;
+    return (SystemCoreClock * coreClockDivider / fastClockDivider);
+}
+
+uint32_t get_uart_clock(uint32_t instance)
+{
+    switch (instance)
+    {
+        case 0:
+            // UART0 and UART1 always use the system clock
+            return SystemCoreClock;
+        default:
+            return 0;
+    }
+}
+
+bool is_boot_pin_asserted(void)
+{
+#ifdef BL_TARGET_FLASH
+    // Initialize boot pin for GPIO
+    BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] = PORT_PCR_MUX(BOOT_PIN_ALT_MODE);
+    // Set boot pin as an input
+    BOOT_PIN_GPIO->PDDR &= (uint32_t) ~(1 << BOOT_PIN_NUMBER);
+    // Set boot pin pullup enabled, pullup select, filter enable
+    BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_PFE_MASK);
+
+    uint32_t readCount = 0;
+
+    // Sample the pin a number of times
+    for (uint32_t i = 0; i < BOOT_PIN_DEBOUNCE_READ_COUNT; i++)
+    {
+        readCount += ((BOOT_PIN_GPIO->PDIR) >> BOOT_PIN_NUMBER) & 1;
+    }
+
+    // boot pin is pulled high so we are measuring lows, make sure most of our measurements
+    // registered as low
+    return (readCount < (BOOT_PIN_DEBOUNCE_READ_COUNT / 2));
+#else
+    // Boot pin for Flash only target
+    return false;
+#endif
+}
+
+void debug_init(void)
+{
+}
+
+#if __ICCARM__
+
+size_t __write(int handle, const unsigned char *buf, size_t size)
+{
+    return size;
+}
+
+#endif // __ICCARM__
+
+void update_available_peripherals()
+{
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

targets/MKV58F22/src/memory_map_KV58F22.c

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bootloader/bl_context.h"
+#include "memory/memory.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Memory map for KV58F22
+//!
+//! This map is not const because it is updated at runtime with the actual sizes of
+//! flash and RAM for the chip we're running on.
+memory_map_entry_t g_memoryMap[] = {
+    { 0x10000000, 0x100fffff, kMemoryIsExecutable, &g_flashMemoryInterface },   // Flash array (1MB)
+    { 0x00000000, 0x0000ffff, kMemoryIsExecutable, &g_normalMemoryInterface },  // ITCM SRAM (64KB)
+    { 0x20000000, 0x2001ffff, kMemoryIsExecutable, &g_normalDTCMInterface },    // DTCM SRAM (128KB)
+    { 0x2f000000, 0x2f00ffff, kMemoryIsExecutable, &g_normalOCRAMInterface },   // OCRAM (64KB)
+    { 0x40000000, 0x4007ffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS peripherals
+    { 0x400ff000, 0x400fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // GPIO
+    { 0xe0000000, 0xe00fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // M7 private peripherals
+    { 0 }                                                                       // Terminator
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

targets/MKV58F22/src/peripherals_KV58F22.c

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bootloader/bl_context.h"
+#include "bootloader/bl_peripheral_interface.h"
+#include "packet/serial_packet.h"
+
+extern void uart_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
+extern void i2c_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
+extern void spi_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
+extern void can_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+#if !BL_CONFIG_SCUART && !BL_CONFIG_I2C && !BL_CONFIG_DSPI && !BL_CONFIG_CAN
+#error At least one peripheral must be enabled!
+#endif
+
+//! @brief Peripheral array for K22F5256.
+const peripheral_descriptor_t g_peripherals[] = {
+#if BL_CONFIG_SCUART
+    // UART0
+    {.typeMask = kPeripheralType_UART,
+     .instance = 0,
+     .pinmuxConfig = uart_pinmux_config,
+     .controlInterface = &g_scuartControlInterface,
+     .byteInterface = &g_scuartByteInterface,
+     .packetInterface = &g_framingPacketInterface },
+#endif // BL_CONFIG_SCUART
+#if BL_CONFIG_I2C
+    // I2C0
+    {.typeMask = kPeripheralType_I2CSlave,
+     .instance = 0,
+     .pinmuxConfig = i2c_pinmux_config,
+     .controlInterface = &g_i2cControlInterface,
+     .byteInterface = &g_i2cByteInterface,
+     .packetInterface = &g_framingPacketInterface },
+#endif // BL_CONFIG_I2C
+#if BL_CONFIG_DSPI
+    // SPI0
+    {.typeMask = kPeripheralType_SPISlave,
+     .instance = 0,
+     .pinmuxConfig = spi_pinmux_config,
+     .controlInterface = &g_dspiControlInterface,
+     .byteInterface = &g_dspiByteInterface,
+     .packetInterface = &g_framingPacketInterface },
+#endif // BL_CONFIG_DSPI
+#if BL_CONFIG_CAN
+    // CAN0
+    {.typeMask = kPeripheralType_CAN,
+     .instance = 0,
+     .pinmuxConfig = can_pinmux_config,
+     .controlInterface = &g_flexcanControlInterface,
+     .byteInterface = &g_flexcanByteInterface,
+     .packetInterface = &g_framingPacketInterface },
+#endif    // BL_CONFIG_CAN
+    { 0 } // Terminator
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

targets/MKV58F22/src/peripherals_pinmux.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+#if !defined(TOWER) && !defined(FREEDOM)
+#define TOWER 1
+#endif
+
+//! peripheral enable configurations
+#define BL_ENABLE_PINMUX_UART0 (BL_CONFIG_SCUART)
+#define BL_ENABLE_PINMUX_SPI0 (BL_CONFIG_DSPI)
+#define BL_ENABLE_PINMUX_I2C0 (BL_CONFIG_I2C)
+#define BL_ENABLE_PINMUX_CAN0 (BL_CONFIG_CAN)
+
+#if defined(TOWER)
+//! UART pinmux configurations - For TWR board bootloader
+#define UART0_RX_PORT_BASE PORTB
+#define UART0_RX_GPIO_BASE GPIOB
+#define UART0_RX_GPIO_PIN_NUM 0                // PIN 0 in the PTB group
+#define UART0_RX_FUNC_ALT_MODE kPORT_MuxAlt7   // ALT mode for UART0 RX
+#define UART0_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO
+#define UART0_RX_GPIO_IRQn PORTB_IRQn
+#define UART0_RX_GPIO_IRQHandler PORTB_IRQHandler
+#define UART0_TX_PORT_BASE PORTB
+#define UART0_TX_GPIO_PIN_NUM 1              // PIN 1 in the PTB group
+#define UART0_TX_FUNC_ALT_MODE kPORT_MuxAlt7 // ALT mode for UART0 TX
+#else
+//! UART pinmux configurations - For flashloader
+#define UART0_RX_PORT_BASE PORTD
+#define UART0_RX_GPIO_BASE GPIOD
+#define UART0_RX_GPIO_PIN_NUM 6                // PIN 6 in the PTD group
+#define UART0_RX_FUNC_ALT_MODE kPORT_MuxAlt3   // ALT mode for UART0 RX
+#define UART0_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO
+#define UART0_RX_GPIO_IRQn PORTD_IRQn
+#define UART0_RX_GPIO_IRQHandler PORTD_IRQHandler
+#define UART0_TX_PORT_BASE PORTD
+#define UART0_TX_GPIO_PIN_NUM 7              // PIN 7 in the PTD group
+#define UART0_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART0 TX
+#endif                                       // defined TOWER
+
+#if defined(TOWER)
+//! I2C pinmux configurations - For TWR board bootloader
+#define I2C0_SCL_PORT_BASE PORTB
+#define I2C0_SCL_GPIO_PIN_NUM 2              // PIN 2 in the PTB group
+#define I2C0_SCL_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C0 SCL
+#define I2C0_SDA_PORT_BASE PORTB
+#define I2C0_SDA_GPIO_PIN_NUM 3              // PIN 3 in the PTB group
+#define I2C0_SDA_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C0 SDA
+#else
+//! I2C pinmux configurations - For flashloader
+#define I2C0_SCL_PORT_BASE PORTB
+#define I2C0_SCL_GPIO_PIN_NUM 0              // PIN 0 in the PTB group
+#define I2C0_SCL_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C0 SCL
+#define I2C0_SDA_PORT_BASE PORTB
+#define I2C0_SDA_GPIO_PIN_NUM 1              // PIN 1 in the PTB group
+#define I2C0_SDA_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C0 SDA
+#endif
+
+//! SPI pinmux configurations
+#define SPI0_PCS_PORT_BASE PORTE
+#define SPI0_PCS_GPIO_PIN_NUM 16             // PIN 16 in the PTE group
+#define SPI0_PCS_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI0 PCS
+#define SPI0_SCK_PORT_BASE PORTE
+#define SPI0_SCK_GPIO_PIN_NUM 17             // PIN 17 in the PTE group
+#define SPI0_SCK_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI0 SCK
+#define SPI0_SOUT_PORT_BASE PORTE
+#define SPI0_SOUT_GPIO_PIN_NUM 18             // PIN 18 in the PTE group
+#define SPI0_SOUT_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI0 SOUT
+#define SPI0_SIN_PORT_BASE PORTE
+#define SPI0_SIN_GPIO_PIN_NUM 19             // PIN 19 in the PTE group
+#define SPI0_SIN_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI0 SIN
+
+//! CAN pinmux configurations
+#define CAN0_RX_PORT_BASE PORTB
+#define CAN0_RX_GPIO_PIN_NUM 17             // PIN 17 in the PTB group
+#define CAN0_RX_FUNC_ALT_MODE kPORT_MuxAlt5 // ALT mode for CAN0 RX
+#define CAN0_TX_PORT_BASE PORTB
+#define CAN0_TX_GPIO_PIN_NUM 16             // PIN 16 in the PTB group
+#define CAN0_TX_FUNC_ALT_MODE kPORT_MuxAlt5 // ALT mode for CAN0 TX
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

targets/MKV58F22/src/startup/system_MKV58F22.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include "system_MKV58F22.h"
+#include "fsl_device_registers.h"
+#include "target_config.h"
+
+#ifndef DISABLE_WDOG
+#define DISABLE_WDOG 1
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = kDefaultClock;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+/* Watchdog disable */
+#if (DISABLE_WDOG)
+    /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+    /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+                                                   /* WDOG->STCTRLH:
+                                                    * ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
+                                                    */
+    WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
+                    WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
+#endif /* (DISABLE_WDOG) */
+}

targets/MKV58F22/src/startup/system_MKV58F22.h

@@ -0,0 +1,279 @@
+/*
+** ###################################################################
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KV5xP64M75RM Rev.0, November 2014
+**     Version:             rev. 0.1, 2015-02-24
+**     Build:               b150630
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 0.1 (2015-02-24)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKV58F22
+ * @version 0.1
+ * @date 2015-02-24
+ * @brief Device specific configuration file for MKV58F22 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MKV58F22_H_
+#define _SYSTEM_MKV58F22_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef DISABLE_WDOG
+#define DISABLE_WDOG 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+   0 ... Default part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock      = 20.97152MHz
+         Fast bus clock  = 20.97152MHz
+         Bus/Flash clock = 10.48576
+   1 ... Maximum achievable clock frequency configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator reference clock
+         Core clock      = 200MHz
+         Fast bus clock  = 100MHz
+         Bus/Flash clock = 25MHz
+   2 ... Chip internally clocked, ready for Very Low Power Run mode
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock      = 4MHz
+         Fast bus clock  = 4MHz
+         Bus/Flash clock = 0.8MHz
+   3 ... Chip externally clocked
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: System oscillator reference clock
+         Core clock      = 3.84615MHz
+         Fast bus clock  = 3.84615MHz
+         Bus/Flash clock = 3.84615MHz
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ 50000000UL    /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ 32768UL   /* Value of the slow internal oscillator clock frequency in Hz  */
+#define CPU_INT_FAST_CLK_HZ 4000000UL /* Value of the fast internal oscillator clock frequency in Hz  */
+
+/* Low power mode enable */
+
+/* SMC_PMPROT: AHSRUN=1,?=0,AVLP=1,?=0,?=0,?=0,AVLLS=1,?=0 */
+#define SYSTEM_SMC_PMPROT_VALUE                     \
+    SMC_PMPROT_AHSRUN_MASK | SMC_PMPROT_AVLP_MASK | \
+        SMC_PMPROT_AVLLS_MASK /* Mask of allowed low power modes used to initialize power modes protection register */
+
+/* Internal reference clock trim */
+
+/* #undef SLOW_TRIM_ADDRESS */      /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */      /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+/* System clock */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+#define DEFAULT_SYSTEM_CLOCK 20971520UL /* Default System clock value */
+#define MCG_MODE MCG_MODE_FEI           /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
+/* OSC0_OSC_DIV: ERPS=0 */
+#define SYSTEM_OSC0_OSC_DIV_VALUE 0x00U /* OSC0_OSC_DIV */
+/* SIM_SOPT1: OSC32KSEL=3 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000UL /* SIM_CLKDIV1 */
+/* SMC_PMCTRL: RUNM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00 /* SMC_PMCTRL */
+#elif(CLOCK_SETUP == 1)
+#define DEFAULT_SYSTEM_CLOCK 200000000UL /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE      /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x3AU  /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x20U  /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U  /* MCG_C4 */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=3 */
+#define SYSTEM_MCG_C5_VALUE 0x03U  /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x40U  /* MCG_C6 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U  /* MCG_SC */
+/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
+/* OSC0_OSC_DIV: ERPS=0 */
+#define SYSTEM_OSC0_OSC_DIV_VALUE 0x00U     /* OSC0_OSC_DIV */
+/* SIM_SOPT1: OSC32KSEL=3 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=7 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01370000UL /* SIM_CLKDIV1 */
+/* SMC_PMCTRL: RUNM=3 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60          /* SMC_PMCTRL */
+#elif(CLOCK_SETUP == 2)
+#define DEFAULT_SYSTEM_CLOCK 4000000UL /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPI     /* Clock generator mode */
+/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x46U  /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x23U  /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U  /* MCG_C4 */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U  /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U  /* MCG_C6 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U  /* MCG_SC */
+/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
+/* OSC0_OSC_DIV: ERPS=0 */
+#define SYSTEM_OSC0_OSC_DIV_VALUE 0x00U     /* OSC0_OSC_DIV */
+/* SIM_SOPT1: OSC32KSEL=3 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=4,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00440000UL /* SIM_CLKDIV1 */
+/* SMC_PMCTRL: RUNM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00          /* SMC_PMCTRL */
+#elif(CLOCK_SETUP == 3)
+#define DEFAULT_SYSTEM_CLOCK 3846154UL /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPE     /* Clock generator mode */
+/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0xAAU  /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x23U  /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U  /* MCG_C4 */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U  /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U  /* MCG_C6 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U  /* MCG_SC */
+/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
+/* OSC0_OSC_DIV: ERPS=0 */
+#define SYSTEM_OSC0_OSC_DIV_VALUE 0x00U /* OSC0_OSC_DIV */
+/* SIM_SOPT1: OSC32KSEL=3 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */
+/* SIM_CLKDIV1: OUTDIV1=0x0C,OUTDIV2=0x0C,OUTDIV3=0x0C,OUTDIV4=0x0C */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0xCCCC0000UL /* SIM_CLKDIV1 */
+/* SMC_PMCTRL: RUNM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00          /* SMC_PMCTRL */
+#endif
+#else
+#define DEFAULT_SYSTEM_CLOCK 20971520UL /* Default System clock value */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(_SYSTEM_MKV58F22_H_) */

targets/MKV58F22/src/target_config.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__TARGET_CONFIG_H__)
+#define __TARGET_CONFIG_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Constants for clock frequencies.
+enum _target_clocks
+{
+    kDefaultClock = 20971520u,
+    kHIRC = 48000000u,
+    kMinCoreClockWithUsbSupport = 20000000u,
+    kMaxCoreClock = 120000000u,
+    kMaxBusClock = 60000000u,
+    kMaxFlashClock = 25000000u,
+
+    kDivider_Min = 1,
+    kDivider_Max = 16,
+};
+
+//! @brief Constants for sram partition
+enum _sram_partition
+{
+    kSram_LowerPart = 1,
+    kSram_UpperPart = 1,
+};
+
+//! @brief Version constants for the target.
+enum _target_version_constants
+{
+    kTarget_Version_Name = 'T',
+    kTarget_Version_Major = 1,
+    kTarget_Version_Minor = 0,
+    kTarget_Version_Bugfix = 0
+};
+
+#endif // __TARGET_CONFIG_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////