Add KBOOT.
This commit is contained in:
László Monda
795
targets/MKL82Z7/src/startup/arm/startup_MKL82Z7.s
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795
targets/MKL82Z7/src/startup/arm/startup_MKL82Z7.s
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File diff suppressed because it is too large
Load Diff
415
targets/MKL82Z7/src/startup/gcc/startup_MKL82Z7.S
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415
targets/MKL82Z7/src/startup/gcc/startup_MKL82Z7.S
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@@ -0,0 +1,415 @@
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/* ---------------------------------------------------------------------------------------*/
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/* @file: startup_MKL82Z7.s */
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/* @purpose: CMSIS Cortex-M0P Core Device Startup File */
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/* MKL82Z7 */
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/* @version: 2.0 */
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/* @date: 2015-9-24 */
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/* @build: b151106 */
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/* ---------------------------------------------------------------------------------------*/
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/* */
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/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without modification, */
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/* are permitted provided that the following conditions are met: */
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/* */
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/* o Redistributions of source code must retain the above copyright notice, this list */
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/* of conditions and the following disclaimer. */
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/* */
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/* o Redistributions in binary form must reproduce the above copyright notice, this */
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/* list of conditions and the following disclaimer in the documentation and/or */
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/* other materials provided with the distribution. */
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/* */
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/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
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/* contributors may be used to endorse or promote products derived from this */
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/* software without specific prior written permission. */
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/* */
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/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
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/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
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/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
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/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
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/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
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/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
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/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
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/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
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/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/*****************************************************************************/
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/* Version: GCC for ARM Embedded Processors */
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/*****************************************************************************/
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.syntax unified
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.arch armv6-m
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.section .isr_vector, "a"
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler*/
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.long HardFault_Handler /* Hard Fault Handler*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long SVC_Handler /* SVCall Handler*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long PendSV_Handler /* PendSV Handler*/
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.long SysTick_Handler /* SysTick Handler*/
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/* External Interrupts*/
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.long DMA0_DMA4_IRQHandler /* DMA channel 0, 4 transfer complete*/
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.long DMA1_DMA5_IRQHandler /* DMA channel 1, 5 transfer complete*/
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.long DMA2_DMA6_IRQHandler /* DMA channel 2, 6 transfer complete*/
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.long DMA3_DMA7_IRQHandler /* DMA channel 3, 7 transfer complete*/
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.long DMA_Error_IRQHandler /* DMA channel 0 - 7 error*/
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.long FLEXIO0_IRQHandler /* Flexible IO*/
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.long TPM0_IRQHandler /* Timer/PWM module 0*/
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.long TPM1_IRQHandler /* Timer/PWM module 1*/
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.long TPM2_IRQHandler /* Timer/PWM module 2*/
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.long PIT0_IRQHandler /* Periodic Interrupt Timer 0*/
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.long SPI0_IRQHandler /* Serial Peripheral Interface 0*/
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.long EMVSIM0_IRQHandler /* EMVSIM0 common interrupt*/
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.long LPUART0_IRQHandler /* LPUART0 status and error*/
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.long LPUART1_IRQHandler /* LPUART1 status and error*/
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.long I2C0_IRQHandler /* Inter-Integrated Circuit 0*/
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.long QSPI0_IRQHandler /* QuadSPI0 interrupt*/
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.long Reserved32_IRQHandler /* DryIce tamper detect*/
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.long PORTA_IRQHandler /* Pin detect Port A*/
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.long PORTB_IRQHandler /* Pin detect Port B*/
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.long PORTC_IRQHandler /* Pin detect Port C*/
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.long PORTD_IRQHandler /* Pin detect Port D*/
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.long PORTE_IRQHandler /* Pin detect Port E*/
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.long LLWU_IRQHandler /* Low Leakage Wakeup*/
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.long LTC0_IRQHandler /* Low power trusted cryptographic*/
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.long USB0_IRQHandler /* USB OTG interrupt*/
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.long ADC0_IRQHandler /* Analog-to-Digital Converter 0*/
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.long LPTMR0_IRQHandler /* Low-Power Timer 0*/
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.long RTC_Seconds_IRQHandler /* RTC seconds*/
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.long INTMUX0_0_IRQHandler /* Selectable peripheral interrupt INTMUX0-0*/
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.long INTMUX0_1_IRQHandler /* Selectable peripheral interrupt INTMUX0-1*/
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.long INTMUX0_2_IRQHandler /* Selectable peripheral interrupt INTMUX0-2*/
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.long INTMUX0_3_IRQHandler /* Selectable peripheral interrupt INTMUX0-3*/
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.long LPTMR1_IRQHandler /* Low-Power Timer 1 (INTMUX source IRQ0)*/
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.long Reserved49_IRQHandler /* Reserved interrupt (INTMUX source IRQ1)*/
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.long Reserved50_IRQHandler /* Reserved interrupt (INTMUX source IRQ2)*/
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.long Reserved51_IRQHandler /* Reserved interrupt (INTMUX source IRQ3)*/
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.long SPI1_IRQHandler /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
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.long LPUART2_IRQHandler /* LPUART2 status and error (INTMUX source IRQ5)*/
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.long EMVSIM1_IRQHandler /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
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.long I2C1_IRQHandler /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
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.long TSI0_IRQHandler /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
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.long PMC_IRQHandler /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
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.long FTFA_IRQHandler /* FTFA command complete/read collision (INTMUX source IRQ10)*/
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.long MCG_IRQHandler /* Multipurpose clock generator (INTMUX source IRQ11)*/
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.long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM (INTMUX source IRQ12)*/
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.long DAC0_IRQHandler /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
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.long TRNG0_IRQHandler /* True randon number generator (INTMUX source IRQ14)*/
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.long Reserved63_IRQHandler /* Reserved interrupt (INTMUX source IRQ15)*/
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.long CMP0_IRQHandler /* Comparator 0 (INTMUX source IRQ16)*/
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.long Reserved65_IRQHandler /* Reserved interrupt (INTMUX source IRQ17)*/
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.long RTC_Alarm_IRQHandler /* Real time clock (INTMUX source IRQ18)*/
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.long Reserved67_IRQHandler /* Reserved interrupt (INTMUX source IRQ19)*/
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.long Reserved68_IRQHandler /* Reserved interrupt (INTMUX source IRQ20)*/
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.long Reserved69_IRQHandler /* Reserved interrupt (INTMUX source IRQ21)*/
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.long Reserved70_IRQHandler /* Reserved interrupt (INTMUX source IRQ22)*/
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.long Reserved71_IRQHandler /* Reserved interrupt (INTMUX source IRQ23)*/
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.long DMA4_IRQHandler /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
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.long DMA5_IRQHandler /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
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.long DMA6_IRQHandler /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
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.long DMA7_IRQHandler /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
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.long Reserved76_IRQHandler /* Reserved interrupt (INTMUX source IRQ28)*/
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.long Reserved77_IRQHandler /* Reserved interrupt (INTMUX source IRQ29)*/
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.long Reserved78_IRQHandler /* Reserved interrupt (INTMUX source IRQ30)*/
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.long Reserved79_IRQHandler /* Reserved interrupt (INTMUX source IRQ31)*/
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.size __isr_vector, . - __isr_vector
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/* Bootloader Config Area */
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.section .BootloaderConfig, "a"
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#ifdef BL_HAS_BOOTLOADER_CONFIG
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//__bootloaderConfigurationArea ; 0x3c0
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.long 0x6766636b // [00:03] tag - Tag value used to validate the bootloader configuration data. Must be set to 'kcfg'
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.long 0xFFFFFFFF // [04:07] crcStartAddress
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.long 0xFFFFFFFF // [08:0b] crcByteCount
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.long 0xFFFFFFFF // [0c:0f] crcExpectedValue
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.byte 0xFF // [10:10] enabledPeripherals
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.byte 0xFF // [11:11] i2cSlaveAddress
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.short 5000 // [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code
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.short 0xFFFF // [14:15] usbVid
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.short 0xFFFF // [16:17] usbPid
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.long 0xFFFFFFFF // [18:1b] usbStringsPointer
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.byte 0xFF // [1c:1c] clockFlags - High Speed and other clock options
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.byte 0xFF // [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1
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.short 0xFFFF // [1e:1f] reserved
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// Fill to align with flash configuration field.
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF // Reserved for user TRIM value
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#else
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//Fill to align with flash configuration field.
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF // Reserved for user TRIM value
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#endif // BL_HAS_BOOTLOADER_CONFIG
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/* Flash Configuration */
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.section .FlashConfig, "a"
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFF3DFE
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.text
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.thumb
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/* Reset Handler */
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.thumb_func
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.align 2
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.globl Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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cpsid i /* Mask interrupts */
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.equ VTOR, 0xE000ED08
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ldr r0, =VTOR
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ldr r1, =__isr_vector
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str r1, [r0]
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#ifndef __NO_SYSTEM_INIT
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ldr r0,=SystemInit
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blx r0
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#endif
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ldr r0,=init_data_bss
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blx r0
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cpsie i /* Unmask interrupts */
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#ifndef __START
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#define __START _start
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#endif
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#ifndef __ATOLLIC__
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ldr r0,=__START
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blx r0
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#else
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ldr r0,=__libc_init_array
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blx r0
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ldr r0,=main
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bx r0
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#endif
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak DefaultISR
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.type DefaultISR, %function
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DefaultISR:
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ldr r0, =DefaultISR
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bx r0
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.size DefaultISR, . - DefaultISR
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.align 1
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.thumb_func
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.weak DMA0_DMA4_IRQHandler
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.type DMA0_DMA4_IRQHandler, %function
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DMA0_DMA4_IRQHandler:
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ldr r0,=DMA0_DMA4_DriverIRQHandler
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bx r0
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.size DMA0_DMA4_IRQHandler, . - DMA0_DMA4_IRQHandler
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.align 1
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.thumb_func
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.weak DMA1_DMA5_IRQHandler
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.type DMA1_DMA5_IRQHandler, %function
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DMA1_DMA5_IRQHandler:
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ldr r0,=DMA1_DMA5_DriverIRQHandler
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bx r0
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.size DMA1_DMA5_IRQHandler, . - DMA1_DMA5_IRQHandler
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.align 1
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.thumb_func
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.weak DMA2_DMA6_IRQHandler
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.type DMA2_DMA6_IRQHandler, %function
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DMA2_DMA6_IRQHandler:
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ldr r0,=DMA2_DMA6_DriverIRQHandler
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bx r0
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.size DMA2_DMA6_IRQHandler, . - DMA2_DMA6_IRQHandler
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.align 1
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.thumb_func
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.weak DMA3_DMA7_IRQHandler
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.type DMA3_DMA7_IRQHandler, %function
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DMA3_DMA7_IRQHandler:
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ldr r0,=DMA3_DMA7_DriverIRQHandler
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bx r0
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.size DMA3_DMA7_IRQHandler, . - DMA3_DMA7_IRQHandler
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.align 1
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.thumb_func
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.weak DMA_Error_IRQHandler
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.type DMA_Error_IRQHandler, %function
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DMA_Error_IRQHandler:
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ldr r0,=DMA_Error_DriverIRQHandler
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bx r0
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.size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler
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.align 1
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.thumb_func
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.weak FLEXIO0_IRQHandler
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.type FLEXIO0_IRQHandler, %function
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FLEXIO0_IRQHandler:
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ldr r0,=FLEXIO0_DriverIRQHandler
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bx r0
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.size FLEXIO0_IRQHandler, . - FLEXIO0_IRQHandler
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.align 1
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.thumb_func
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.weak SPI0_IRQHandler
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.type SPI0_IRQHandler, %function
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SPI0_IRQHandler:
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ldr r0,=SPI0_DriverIRQHandler
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bx r0
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.size SPI0_IRQHandler, . - SPI0_IRQHandler
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.align 1
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.thumb_func
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.weak LPUART0_IRQHandler
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.type LPUART0_IRQHandler, %function
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LPUART0_IRQHandler:
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ldr r0,=LPUART0_DriverIRQHandler
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bx r0
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.size LPUART0_IRQHandler, . - LPUART0_IRQHandler
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.align 1
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.thumb_func
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.weak LPUART1_IRQHandler
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.type LPUART1_IRQHandler, %function
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LPUART1_IRQHandler:
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ldr r0,=LPUART1_DriverIRQHandler
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bx r0
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.size LPUART1_IRQHandler, . - LPUART1_IRQHandler
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.align 1
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.thumb_func
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.weak I2C0_IRQHandler
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.type I2C0_IRQHandler, %function
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I2C0_IRQHandler:
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ldr r0,=I2C0_DriverIRQHandler
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bx r0
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.size I2C0_IRQHandler, . - I2C0_IRQHandler
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.align 1
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.thumb_func
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.weak QSPI0_IRQHandler
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.type QSPI0_IRQHandler, %function
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QSPI0_IRQHandler:
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ldr r0,=QSPI0_DriverIRQHandler
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bx r0
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.size QSPI0_IRQHandler, . - QSPI0_IRQHandler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, DefaultISR
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.endm
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/* Exception Handlers */
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
|
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def_irq_handler DMA0_DMA4_DriverIRQHandler
|
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def_irq_handler DMA1_DMA5_DriverIRQHandler
|
||||
def_irq_handler DMA2_DMA6_DriverIRQHandler
|
||||
def_irq_handler DMA3_DMA7_DriverIRQHandler
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||||
def_irq_handler DMA_Error_DriverIRQHandler
|
||||
def_irq_handler FLEXIO0_DriverIRQHandler
|
||||
def_irq_handler TPM0_IRQHandler
|
||||
def_irq_handler TPM1_IRQHandler
|
||||
def_irq_handler TPM2_IRQHandler
|
||||
def_irq_handler PIT0_IRQHandler
|
||||
def_irq_handler SPI0_DriverIRQHandler
|
||||
def_irq_handler EMVSIM0_IRQHandler
|
||||
def_irq_handler LPUART0_DriverIRQHandler
|
||||
def_irq_handler LPUART1_DriverIRQHandler
|
||||
def_irq_handler I2C0_DriverIRQHandler
|
||||
def_irq_handler QSPI0_DriverIRQHandler
|
||||
def_irq_handler Reserved32_IRQHandler
|
||||
def_irq_handler PORTA_IRQHandler
|
||||
def_irq_handler PORTB_IRQHandler
|
||||
def_irq_handler PORTC_IRQHandler
|
||||
def_irq_handler PORTD_IRQHandler
|
||||
def_irq_handler PORTE_IRQHandler
|
||||
def_irq_handler LLWU_IRQHandler
|
||||
def_irq_handler LTC0_IRQHandler
|
||||
def_irq_handler USB0_IRQHandler
|
||||
def_irq_handler ADC0_IRQHandler
|
||||
def_irq_handler LPTMR0_IRQHandler
|
||||
def_irq_handler RTC_Seconds_IRQHandler
|
||||
def_irq_handler INTMUX0_0_IRQHandler
|
||||
def_irq_handler INTMUX0_1_IRQHandler
|
||||
def_irq_handler INTMUX0_2_IRQHandler
|
||||
def_irq_handler INTMUX0_3_IRQHandler
|
||||
def_irq_handler LPTMR1_IRQHandler
|
||||
def_irq_handler Reserved49_IRQHandler
|
||||
def_irq_handler Reserved50_IRQHandler
|
||||
def_irq_handler Reserved51_IRQHandler
|
||||
def_irq_handler SPI1_IRQHandler
|
||||
def_irq_handler LPUART2_IRQHandler
|
||||
def_irq_handler EMVSIM1_IRQHandler
|
||||
def_irq_handler I2C1_IRQHandler
|
||||
def_irq_handler TSI0_IRQHandler
|
||||
def_irq_handler PMC_IRQHandler
|
||||
def_irq_handler FTFA_IRQHandler
|
||||
def_irq_handler MCG_IRQHandler
|
||||
def_irq_handler WDOG_EWM_IRQHandler
|
||||
def_irq_handler DAC0_IRQHandler
|
||||
def_irq_handler TRNG0_IRQHandler
|
||||
def_irq_handler Reserved63_IRQHandler
|
||||
def_irq_handler CMP0_IRQHandler
|
||||
def_irq_handler Reserved65_IRQHandler
|
||||
def_irq_handler RTC_Alarm_IRQHandler
|
||||
def_irq_handler Reserved67_IRQHandler
|
||||
def_irq_handler Reserved68_IRQHandler
|
||||
def_irq_handler Reserved69_IRQHandler
|
||||
def_irq_handler Reserved70_IRQHandler
|
||||
def_irq_handler Reserved71_IRQHandler
|
||||
def_irq_handler DMA4_IRQHandler
|
||||
def_irq_handler DMA5_IRQHandler
|
||||
def_irq_handler DMA6_IRQHandler
|
||||
def_irq_handler DMA7_IRQHandler
|
||||
def_irq_handler Reserved76_IRQHandler
|
||||
def_irq_handler Reserved77_IRQHandler
|
||||
def_irq_handler Reserved78_IRQHandler
|
||||
def_irq_handler Reserved79_IRQHandler
|
||||
|
||||
.end
|
||||
641
targets/MKL82Z7/src/startup/iar/startup_MKL82Z7.s
Normal file
641
targets/MKL82Z7/src/startup/iar/startup_MKL82Z7.s
Normal file
File diff suppressed because it is too large
Load Diff
109
targets/MKL82Z7/src/startup/system_MKL82Z7.c
Normal file
109
targets/MKL82Z7/src/startup/system_MKL82Z7.c
Normal file
@@ -0,0 +1,109 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MKL82Z128VLH7
|
||||
** MKL82Z128VLK7
|
||||
** MKL82Z128VLL7
|
||||
** MKL82Z128VMC7
|
||||
** MKL82Z128VMP7
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: KL82P121M72SF0RM, Rev.1.2 September 2015
|
||||
** Version: rev. 1.5, 2015-09-24
|
||||
** Build: b151023
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2015-04-18)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2015-05-04)
|
||||
** Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
|
||||
** - rev. 1.2 (2015-08-11)
|
||||
** Correct clock configuration.
|
||||
** - rev. 1.3 (2015-08-20)
|
||||
** Align with RM Rev.1.
|
||||
** - rev. 1.4 (2015-08-28)
|
||||
** Update LPUART to add FIFO.
|
||||
** - rev. 1.5 (2015-09-24)
|
||||
** Update to align with RM Rev.1.2.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MKL82Z7
|
||||
* @version 1.5
|
||||
* @date 2015-09-24
|
||||
* @brief Device specific configuration file for MKL82Z7 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "system_MKL82Z7.h"
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if (DISABLE_WDOG)
|
||||
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
|
||||
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
|
||||
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
|
||||
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
|
||||
/* WDOG->STCTRLH:
|
||||
* ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
|
||||
*/
|
||||
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
|
||||
WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
}
|
||||
391
targets/MKL82Z7/src/startup/system_MKL82Z7.h
Normal file
391
targets/MKL82Z7/src/startup/system_MKL82Z7.h
Normal file
@@ -0,0 +1,391 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MKL82Z128VLH7
|
||||
** MKL82Z128VLK7
|
||||
** MKL82Z128VLL7
|
||||
** MKL82Z128VMC7
|
||||
** MKL82Z128VMP7
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: KL82P121M72SF0RM, Rev.1.2 September 2015
|
||||
** Version: rev. 1.5, 2015-09-24
|
||||
** Build: b151023
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2015-04-18)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2015-05-04)
|
||||
** Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
|
||||
** - rev. 1.2 (2015-08-11)
|
||||
** Correct clock configuration.
|
||||
** - rev. 1.3 (2015-08-20)
|
||||
** Align with RM Rev.1.
|
||||
** - rev. 1.4 (2015-08-28)
|
||||
** Update LPUART to add FIFO.
|
||||
** - rev. 1.5 (2015-09-24)
|
||||
** Update to align with RM Rev.1.2.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MKL82Z7
|
||||
* @version 1.5
|
||||
* @date 2015-09-24
|
||||
* @brief Device specific configuration file for MKL82Z7 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MKL82Z7_H_
|
||||
#define _SYSTEM_MKL82Z7_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* MCG mode constants */
|
||||
|
||||
#define MCG_MODE_FEI 0U
|
||||
#define MCG_MODE_FBI 1U
|
||||
#define MCG_MODE_BLPI 2U
|
||||
#define MCG_MODE_FEE 3U
|
||||
#define MCG_MODE_FBE 4U
|
||||
#define MCG_MODE_BLPE 5U
|
||||
#define MCG_MODE_PBE 6U
|
||||
#define MCG_MODE_PEE 7U
|
||||
|
||||
/* Predefined clock setups
|
||||
0 ... Default part configuration
|
||||
Multipurpose Clock Generator (MCG) in FEI mode.
|
||||
Reference clock source for MCG module: Slow internal reference clock
|
||||
Core clock = 20.97152MHz
|
||||
Bus clock = 20.97152MHz
|
||||
1 ... Maximal speed configuration
|
||||
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 96MHz
|
||||
Bus clock = 24MHz
|
||||
2 ... Chip internally clocked, ready for Very Low Power Run mode.
|
||||
Multipurpose Clock Generator (MCG) in BLPI mode.
|
||||
Reference clock source for MCG module: Fast internal reference clock
|
||||
Core clock = 4MHz
|
||||
Bus clock = 4MHz
|
||||
3 ... Chip externally clocked, ready for Very Low Power Run mode.
|
||||
Multipurpose Clock Generator (MCG) in BLPE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 4MHz
|
||||
Bus clock = 4MHz
|
||||
4 ... USB clock setup
|
||||
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 96MHz
|
||||
Bus clock = 24MHz
|
||||
5 ... Maximum achievable clock frequency configuration in RUN mode
|
||||
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 72MHz
|
||||
Bus clock = 24MHz
|
||||
*/
|
||||
|
||||
/* Define clock source values */
|
||||
|
||||
#define CPU_XTAL_CLK_HZ \
|
||||
12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
|
||||
#define CPU_XTAL32k_CLK_HZ \
|
||||
32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
|
||||
*/
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
|
||||
|
||||
/* RTC oscillator setting */
|
||||
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
|
||||
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
|
||||
|
||||
/* Low power mode enable */
|
||||
/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
|
||||
#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
|
||||
|
||||
/* Internal reference clock trim */
|
||||
/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
|
||||
#ifdef CLOCK_SETUP
|
||||
#if (CLOCK_SETUP == 0)
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1,OUTDIV5=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00011000U /* SIM_CLKDIV1 */
|
||||
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
|
||||
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
|
||||
*/
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 1)
|
||||
#define DEFAULT_SYSTEM_CLOCK 96000000U /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
|
||||
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
|
||||
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
|
||||
*/
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 2)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=4,OUTDIV5=0 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03040000U /* SIM_CLKDIV1 */
|
||||
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
|
||||
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
|
||||
*/
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 3)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0x0B */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
|
||||
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
|
||||
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
|
||||
*/
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 4)
|
||||
#define DEFAULT_SYSTEM_CLOCK 96000000U /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
|
||||
/* SIM_CLKDIV2: USBDIV=3,USBFRAC=0 */
|
||||
#define SYSTEM_SIM_CLKDIV2_VALUE 0x03U /* SIM_CLKDIV2 */
|
||||
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
|
||||
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
|
||||
*/
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 5)
|
||||
#define DEFAULT_SYSTEM_CLOCK 72000000U /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=8 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x48U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=2,OUTDIV4=2,OUTDIV5=0 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x02020000U /* SIM_CLKDIV1 */
|
||||
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
|
||||
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
|
||||
*/
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
|
||||
#endif
|
||||
#else
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MKL82Z7_H_ */
|
||||
Reference in New Issue
Block a user