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This commit is contained in:
László Monda
2016-08-10 01:45:15 +02:00
commit e6c1fce5b4
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75
targets/MKL82Z7/src/bl_dspi_irq_config_MKL82Z7.c Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h" // needed for NULL
#include "bootloader_config.h"
#include "target_config.h"
#include "bootloader/bl_irq_common.h"
#include "fsl_device_registers.h"
#include "dspi/fsl_dspi.h"
#include "intmux/fsl_intmux.h"
#include "utilities/fsl_assert.h"
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
static const IRQn_Type dspi_irq_ids[FSL_FEATURE_SOC_DSPI_COUNT] = {
SPI0_IRQn, SPI1_IRQn,
};
////////////////////////////////////////////////////////////////////////////////
// Codes
////////////////////////////////////////////////////////////////////////////////
void DSPI_SetSystemIRQ(uint32_t instance, PeripheralSystemIRQSetting set)
{
switch (instance)
{
// Note: DSPI0 is not supported in KL80 ROM.
case 1:
{
int32_t intmux_offset = (uint32_t)dspi_irq_ids[1] - FSL_FEATURE_INTMUX_IRQ_START_INDEX;
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(INTMUX0_2_IRQn);
INTMUX0->CHANNEL[2].CHn_IER_31_0 |= 1 << (intmux_offset);
}
else
{
NVIC_DisableIRQ(INTMUX0_2_IRQn);
INTMUX0->CHANNEL[2].CHn_IER_31_0 &= ~(1 << (intmux_offset));
}
}
break;
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL82Z7/src/bl_i2c_irq_config_MKL82Z7.c Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "bootloader_common.h"
#include "bootloader_config.h"
#include "target_config.h"
#include "bootloader/bl_irq_common.h"
#include "autobaud/autobaud.h"
#include "packet/serial_packet.h"
#include "fsl_device_registers.h"
#include "i2c/fsl_i2c.h"
#include "intmux/fsl_intmux.h"
#include "utilities/fsl_assert.h"
static const IRQn_Type i2c_irq_ids[FSL_FEATURE_SOC_I2C_COUNT] = {
I2C0_IRQn, I2C1_IRQn,
};
void I2C_SetSystemIRQ(uint32_t instance, PeripheralSystemIRQSetting set)
{
switch (instance)
{
case 1:
{
uint32_t intmux_offset = (uint32_t)i2c_irq_ids[1] - FSL_FEATURE_INTMUX_IRQ_START_INDEX;
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(INTMUX0_1_IRQn);
INTMUX0->CHANNEL[1].CHn_IER_31_0 |= 1 << (intmux_offset);
}
else
{
NVIC_DisableIRQ(INTMUX0_1_IRQn);
INTMUX0->CHANNEL[1].CHn_IER_31_0 &= ~(1 << (intmux_offset));
}
}
break;
// Note: I2C0 is not supported in KL80 ROM.
#if 0
case 0:
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(i2c_irq_ids[instance]);
}
else
{
NVIC_DisableIRQ(i2c_irq_ids[instance]);
}
break;
#endif //
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

81
targets/MKL82Z7/src/bl_lpuart_irq_config_MKL82Z7.c Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "bootloader_common.h"
#include "bootloader_config.h"
#include "target_config.h"
#include "bootloader/bl_irq_common.h"
#include "autobaud/autobaud.h"
#include "packet/serial_packet.h"
#include "fsl_device_registers.h"
#include "intmux/fsl_intmux.h"
#include "lpuart/fsl_lpuart.h"
#include "utilities/fsl_assert.h"
static const IRQn_Type lpuart_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {
LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn,
};
void LPUART_SetSystemIRQ(uint32_t instance, PeripheralSystemIRQSetting set)
{
switch (instance)
{
case 2:
{
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(INTMUX0_0_IRQn);
INTMUX0->CHANNEL[0].CHn_IER_31_0 |= 1 << (lpuart_irq_ids[instance]);
}
else
{
NVIC_DisableIRQ(INTMUX0_0_IRQn);
INTMUX0->CHANNEL[0].CHn_IER_31_0 &= ~(1 << (lpuart_irq_ids[instance]));
}
}
break;
case 0:
case 1:
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(lpuart_irq_ids[instance]);
}
else
{
NVIC_DisableIRQ(lpuart_irq_ids[instance]);
}
break;
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL82Z7/src/bootloader_config.h Normal file
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BOOTLOADER_CONFIG_H__
#define __BOOTLOADER_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//
// Bootloader configuration options
//
//! @name Peripheral configuration macros
//@{
#if !BL_TARGET_RAM
#define BL_FEATURE_ROM_UART_PORT (0)
#define BL_FEATURE_ROM_I2C_PORT (0)
#define BL_FEATURE_ROM_SPI_PORT (0)
#else
// For flashloader, use the same pinmux as ROM
#define BL_FEATURE_ROM_UART_PORT (1)
#define BL_FEATURE_ROM_I2C_PORT (1)
#define BL_FEATURE_ROM_SPI_PORT (1)
#endif
#if !defined(BL_CONFIG_LPUART_0)
#if FREEDOM
#define BL_CONFIG_LPUART_0 (1)
#else
#define BL_CONFIG_LPUART_0 (BL_FEATURE_ROM_UART_PORT)
#endif // FREEDOM
#endif
#if !defined(BL_CONFIG_LPUART_1)
#if TOWER
#define BL_CONFIG_LPUART_1 (1)
#else
#define BL_CONFIG_LPUART_1 (BL_FEATURE_ROM_UART_PORT)
#endif // TOWER
#endif
#if !defined(BL_CONFIG_LPUART_2)
#define BL_CONFIG_LPUART_2 (BL_FEATURE_ROM_UART_PORT)
#endif
#define BL_CONFIG_LPUART (BL_CONFIG_LPUART_0 || BL_CONFIG_LPUART_1 || BL_CONFIG_LPUART_2)
#if !defined(BL_CONFIG_I2C)
#define BL_CONFIG_I2C (1)
#endif
//#define BL_CONFIG_I2C (BL_CONFIG_I2C_1)
#if !defined(BL_CONFIG_DSPI)
#define BL_CONFIG_DSPI (1)
#endif
//#define BL_CONFIG_DSPI (BL_CONFIG_DSPI_1)
#if !defined(BL_CONFIG_USB_HID)
#define BL_CONFIG_USB_HID (1)
#endif
#if !defined(BL_CONFIG_USB_MSC)
#define BL_CONFIG_USB_MSC (1)
#endif
#define BL_I2C_SIZE_OPTIMIZE 1
#define BL_I2C_USED_INSTANCE 1
//@}
#if !defined(BL_TARGET_FLASH) && !defined(BL_TARGET_RAM)
#define BL_TARGET_FLASH (1)
#endif
#if defined(BL_TARGET_RAM)
#define BL_FEATURE_FLASH_SECURITY (0)
#else
#define BL_FEATURE_FLASH_SECURITY (1)
#endif
#define BL_FEATURE_MIN_PROFILE (0)
#define BL_FEATURE_ERASEALL_UNSECURE (0)
#define BL_FEATURE_FAC_ERASE (0)
#define BL_FEATURE_FLASH_VERIFY_DISABLE (0)
#if !defined(BL_TARGET_RAM)
#define BL_FEATURE_CRC_CHECK (1)
#endif
#define BL_FEATURE_UART_AUTOBAUD_IRQ (1)
#define BL_FEATURE_QSPI_MODULE (1)
#define BL_FEATURE_QSPI_ALIAS_AREA (0)
#define BL_FEATURE_QSPI_HYPERFLASH (1) // NOTE: This feature can be disabled if the HyperFLASH support is not required.
#if BL_FEATURE_QSPI_MODULE
#define BL_FEATURE_EXTERNAL_MEMORY_PROPERTY (1)
#endif
#define BL_FEATURE_OTFAD_MODULE (0)
#define BL_FEATURE_ENCRYPTION_LTC (1)
#define BL_FEATURE_ENCRYPTION (BL_FEATURE_ENCRYPTION_LTC)
#define BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS (0)
// Bootloader peripheral detection default timeout in milliseconds
// After coming out of reset the bootloader will spin in a peripheral detection
// loop for this amount of time. A zero value means no time out.
#if DEBUG
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 0
#else
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 5000
#endif // DEBUG
// The bootloader will check this address for the application vector table upon startup.
#if !defined(BL_APP_VECTOR_TABLE_ADDRESS)
#define BL_APP_VECTOR_TABLE_ADDRESS 0xA000
#endif
/* Serial Port Info */
/**************************************************************************
* Note:
*
* Because of the changes to the UART modules, we can no longer define
* the TERM_PORT as a base pointer. The uart functions have been modified
* accommodate this change. Now, TERM_PORT_NUM must be defined as the
* number of the UART port desired to use
*
* TERM_PORT_NUM = 0 -- This allows you to use UART0; default pins are
* PTA14 and PTA15
*
* TERM_PORT_NUM = 1 -- This allows you to use UART1; default pins are
* PTC3 and PTC4
*
* TERM_PORT_NUM = 2 -- This allows you to use UART2; default pins are
* PTD2 and PTD3
*
*************************************************************************/
#define TERM_PORT_NUM 0
#define TERMINAL_BAUD 19200
#undef HW_FLOW_CONTROL
#endif // __BOOTLOADER_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL82Z7/src/clock_config_MKL82Z7.c Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h"
#include "bootloader/bl_context.h"
#include "property/property.h"
#include "fsl_device_registers.h"
#include "qspi/qspi.h"
#include "utilities/fsl_assert.h"
#include "target_config.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
// Clock mode types
typedef enum _target_clock_mode
{
kClockMode_FEI = 0,
kClockMode_FEE = 1,
kClockMode_Default = kClockMode_FEI,
} target_clock_mode_t;
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
// This function implements clock mode switch between FEI and PEE mode used in this bootloader
void clock_mode_switch(const target_clock_mode_t currentMode,
const target_clock_mode_t expectedMode,
bool isQspiConfigured);
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
// See bootloader_common for documentation on this function.
void configure_clocks(bootloader_clock_option_t option)
{
#if (BL_TARGET_FLASH)
static target_clock_mode_t s_currentClockMode = kClockMode_FEI;
static uint32_t s_defaultClockDivider;
// Check if qspi module is configured.
bool isQuadSpiConfigured = is_quadspi_configured();
if (option == kClockOption_EnterBootloader)
{
s_defaultClockDivider = SIM->CLKDIV1;
// 1. Read clock flags and divider from bootloader config in property store
bootloader_configuration_data_t *config = &g_bootloaderContext.propertyInterface->store->configurationData;
uint8_t options = config->clockFlags;
// Check if the USB HID peripheral is enabled.
bool isUsbEnabled = config->enabledPeripherals & kPeripheralType_USB_HID;
// 2. Update SystemCoreClock (DEFAULT_SYSTEM_CLOCK is default value of MCGOUTCLK when OUTDIV1 is equal to 0)
// In this case, rom should consider the situation that FOPT[LPBOOT] is eqaul to 0
uint32_t coreClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1;
uint32_t mcgOutClock = isQuadSpiConfigured ? kFLL_72MHz : kFLL_48MHz;
// 3. If any of following conditions are met, do nothing (use reset clock config)
// (1) NOT High Speed is NOT enabled
// (2) usb peripheral is NOT enabled
// (3) qspi doesn't need to run at high frequency
if ((options & kClockFlag_HighSpeed) && (!isUsbEnabled) && (!isQuadSpiConfigured))
{
// High speed flag is set (meaning disabled), so just use default clocks.
SystemCoreClock = kDefaultClock / coreClockDivider;
return;
}
SystemCoreClock = mcgOutClock / coreClockDivider;
// 4. Set OUTDIV1 based on divider in config. OUTDIV4 starts out at /1.
// The divider values are masked by the maximum bits per divider.
uint32_t div1 = ((~config->clockDivider) & (SIM_CLKDIV1_OUTDIV1_MASK >> SIM_CLKDIV1_OUTDIV1_SHIFT)) + 1;
uint32_t div2 = div1;
uint32_t div4 = div1;
// Core = 72MHz, bus = 24MHz, flash = 24MHz
if (isQuadSpiConfigured)
{
div1 = 1;
div2 = 3;
div4 = 3;
}
// Core = 48MHz, bus = 24MHz, flash = 24MHz
else if (isUsbEnabled)
{
div1 = 1;
div2 = 2;
div4 = 2;
}
else if (mcgOutClock / div1 == kFLL_48MHz)
{
div2 = 2;
div4 = 2;
}
// 5. Now set the dividers
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(div1 - 1) | SIM_CLKDIV1_OUTDIV2(div2 - 1) |
SIM_CLKDIV1_OUTDIV4(div4 - 1); /* Update system prescalers */
// 6. Update SystemCoreClock global.
SystemCoreClock = mcgOutClock / div1;
// Switch to FEE mode.
clock_mode_switch(s_currentClockMode, kClockMode_FEE, isQuadSpiConfigured);
s_currentClockMode = kClockMode_FEE;
}
else if (option == kClockOption_ExitBootloader)
{
if (!isQuadSpiConfigured)
{
clock_mode_switch(s_currentClockMode, kClockMode_FEI, isQuadSpiConfigured);
SIM->CLKDIV1 = s_defaultClockDivider;
}
}
#endif // BL_TARGET_FLASH
}
void clock_mode_switch(const target_clock_mode_t currentMode,
const target_clock_mode_t expectedMode,
bool isQspiConfigured)
{
// Note: here only implements clock switch between FEI and FEE,
// The other modes are not supported.
assert(currentMode == kClockMode_FEE || currentMode == kClockMode_FEI);
assert(expectedMode == kClockMode_FEE || expectedMode == kClockMode_FEI);
if (currentMode == expectedMode)
{
return;
}
if (expectedMode == kClockMode_FEE)
{
uint8_t tmp;
/* Switch to FEE mode */
MCG->C7 = 2; // Select IRC48M as Oscillator.
// Delay ~50us to ensure that MCG_C7[OSCSEL] is correctly switched to IRC48M.
for (volatile uint32_t delayCnt = 0; delayCnt < 1000; delayCnt++)
{
__ASM("nop");
}
MCG->C1 = MCG_C1_FRDIV(6); // FRDIV=6, divide IRC48M with 1280, Switch to external reference clock.
tmp = MCG->C4;
tmp &= (uint8_t)~MCG_C4_DRST_DRS_MASK;
if (!isQspiConfigured)
{
tmp |= MCG_C4_DRST_DRS(1); // Multiply with 1280, MCGOUTCLK is 48Mhz
}
else
{
tmp |= MCG_C4_DRST_DRS(2); // Multiply with 1920, MCGOUTCLK is 72Mhz
}
MCG->C4 = tmp;
// Wait until external reference clock is ready.
while (MCG->S & MCG_S_IREFST_MASK)
{
}
// Wait until FLL clock is stable
for (volatile uint32_t delayCnt = 0; delayCnt < 24000; delayCnt++)
{
__ASM("nop");
}
}
else if (expectedMode == kClockMode_FEI)
{
if (isQspiConfigured)
{
return;
}
MCG->C1 = MCG_C1_FRDIV(6) | MCG_C1_IREFS_MASK; // Switch to internal reference clock.
while (!(MCG->S & MCG_S_IREFST_MASK))
{
} // Wait until internal reference clock is ready.
// Delay ~50us to ensure that MCG_C7[OSCSEL] is correctly restored.
MCG->C7 = 0;
for (volatile uint32_t delayCnt = 0; delayCnt < 1000; delayCnt++)
{
__ASM("nop");
}
// Restore registers to default value out of reset.
MCG->C1 = 0x04;
MCG->C4 &= (uint8_t)~MCG_C4_DRST_DRS_MASK;
// Wait until FLL clock is stable
for (volatile uint32_t delayCnt = 0; delayCnt < 24000; delayCnt++)
{
__ASM("nop");
}
}
}
void quadspi_serial_clock_configure(qspi_serial_clock_freq_t freq)
{
uint32_t mcr_val = QuadSPI0->MCR;
mcr_val &= (uint32_t)~QuadSPI_MCR_SCLKCFG_MASK;
switch (freq)
{
case kQspiSerialClockFreq_Low:
mcr_val |= QuadSPI_MCR_SCLKCFG(0x3); // Divide by 4
break;
case kQspiSerialClockFreq_Mid:
mcr_val |= QuadSPI_MCR_SCLKCFG(0x1); // Divide by 2
break;
case kQspiSerialClockFreq_High:
mcr_val |= QuadSPI_MCR_SCLKCFG(0x0); // Divide by 1
break;
}
QuadSPI0->MCR = mcr_val;
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL82Z7/src/external_memory_property_map_MKL82Z7.c Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "property/property.h"
#include "qspi/qspi.h"
#include "bootloader_common.h"
const external_memory_property_interface_t g_externalMemPropertyInterfaceMap[] = {
{ kExternalMemId_QuadSPI0, quadspi_get_property }, { 0 }, // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL82Z7/src/hardware_init_MKL82Z7.c Normal file
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h"
#include "bootloader/bl_context.h"
#include "fsl_device_registers.h"
#include "qspi/qspi.h"
#include "intmux/fsl_intmux.h"
#include "smc/smc.h"
#include "lpuart/fsl_lpuart.h"
#include "utilities/fsl_assert.h"
#if BL_FEATURE_CRC_CHECK
#include "bootloader/bl_app_crc_check.h"
#endif
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
#define SECONDARY_I2C_ADDR_SELECT_PIN_IDX 1
#define SECONDARY_I2C_ADDR_SELECT_PIN_PORT PORTA
#define SECONDARY_I2C_ADDR_SELECT_PIN_GPIO GPIOA
#define SECONDARY_I2C_ADDR_SELECT_PIN_ALT_MODE 1
#define SECONDARY_I2C_ADDR_SELECT_PIN_DEBOUNCE_READ_COUNT 1000
enum
{
//! @brief Mask for the bit of RCM_MR[BOOTROM] indicating that the BOOTCFG0 pin was asserted.
kBootedViaPinMask = 1
};
#define kIRC_48M 48000000UL
#define BOOT_PIN_DEBOUNCE_READ_COUNT 500
#define PORT_IRQC_INTERRUPT_FALLING_EDGE 0xA
#define PORT_IRQC_INTERRUPT_DISABLE 0
enum _peripheral_clock_source
{
kPeripheralClockSource_CLKOFF = 0,
kPeripheralClockSource_OSCCLK = 1,
kPeripheralClockSource_SCGIRCLK = 2,
kPeripheralClockSource_SCGFIRCLK = 3,
kPeripheralClockSource_SCGPCLK = 6
};
static INTMUX_Type *const s_intmuxBase[] = INTMUX_BASE_PTRS;
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
#if BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS
static void secondary_i2c_slave_address_select_pin_init(void);
static void secondary_i2c_slave_address_select_pin_deinit(void);
#endif // BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
/*
* This function is called if parameters for QSPI io configuration is invalid
*/
static status_t quadspi_iomux_init_error_handle(void)
{
// Restore all quadspi related pin mux to default value out of reset.
for (uint32_t pin = 0; pin < 14; pin++)
{
PORTE->PCR[pin] &= (uint32_t)~PORT_PCR_MUX_MASK;
}
return kStatus_InvalidArgument;
}
/* This function is called for configurating pinmux for qspi module
* This function only supports switching default mode on specified pins
* If the isParallel parameter is used to determine which group of QSPI interface should be configured.
*/
status_t quadspi_iomux_configuration(qspi_config_t *config_base)
{
bool needInitQuadSPI0A = true;
bool needInitQuadSPI0B = false;
bool isBasicConfiguration = false;
// If the config_base pointer is invalid, only QuadSPI0A will be configured.
if (config_base == NULL)
{
needInitQuadSPI0A = true;
needInitQuadSPI0B = false;
isBasicConfiguration = true;
}
else // Determine which Ports need to be configured based on parameters in qspi config block
{
if (config_base->sflash_type > kQspiFlashPad_Octal)
{
return quadspi_iomux_init_error_handle();
}
if (config_base->sflash_A1_size > 0)
{
needInitQuadSPI0A = true;
}
else
{
needInitQuadSPI0A = false;
}
if (config_base->sflash_B1_size > 0)
{
needInitQuadSPI0B = true;
}
else
{
needInitQuadSPI0B = false;
}
}
if (needInitQuadSPI0A)
{
// Configure default GPIOs for basic read
PORTE->PCR[1] = PORT_PCR_MUX(5); // QSPI0A_SCLK is ALT5 for pin PTE1
PORTE->PCR[2] = PORT_PCR_MUX(5); // QSPI0A_DATA0 is ALT5 for pin PTE2
PORTE->PCR[4] = PORT_PCR_MUX(5); // QSPI0A_DATA1 is ALT5 for pin PTE4
PORTE->PCR[5] = PORT_PCR_MUX(5); // QSPI0A_SS0_B is ALT5 for pin PTE5
if (isBasicConfiguration)
{
return kStatus_Success;
}
if (config_base->sflash_A2_size > 0)
{
PORTE->PCR[7] = PORT_PCR_MUX(7); // QSPI0A_SS1_B is ALT7 for pin PTE7
}
if ((config_base->sflash_type == kQspiFlashPad_Quad) || (config_base->sflash_type == kQspiFlashPad_Octal))
{
PORTE->PCR[0] = PORT_PCR_MUX(5); // QSPI0A_DATA3 is ALT5 for pin PTE0
PORTE->PCR[3] = PORT_PCR_MUX(5); // QSPI0A_DATA2 is ALT5 for pin PTE3
}
if (config_base->sflash_type == kQspiFlashPad_Octal)
{
PORTE->PCR[8] = PORT_PCR_MUX(5); // QSPI0B_DQ4 is ALT5 for pin PTE8
PORTE->PCR[10] = PORT_PCR_MUX(5); // QSPI0B_DQ5 is ALT5 for pin PTE10
PORTE->PCR[9] = PORT_PCR_MUX(5); // QSPI0B_DQ6 is ALT5 for pin PTE9
PORTE->PCR[6] = PORT_PCR_MUX(5); // QSPI0B_DQ7 is ALT5 for pin PTE6
// Note: The functionality of PTE for QuadSPI depends on different combinations
// of DIFFCKEN and CK2EN.
// ----------------------------------------
// | DIFFCKEN | CK2EN | FUNCTION | ALT |
// ----------------------------------------
// | 0 | 0 | QSPI0B_CLK | 5 |
// ----------------------------------------
// | 0 | 1 | CK2 | 5 |
// ----------------------------------------
// | 1 | 0 | CK# | 5 |
// ----------------------------------------
// | 1 | 1 | CK2# | 5 |
// ----------------------------------------
if (config_base->differential_clock_pin_enable || config_base->flash_CK2_clock_pin_enable)
{
PORTE->PCR[7] = PORT_PCR_MUX(5);
}
}
if (config_base->dqs_enable)
{
PORTE->PCR[11] = PORT_PCR_MUX(7); // QSPI0A_DQS is ALT7 for pin PTE11
}
}
if (needInitQuadSPI0B)
{
PORTE->PCR[7] = PORT_PCR_MUX(5); // QSPI0B_SCLK is ALT5 for pin PTE7
PORTE->PCR[8] = PORT_PCR_MUX(5); // QSPI0B_DATA0 is ALT5 for pin PTE8
PORTE->PCR[10] = PORT_PCR_MUX(5); // QSPI0B_DATA1 is ALT5 for pin PTE10
PORTE->PCR[11] = PORT_PCR_MUX(5); // QSPI0B_SS0_B is ALT5 for pin PTE11
if (config_base->sflash_type == kQspiFlashPad_Quad)
{
PORTE->PCR[9] = PORT_PCR_MUX(5); // QSPI0B_DATA2 is ALT5 for pin PTE9
PORTE->PCR[6] = PORT_PCR_MUX(5); // QSPI0B_DATA3 is ALT5 for pin PTE6
}
if ((config_base->sflash_B2_size > 0) || (config_base->dqs_enable))
{
return quadspi_iomux_init_error_handle();
}
}
return kStatus_Success;
}
void init_hardware(void)
{
// Disable the MPU otherwise USB cannot access the bus
MPU->CESR &= (uint32_t)~MPU_CESR_VLD_MASK;
// Enable all the ports
SIM->SCGC5 |=
(SIM_SCGC5_PTA_MASK | SIM_SCGC5_PTB_MASK | SIM_SCGC5_PTC_MASK | SIM_SCGC5_PTD_MASK | SIM_SCGC5_PTE_MASK);
// set PLLFLLSEL to select the IRC48Mhz
// set LPUART Clock source to MCGFLLCLK or MCGPLLCLK
SIM->SOPT2 |= (SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_LPUARTSRC(1));
#if BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS
// Initialize Secondary I2C slave address section pin
secondary_i2c_slave_address_select_pin_init();
#endif // BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS
// Enable clock to INTMUX0 and reset all channels
INTMUX_Init((INTMUX_Type *)s_intmuxBase[0]);
}
void deinit_hardware(void)
{
// Restore MPU to default state (enabled)
MPU->CESR |= (uint32_t)MPU_CESR_VLD_MASK;
// Restore configuration for Secondary I2C slave address section pin
#if BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS
secondary_i2c_slave_address_select_pin_deinit();
#endif // BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS
#if BL_ENABLE_CRC_CHECK && BL_FEATURE_CRC_ASSERT
restore_crc_check_failure_pin();
#endif
// Keep enabling PORTE clock since it is needed for QSPI module
if (is_quadspi_configured())
{
SIM->SCGC5 &= (uint32_t) ~(SIM_SCGC5_PTA_MASK | SIM_SCGC5_PTB_MASK | SIM_SCGC5_PTC_MASK | SIM_SCGC5_PTD_MASK);
}
else
{
SIM->SCGC5 = (uint32_t) ~(SIM_SCGC5_PTA_MASK | SIM_SCGC5_PTB_MASK | SIM_SCGC5_PTC_MASK | SIM_SCGC5_PTD_MASK |
SIM_SCGC5_PTE_MASK);
}
// Restore SIM_SOPTx related bits being changed
SIM->SOPT2 &= (uint32_t) ~(SIM_SOPT2_LPUARTSRC_MASK | SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
// Restore Intmux
INTMUX_Deinit((INTMUX_Type *)s_intmuxBase[0]);
}
bool usb_clock_init(void)
{
// Select IRC48M clock
SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
// Enable USB-OTG IP clocking
SIM->SCGC4 |= (SIM_SCGC4_USBOTG_MASK);
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
return true;
}
uint32_t get_bus_clock(void)
{
uint32_t coreClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1;
uint32_t busClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1;
volatile uint32_t mcgOutClock = SystemCoreClock * coreClockDivider;
return (mcgOutClock / busClockDivider);
}
//! @brief Return uart clock frequency according to instance
//! @note: This function is updated according the "K80_256 RM Rev0 draft a", section 6.7.9
uint32_t get_uart_clock(uint32_t instance)
{
volatile uint32_t lpuartClock;
uint32_t pllFllFrac = ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLFRAC_MASK) >> SIM_CLKDIV3_PLLFLLFRAC_SHIFT) + 1;
uint32_t pllFllDiv = ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLDIV_MASK) >> SIM_CLKDIV3_PLLFLLDIV_SHIFT) + 1;
lpuartClock = kIRC_48M * pllFllFrac / pllFllDiv;
return lpuartClock;
}
bool is_boot_pin_asserted(void)
{
// Boot pin for Flash only target
return false;
}
bool is_secondary_i2c_slave_address_enabled(void)
{
static bool isFirstTimeRead = true;
static bool isEnabled = false;
if (!isFirstTimeRead)
{
return isEnabled;
}
// Read several time to do debounce.
uint32_t count = 0;
for (uint32_t i = 0; i < SECONDARY_I2C_ADDR_SELECT_PIN_DEBOUNCE_READ_COUNT; i++)
{
// Note: 0 means this pin is asserted.
// 1 means it is not asserted.
if (SECONDARY_I2C_ADDR_SELECT_PIN_GPIO->PDIR >> SECONDARY_I2C_ADDR_SELECT_PIN_IDX)
{
count++;
}
}
if (count < (SECONDARY_I2C_ADDR_SELECT_PIN_DEBOUNCE_READ_COUNT / 2))
{
isEnabled = true;
}
isFirstTimeRead = false;
return isEnabled;
}
#if BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS
static void secondary_i2c_slave_address_select_pin_init(void)
{
// Set SecondaryI2cSlaveAddress Section pin in GPIO mode
SECONDARY_I2C_ADDR_SELECT_PIN_PORT->PCR[SECONDARY_I2C_ADDR_SELECT_PIN_IDX] =
PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
SECONDARY_I2C_ADDR_SELECT_PIN_GPIO->PDDR &= (uint32_t) ~(1 << SECONDARY_I2C_ADDR_SELECT_PIN_IDX);
}
static void secondary_i2c_slave_address_select_pin_deinit(void)
{
SECONDARY_I2C_ADDR_SELECT_PIN_PORT->PCR[SECONDARY_I2C_ADDR_SELECT_PIN_IDX] &=
(uint32_t) ~(PORT_MCR_MUX_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK);
}
#endif // BL_FEATURE_SECONDARY_I2C_SLAVE_ADDRESS
void dummy_byte_callback(uint8_t byte)
{
(void)byte;
}
void debug_init(void)
{
}
#if __ICCARM__
size_t __write(int handle, const unsigned char *buf, size_t size)
{
return size;
}
#endif // __ICCARM__
void update_available_peripherals()
{
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL82Z7/src/memory_map_MKL82Z7.c Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "memory/memory.h"
#include "qspi/qspi.h"
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
//! @brief Memory map for KL80Z7.
//!
//! This map is not const because it is updated at runtime with the actual sizes of
//! flash and RAM for the chip we're running on.
//! @note Do not change the index of Flash, SRAM, or QSPI (see memory.h).
memory_map_entry_t g_memoryMap[] = {
{ 0x00000000, 0x0001ffff, kMemoryIsExecutable, &g_flashMemoryInterface }, // Flash array (128KB)
{ 0x1fffA000, 0x20011fff, kMemoryIsExecutable, &g_normalMemoryInterface }, // SRAM (96KB)
{ 0x68000000, 0x6fffffff, kMemoryNotExecutable, &g_qspiMemoryInterface }, // QSPI memory
{ 0x40000000, 0x4007ffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS0 peripherals
{ 0x40080000, 0x400fefff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS1 peripherals
{ 0x400ff000, 0x400fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // GPIO
{ 0xe0000000, 0xe00fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // M4 private peripherals
{ 0 } // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL82Z7/src/peripherals_MKL82Z7.c Normal file
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "bootloader/bl_peripheral_interface.h"
#include "packet/serial_packet.h"
extern void uart_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void i2c_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void spi_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
#if !BL_CONFIG_LPUART && !BL_CONFIG_I2C && !BL_CONFIG_DSPI && !BL_CONFIG_USB_HID && !BL_CONFIG_USB_MSC
#error At least one peripheral must be enabled!
#endif
//! @brief Peripheral array for KL25Z4.
const peripheral_descriptor_t g_peripherals[] = {
#if BL_CONFIG_LPUART_0
// LPUART0
{.typeMask = kPeripheralType_UART,
.instance = 0,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_lpuartControlInterface,
.byteInterface = &g_lpuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPUART_0
#if BL_CONFIG_LPUART_1
// LPUART1
{.typeMask = kPeripheralType_UART,
.instance = 1,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_lpuartControlInterface,
.byteInterface = &g_lpuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPUART_1
#if BL_CONFIG_LPUART_2
// LPUART2
{.typeMask = kPeripheralType_UART,
.instance = 2,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_lpuartControlInterface,
.byteInterface = &g_lpuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPUART_2
#if BL_CONFIG_I2C
// I2C1
{.typeMask = kPeripheralType_I2CSlave,
.instance = 1,
.pinmuxConfig = i2c_pinmux_config,
.controlInterface = &g_i2cControlInterface,
.byteInterface = &g_i2cByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_I2C
#if BL_CONFIG_DSPI
// SPI1
{.typeMask = kPeripheralType_SPISlave,
.instance = 1,
.pinmuxConfig = spi_pinmux_config,
.controlInterface = &g_dspiControlInterface,
.byteInterface = &g_dspiByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_DSPI
#if (BL_CONFIG_USB_HID || BL_CONFIG_USB_MSC)
// USB HID
{.typeMask = kPeripheralType_USB_HID,
.instance = 0,
.pinmuxConfig = NULL,
.controlInterface = &g_usbHidControlInterface,
.byteInterface = NULL,
.packetInterface = &g_usbHidPacketInterface },
#endif // BL_CONFIG_USB_HID
{ 0 } // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! peripheral enable configurations
#define BL_ENABLE_PINMUX_UART0 (BL_CONFIG_LPUART_0)
#define BL_ENABLE_PINMUX_UART1 (BL_CONFIG_LPUART_1)
#define BL_ENABLE_PINMUX_UART2 (BL_CONFIG_LPUART_2)
#define BL_ENABLE_PINMUX_SPI1 (BL_CONFIG_DSPI)
#define BL_ENABLE_PINMUX_I2C1 (BL_CONFIG_I2C)
//! UART pinmux configurations
#define UART0_RX_PORT_BASE PORTB
#define UART0_RX_GPIO_BASE GPIOB
#define UART0_RX_GPIO_PIN_NUM 16 // PTB16
#define UART0_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART0 RX
#define UART0_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO
#define UART0_RX_GPIO_IRQn PORTB_IRQn
#define UART0_RX_GPIO_IRQHandler PORTB_IRQHandler
#define UART0_TX_PORT_BASE PORTB
#define UART0_TX_GPIO_PIN_NUM 17 // PTB17
#define UART0_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART0 TX
#define UART1_RX_PORT_BASE PORTC
#define UART1_RX_GPIO_BASE GPIOC
#define UART1_RX_GPIO_PIN_NUM 3 // PIN 3 in the PTC group
#define UART1_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 RX
#define UART1_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO
#define UART1_RX_GPIO_IRQn PORTC_IRQn
#define UART1_RX_GPIO_IRQHandler PORTC_IRQHandler
#define UART1_TX_PORT_BASE PORTC
#define UART1_TX_GPIO_PIN_NUM 4 // PIN 4 in the PTC group
#define UART1_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 TX
#define UART2_RX_PORT_BASE PORTD
#define UART2_RX_GPIO_BASE GPIOD
#define UART2_RX_GPIO_PIN_NUM 2 // PIN 2 in the PTD group
#define UART2_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART2 RX
#define UART2_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO
#define UART2_RX_GPIO_IRQn PORTD_IRQn
#define UART2_RX_GPIO_IRQHandler PORTD_IRQHandler
#define UART2_TX_PORT_BASE PORTD
#define UART2_TX_GPIO_PIN_NUM 3 // PIN 3 in the PTD group
#define UART2_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART2 TX
//! I2C pinmux configurations
#define I2C1_SCL_PORT_BASE PORTC
#define I2C1_SCL_GPIO_PIN_NUM 10 // PTC10
#define I2C1_SCL_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C1_SCL
#define I2C1_SDA_PORT_BASE PORTC
#define I2C1_SDA_GPIO_PIN_NUM 11 // PTC11
#define I2C1_SDA_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C1_SDA
//! SPI pinmux configurations
#define SPI1_SELECTED_PCS 0
#define SPI1_PCS_PORT_BASE PORTD
#define SPI1_PCS_GPIO_PIN_NUM 4 // PIN 4 in the PTD group
#define SPI1_PCS_FUNC_ALT_MODE kPORT_MuxAlt7 // ALT mode for SPI1 PCS
#define SPI1_SCK_PORT_BASE PORTD
#define SPI1_SCK_GPIO_PIN_NUM 5 // PIN 5 in the PTD group
#define SPI1_SCK_FUNC_ALT_MODE kPORT_MuxAlt7 // ALT mode for SPI1 SCK
#define SPI1_SOUT_PORT_BASE PORTD
#define SPI1_SOUT_GPIO_PIN_NUM 6 // PIN 6 in the PTD group
#define SPI1_SOUT_FUNC_ALT_MODE kPORT_MuxAlt7 // ALT mode for SPI1 SOUT
#define SPI1_SIN_PORT_BASE PORTD
#define SPI1_SIN_GPIO_PIN_NUM 7 // PIN 7 in the PTD group
#define SPI1_SIN_FUNC_ALT_MODE kPORT_MuxAlt7 // ALT mode for SPI1 SIN
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/* ---------------------------------------------------------------------------------------*/
/* @file: startup_MKL82Z7.s */
/* @purpose: CMSIS Cortex-M0P Core Device Startup File */
/* MKL82Z7 */
/* @version: 2.0 */
/* @date: 2015-9-24 */
/* @build: b151106 */
/* ---------------------------------------------------------------------------------------*/
/* */
/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without modification, */
/* are permitted provided that the following conditions are met: */
/* */
/* o Redistributions of source code must retain the above copyright notice, this list */
/* of conditions and the following disclaimer. */
/* */
/* o Redistributions in binary form must reproduce the above copyright notice, this */
/* list of conditions and the following disclaimer in the documentation and/or */
/* other materials provided with the distribution. */
/* */
/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
/* contributors may be used to endorse or promote products derived from this */
/* software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv6-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_DMA4_IRQHandler /* DMA channel 0, 4 transfer complete*/
.long DMA1_DMA5_IRQHandler /* DMA channel 1, 5 transfer complete*/
.long DMA2_DMA6_IRQHandler /* DMA channel 2, 6 transfer complete*/
.long DMA3_DMA7_IRQHandler /* DMA channel 3, 7 transfer complete*/
.long DMA_Error_IRQHandler /* DMA channel 0 - 7 error*/
.long FLEXIO0_IRQHandler /* Flexible IO*/
.long TPM0_IRQHandler /* Timer/PWM module 0*/
.long TPM1_IRQHandler /* Timer/PWM module 1*/
.long TPM2_IRQHandler /* Timer/PWM module 2*/
.long PIT0_IRQHandler /* Periodic Interrupt Timer 0*/
.long SPI0_IRQHandler /* Serial Peripheral Interface 0*/
.long EMVSIM0_IRQHandler /* EMVSIM0 common interrupt*/
.long LPUART0_IRQHandler /* LPUART0 status and error*/
.long LPUART1_IRQHandler /* LPUART1 status and error*/
.long I2C0_IRQHandler /* Inter-Integrated Circuit 0*/
.long QSPI0_IRQHandler /* QuadSPI0 interrupt*/
.long Reserved32_IRQHandler /* DryIce tamper detect*/
.long PORTA_IRQHandler /* Pin detect Port A*/
.long PORTB_IRQHandler /* Pin detect Port B*/
.long PORTC_IRQHandler /* Pin detect Port C*/
.long PORTD_IRQHandler /* Pin detect Port D*/
.long PORTE_IRQHandler /* Pin detect Port E*/
.long LLWU_IRQHandler /* Low Leakage Wakeup*/
.long LTC0_IRQHandler /* Low power trusted cryptographic*/
.long USB0_IRQHandler /* USB OTG interrupt*/
.long ADC0_IRQHandler /* Analog-to-Digital Converter 0*/
.long LPTMR0_IRQHandler /* Low-Power Timer 0*/
.long RTC_Seconds_IRQHandler /* RTC seconds*/
.long INTMUX0_0_IRQHandler /* Selectable peripheral interrupt INTMUX0-0*/
.long INTMUX0_1_IRQHandler /* Selectable peripheral interrupt INTMUX0-1*/
.long INTMUX0_2_IRQHandler /* Selectable peripheral interrupt INTMUX0-2*/
.long INTMUX0_3_IRQHandler /* Selectable peripheral interrupt INTMUX0-3*/
.long LPTMR1_IRQHandler /* Low-Power Timer 1 (INTMUX source IRQ0)*/
.long Reserved49_IRQHandler /* Reserved interrupt (INTMUX source IRQ1)*/
.long Reserved50_IRQHandler /* Reserved interrupt (INTMUX source IRQ2)*/
.long Reserved51_IRQHandler /* Reserved interrupt (INTMUX source IRQ3)*/
.long SPI1_IRQHandler /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
.long LPUART2_IRQHandler /* LPUART2 status and error (INTMUX source IRQ5)*/
.long EMVSIM1_IRQHandler /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
.long I2C1_IRQHandler /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
.long TSI0_IRQHandler /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
.long PMC_IRQHandler /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
.long FTFA_IRQHandler /* FTFA command complete/read collision (INTMUX source IRQ10)*/
.long MCG_IRQHandler /* Multipurpose clock generator (INTMUX source IRQ11)*/
.long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM (INTMUX source IRQ12)*/
.long DAC0_IRQHandler /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
.long TRNG0_IRQHandler /* True randon number generator (INTMUX source IRQ14)*/
.long Reserved63_IRQHandler /* Reserved interrupt (INTMUX source IRQ15)*/
.long CMP0_IRQHandler /* Comparator 0 (INTMUX source IRQ16)*/
.long Reserved65_IRQHandler /* Reserved interrupt (INTMUX source IRQ17)*/
.long RTC_Alarm_IRQHandler /* Real time clock (INTMUX source IRQ18)*/
.long Reserved67_IRQHandler /* Reserved interrupt (INTMUX source IRQ19)*/
.long Reserved68_IRQHandler /* Reserved interrupt (INTMUX source IRQ20)*/
.long Reserved69_IRQHandler /* Reserved interrupt (INTMUX source IRQ21)*/
.long Reserved70_IRQHandler /* Reserved interrupt (INTMUX source IRQ22)*/
.long Reserved71_IRQHandler /* Reserved interrupt (INTMUX source IRQ23)*/
.long DMA4_IRQHandler /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
.long DMA5_IRQHandler /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
.long DMA6_IRQHandler /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
.long DMA7_IRQHandler /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
.long Reserved76_IRQHandler /* Reserved interrupt (INTMUX source IRQ28)*/
.long Reserved77_IRQHandler /* Reserved interrupt (INTMUX source IRQ29)*/
.long Reserved78_IRQHandler /* Reserved interrupt (INTMUX source IRQ30)*/
.long Reserved79_IRQHandler /* Reserved interrupt (INTMUX source IRQ31)*/
.size __isr_vector, . - __isr_vector
/* Bootloader Config Area */
.section .BootloaderConfig, "a"
#ifdef BL_HAS_BOOTLOADER_CONFIG
//__bootloaderConfigurationArea ; 0x3c0
.long 0x6766636b // [00:03] tag - Tag value used to validate the bootloader configuration data. Must be set to 'kcfg'
.long 0xFFFFFFFF // [04:07] crcStartAddress
.long 0xFFFFFFFF // [08:0b] crcByteCount
.long 0xFFFFFFFF // [0c:0f] crcExpectedValue
.byte 0xFF // [10:10] enabledPeripherals
.byte 0xFF // [11:11] i2cSlaveAddress
.short 5000 // [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code
.short 0xFFFF // [14:15] usbVid
.short 0xFFFF // [16:17] usbPid
.long 0xFFFFFFFF // [18:1b] usbStringsPointer
.byte 0xFF // [1c:1c] clockFlags - High Speed and other clock options
.byte 0xFF // [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1
.short 0xFFFF // [1e:1f] reserved
// Fill to align with flash configuration field.
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF // Reserved for user TRIM value
#else
//Fill to align with flash configuration field.
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF // Reserved for user TRIM value
#endif // BL_HAS_BOOTLOADER_CONFIG
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFF3DFE
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
ldr r0,=init_data_bss
blx r0
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
ldr r0, =DefaultISR
bx r0
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak DMA0_DMA4_IRQHandler
.type DMA0_DMA4_IRQHandler, %function
DMA0_DMA4_IRQHandler:
ldr r0,=DMA0_DMA4_DriverIRQHandler
bx r0
.size DMA0_DMA4_IRQHandler, . - DMA0_DMA4_IRQHandler
.align 1
.thumb_func
.weak DMA1_DMA5_IRQHandler
.type DMA1_DMA5_IRQHandler, %function
DMA1_DMA5_IRQHandler:
ldr r0,=DMA1_DMA5_DriverIRQHandler
bx r0
.size DMA1_DMA5_IRQHandler, . - DMA1_DMA5_IRQHandler
.align 1
.thumb_func
.weak DMA2_DMA6_IRQHandler
.type DMA2_DMA6_IRQHandler, %function
DMA2_DMA6_IRQHandler:
ldr r0,=DMA2_DMA6_DriverIRQHandler
bx r0
.size DMA2_DMA6_IRQHandler, . - DMA2_DMA6_IRQHandler
.align 1
.thumb_func
.weak DMA3_DMA7_IRQHandler
.type DMA3_DMA7_IRQHandler, %function
DMA3_DMA7_IRQHandler:
ldr r0,=DMA3_DMA7_DriverIRQHandler
bx r0
.size DMA3_DMA7_IRQHandler, . - DMA3_DMA7_IRQHandler
.align 1
.thumb_func
.weak DMA_Error_IRQHandler
.type DMA_Error_IRQHandler, %function
DMA_Error_IRQHandler:
ldr r0,=DMA_Error_DriverIRQHandler
bx r0
.size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler
.align 1
.thumb_func
.weak FLEXIO0_IRQHandler
.type FLEXIO0_IRQHandler, %function
FLEXIO0_IRQHandler:
ldr r0,=FLEXIO0_DriverIRQHandler
bx r0
.size FLEXIO0_IRQHandler, . - FLEXIO0_IRQHandler
.align 1
.thumb_func
.weak SPI0_IRQHandler
.type SPI0_IRQHandler, %function
SPI0_IRQHandler:
ldr r0,=SPI0_DriverIRQHandler
bx r0
.size SPI0_IRQHandler, . - SPI0_IRQHandler
.align 1
.thumb_func
.weak LPUART0_IRQHandler
.type LPUART0_IRQHandler, %function
LPUART0_IRQHandler:
ldr r0,=LPUART0_DriverIRQHandler
bx r0
.size LPUART0_IRQHandler, . - LPUART0_IRQHandler
.align 1
.thumb_func
.weak LPUART1_IRQHandler
.type LPUART1_IRQHandler, %function
LPUART1_IRQHandler:
ldr r0,=LPUART1_DriverIRQHandler
bx r0
.size LPUART1_IRQHandler, . - LPUART1_IRQHandler
.align 1
.thumb_func
.weak I2C0_IRQHandler
.type I2C0_IRQHandler, %function
I2C0_IRQHandler:
ldr r0,=I2C0_DriverIRQHandler
bx r0
.size I2C0_IRQHandler, . - I2C0_IRQHandler
.align 1
.thumb_func
.weak QSPI0_IRQHandler
.type QSPI0_IRQHandler, %function
QSPI0_IRQHandler:
ldr r0,=QSPI0_DriverIRQHandler
bx r0
.size QSPI0_IRQHandler, . - QSPI0_IRQHandler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_DMA4_DriverIRQHandler
def_irq_handler DMA1_DMA5_DriverIRQHandler
def_irq_handler DMA2_DMA6_DriverIRQHandler
def_irq_handler DMA3_DMA7_DriverIRQHandler
def_irq_handler DMA_Error_DriverIRQHandler
def_irq_handler FLEXIO0_DriverIRQHandler
def_irq_handler TPM0_IRQHandler
def_irq_handler TPM1_IRQHandler
def_irq_handler TPM2_IRQHandler
def_irq_handler PIT0_IRQHandler
def_irq_handler SPI0_DriverIRQHandler
def_irq_handler EMVSIM0_IRQHandler
def_irq_handler LPUART0_DriverIRQHandler
def_irq_handler LPUART1_DriverIRQHandler
def_irq_handler I2C0_DriverIRQHandler
def_irq_handler QSPI0_DriverIRQHandler
def_irq_handler Reserved32_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler LLWU_IRQHandler
def_irq_handler LTC0_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler INTMUX0_0_IRQHandler
def_irq_handler INTMUX0_1_IRQHandler
def_irq_handler INTMUX0_2_IRQHandler
def_irq_handler INTMUX0_3_IRQHandler
def_irq_handler LPTMR1_IRQHandler
def_irq_handler Reserved49_IRQHandler
def_irq_handler Reserved50_IRQHandler
def_irq_handler Reserved51_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler LPUART2_IRQHandler
def_irq_handler EMVSIM1_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler TSI0_IRQHandler
def_irq_handler PMC_IRQHandler
def_irq_handler FTFA_IRQHandler
def_irq_handler MCG_IRQHandler
def_irq_handler WDOG_EWM_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler TRNG0_IRQHandler
def_irq_handler Reserved63_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler Reserved65_IRQHandler
def_irq_handler RTC_Alarm_IRQHandler
def_irq_handler Reserved67_IRQHandler
def_irq_handler Reserved68_IRQHandler
def_irq_handler Reserved69_IRQHandler
def_irq_handler Reserved70_IRQHandler
def_irq_handler Reserved71_IRQHandler
def_irq_handler DMA4_IRQHandler
def_irq_handler DMA5_IRQHandler
def_irq_handler DMA6_IRQHandler
def_irq_handler DMA7_IRQHandler
def_irq_handler Reserved76_IRQHandler
def_irq_handler Reserved77_IRQHandler
def_irq_handler Reserved78_IRQHandler
def_irq_handler Reserved79_IRQHandler
.end

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/*
** ###################################################################
** Processors: MKL82Z128VLH7
** MKL82Z128VLK7
** MKL82Z128VLL7
** MKL82Z128VMC7
** MKL82Z128VMP7
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL82P121M72SF0RM, Rev.1.2 September 2015
** Version: rev. 1.5, 2015-09-24
** Build: b151023
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2015-04-18)
** Initial version.
** - rev. 1.1 (2015-05-04)
** Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
** - rev. 1.2 (2015-08-11)
** Correct clock configuration.
** - rev. 1.3 (2015-08-20)
** Align with RM Rev.1.
** - rev. 1.4 (2015-08-28)
** Update LPUART to add FIFO.
** - rev. 1.5 (2015-09-24)
** Update to align with RM Rev.1.2.
**
** ###################################################################
*/
/*!
* @file MKL82Z7
* @version 1.5
* @date 2015-09-24
* @brief Device specific configuration file for MKL82Z7 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "system_MKL82Z7.h"
#include "fsl_device_registers.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit(void)
{
#if (DISABLE_WDOG)
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG->STCTRLH:
* ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
*/
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
#endif /* (DISABLE_WDOG) */
}

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/*
** ###################################################################
** Processors: MKL82Z128VLH7
** MKL82Z128VLK7
** MKL82Z128VLL7
** MKL82Z128VMC7
** MKL82Z128VMP7
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL82P121M72SF0RM, Rev.1.2 September 2015
** Version: rev. 1.5, 2015-09-24
** Build: b151023
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2015-04-18)
** Initial version.
** - rev. 1.1 (2015-05-04)
** Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
** - rev. 1.2 (2015-08-11)
** Correct clock configuration.
** - rev. 1.3 (2015-08-20)
** Align with RM Rev.1.
** - rev. 1.4 (2015-08-28)
** Update LPUART to add FIFO.
** - rev. 1.5 (2015-09-24)
** Update to align with RM Rev.1.2.
**
** ###################################################################
*/
/*!
* @file MKL82Z7
* @version 1.5
* @date 2015-09-24
* @brief Device specific configuration file for MKL82Z7 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_MKL82Z7_H_
#define _SYSTEM_MKL82Z7_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* MCG mode constants */
#define MCG_MODE_FEI 0U
#define MCG_MODE_FBI 1U
#define MCG_MODE_BLPI 2U
#define MCG_MODE_FEE 3U
#define MCG_MODE_FBE 4U
#define MCG_MODE_BLPE 5U
#define MCG_MODE_PBE 6U
#define MCG_MODE_PEE 7U
/* Predefined clock setups
0 ... Default part configuration
Multipurpose Clock Generator (MCG) in FEI mode.
Reference clock source for MCG module: Slow internal reference clock
Core clock = 20.97152MHz
Bus clock = 20.97152MHz
1 ... Maximal speed configuration
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 96MHz
Bus clock = 24MHz
2 ... Chip internally clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPI mode.
Reference clock source for MCG module: Fast internal reference clock
Core clock = 4MHz
Bus clock = 4MHz
3 ... Chip externally clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 4MHz
Bus clock = 4MHz
4 ... USB clock setup
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 96MHz
Bus clock = 24MHz
5 ... Maximum achievable clock frequency configuration in RUN mode
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 72MHz
Bus clock = 24MHz
*/
/* Define clock source values */
#define CPU_XTAL_CLK_HZ \
12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
#define CPU_XTAL32k_CLK_HZ \
32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
*/
#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
/* RTC oscillator setting */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
/* Internal reference clock trim */
/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
#ifdef CLOCK_SETUP
#if (CLOCK_SETUP == 0)
#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1,OUTDIV5=1 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00011000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 1)
#define DEFAULT_SYSTEM_CLOCK 96000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 2)
#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=4,OUTDIV5=0 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03040000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 3)
#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0x0B */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 4)
#define DEFAULT_SYSTEM_CLOCK 96000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=3,USBFRAC=0 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x03U /* SIM_CLKDIV2 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 5)
#define DEFAULT_SYSTEM_CLOCK 72000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=8 */
#define SYSTEM_MCG_C6_VALUE 0x48U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=2,OUTDIV4=2,OUTDIV5=0 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x02020000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
#endif
#else
#define DEFAULT_SYSTEM_CLOCK 20971520u
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_MKL82Z7_H_ */

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__TARGET_CONFIG_H__)
#define __TARGET_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief Constants for clock frequencies.
enum _target_clocks
{
kDefaultClock = 20971520u,
kFLL_72MHz = 72000000ul,
kFLL_48MHz = 48000000ul,
kFLL_HighFreq = 72000000ul,
kHIRC = 48000000u,
kMinCoreClockWithUsbSupport = 20000000u,
kMaxCoreClock = 720000000u,
kMaxBusClock = 25000000u,
kMaxFlashClock = 25000000u,
kDivider_Min = 1,
kDivider_Max = 16,
};
//! @brief Constants for sram partition
enum _sram_partition
{
kSram_LowerPart = 1,
kSram_UpperPart = 3,
};
//! @brief Version constants for the target.
enum _target_version_constants
{
kTarget_Version_Name = 'T',
kTarget_Version_Major = 1,
kTarget_Version_Minor = 0,
kTarget_Version_Bugfix = 0
};
//! CRC check pinmux configurations
// Note: This default muxing slot of selected crc check failure pin must be ALT0
#define CRC_CHECK_FAILURE_PIN_NUMBER 5
#define CRC_CHECK_FAILURE_PIN_PORT PORTC
#define CRC_CHECK_FAILURE_PIN_GPIO GPIOC
#define CRC_CHECK_FAILURE_PIN_DEFAULT_MODE 0
#define CRC_CHECK_FAILURE_PIN_GPIO_MODE 1
#endif // __TARGET_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __USB_DEVICE_CONFIG_H__
#define __USB_DEVICE_CONFIG_H__ 1
#include "bootloader_common.h"
/*!
* @addtogroup usb_device_configuration
* @{
*/
/*!
* @name Hardware instance define
* @{
*/
/*! @brief KHCI instance count */
#define USB_DEVICE_CONFIG_KHCI (BL_CONFIG_USB_HID | BL_CONFIG_USB_MSC)
/*! @brief EHCI instance count */
#define USB_DEVICE_CONFIG_EHCI (0U)
/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/
#define USB_DEVICE_CONFIG_NUM (1) // (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI)
/* @} */
/*!
* @name class instance define
* @{
*/
/*! @brief HID instance count */
#define USB_DEVICE_CONFIG_HID (BL_CONFIG_USB_HID)
/*! @brief CDC ACM instance count */
#define USB_DEVICE_CONFIG_CDC_ACM (0U)
/*! @brief MSC instance count */
#define USB_DEVICE_CONFIG_MSC (BL_CONFIG_USB_MSC)
/*! @brief Audio instance count */
#define USB_DEVICE_CONFIG_AUDIO (0U)
/*! @brief PHDC instance count */
#define USB_DEVICE_CONFIG_PHDC (0U)
/*! @brief Video instance count */
#define USB_DEVICE_CONFIG_VIDEO (0U)
/*! @brief CCID instance count */
#define USB_DEVICE_CONFIG_CCID (0U)
/*! @brief Printer instance count */
#define USB_DEVICE_CONFIG_PRINTER (0U)
/*! @brief DFU instance count */
#define USB_DEVICE_CONFIG_DFU (0U)
/* @} */
/*! @brief Whether device is self power. 1 supported, 0 not supported */
#define USB_DEVICE_CONFIG_SELF_POWER (1U)
/*! @brief Whether device remote wakeup supported. 1 supported, 0 not supported */
#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
/*! @brief How many endpoints are supported in the stack. */
#define USB_DEVICE_CONFIG_ENDPOINTS (8U)
/*! @brief Whether the device task is enabled. */
#define USB_DEVICE_CONFIG_USE_TASK (0U)
/*! @brief How many the notification message are supported when the device task enabled. */
#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U)
#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
/*! @brief The MAX buffer length for the KHCI DMA workaround.*/
/* clang-format off */
#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U)
/*! @brief Whether handle the USB KHCI bus error. */
#define USB_DEVICE_CONFIG_KHCI_ERROR_HANDLING (0U)
/* clang-format on */
#endif
#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
/*! @brief How many the DTD are supported. */
/* clang-format off */
#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
/*! @brief Whether handle the USB EHCI bus error. */
#define USB_DEVICE_CONFIG_EHCI_ERROR_HANDLING (0U)
/*! @brief Whether test mode enabled. */
#define USB_DEVICE_CONFIG_EHCI_TEST_MODE (0U)
/*! @brief Whether the EHCI ID pin detect feature enabled. */
#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U)
/* clang-format on */
#endif
/*! @brief Whether the keep alive feature enabled. */
/* clang-format off */
#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U)
/*! @brief Whether the transfer buffer is cache-enabled or not. */
#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
/*! @brief Whether the low power mode is enabled or not. */
#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
/*! @brief Whether the device detached feature is enabled or not. */
#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
/* clang-format on */
/* @} */
#endif /* __USB_DEVICE_CONFIG_H__ */