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László Monda
2016-08-10 01:45:15 +02:00
commit e6c1fce5b4
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78
targets/MKL28Z7/src/bl_lpi2c_irq_config_MKL28Z7.c Normal file
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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_config.h"
#include "bootloader/bl_peripheral_interface.h"
#include "fsl_device_registers.h"
#include "intmux/fsl_intmux.h"
#include "lpi2c/fsl_lpi2c.h"
#include "bootloader_common.h"
#include <assert.h>
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
static const IRQn_Type lpi2c_irq_ids[FSL_FEATURE_SOC_LPI2C_COUNT] = {
LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn,
};
void LPI2C_SetSystemIRQ(uint32_t instance, PeripheralSystemIRQSetting set)
{
switch (instance)
{
case 2:
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(INTMUX0_1_IRQn);
INTMUX0->CHANNEL[1].CHn_IER_31_0 |= 1 << lpi2c_irq_ids[instance];
}
else
{
NVIC_DisableIRQ(INTMUX0_1_IRQn);
INTMUX0->CHANNEL[1].CHn_IER_31_0 &= ~(1 << lpi2c_irq_ids[instance]);
}
break;
case 0:
case 1:
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(lpi2c_irq_ids[instance]);
}
else
{
NVIC_DisableIRQ(lpi2c_irq_ids[instance]);
}
break;
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL28Z7/src/bl_lpspi_irq_config_MKL28Z7.c Normal file
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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_config.h"
#include "bootloader/bl_peripheral_interface.h"
#include "fsl_device_registers.h"
#include "intmux/fsl_intmux.h"
#include "lpspi/fsl_lpspi.h"
#include "bootloader_common.h"
#include <assert.h>
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
static const IRQn_Type lpspi_irq_ids[FSL_FEATURE_SOC_LPSPI_COUNT] = {
LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn,
};
void LPSPI_SetSystemIRQ(uint32_t instance, PeripheralSystemIRQSetting set)
{
switch (instance)
{
case 2:
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(INTMUX0_2_IRQn);
// LPSPI2_IRQ is assigned to INTMUX, LPTMR1_IRQ is the first irq assigned to INTMUX.
// So LPSPI2_IRQ id - LPTMR1_IRQ id is the index of LPSPI2_IRQ in INTMUX.
INTMUX0->CHANNEL[2].CHn_IER_31_0 |= 1 << (lpspi_irq_ids[instance] - LPTMR1_IRQn);
}
else
{
NVIC_DisableIRQ(INTMUX0_2_IRQn);
INTMUX0->CHANNEL[2].CHn_IER_31_0 &= ~(1 << (lpspi_irq_ids[instance] - LPTMR1_IRQn));
}
break;
case 0:
case 1:
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(lpspi_irq_ids[instance]);
}
else
{
NVIC_DisableIRQ(lpspi_irq_ids[instance]);
}
break;
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL28Z7/src/bl_lpuart_irq_config_MKL28Z7.c Normal file
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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "bootloader_common.h"
#include "bootloader_config.h"
#include "bootloader/bl_peripheral_interface.h"
#include "autobaud/autobaud.h"
#include "packet/serial_packet.h"
#include "fsl_device_registers.h"
#include "intmux/fsl_intmux.h"
#include "lpuart/fsl_lpuart.h"
#include "utilities/fsl_assert.h"
static const IRQn_Type lpuart_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {
LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn,
};
void LPUART_SetSystemIRQ(uint32_t instance, PeripheralSystemIRQSetting set)
{
switch (instance)
{
case 2:
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(INTMUX0_0_IRQn);
INTMUX0->CHANNEL[0].CHn_IER_31_0 |= 1 << lpuart_irq_ids[instance];
}
else
{
NVIC_DisableIRQ(INTMUX0_0_IRQn);
INTMUX0->CHANNEL[0].CHn_IER_31_0 &= ~(1 << lpuart_irq_ids[instance]);
}
break;
case 0:
case 1:
if (set == kPeripheralEnableIRQ)
{
NVIC_EnableIRQ(lpuart_irq_ids[instance]);
}
else
{
NVIC_DisableIRQ(lpuart_irq_ids[instance]);
}
break;
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL28Z7/src/bootloader_config.h Normal file
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/*
* Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BOOTLOADER_CONFIG_H__
#define __BOOTLOADER_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//
// Bootloader configuration options
//
//! @name Peripheral configuration macros
//@{
#define BL_FEATURE_ROM_UART_PORT (0)
#define BL_FEATURE_ROM_I2C_PORT (0)
#define BL_FEATURE_ROM_SPI_PORT (0)
#if !defined(BL_CONFIG_LPUART_0)
#define BL_CONFIG_LPUART_0 (1)
#endif
#if !defined(BL_CONFIG_LPUART_1)
#define BL_CONFIG_LPUART_1 (BL_FEATURE_ROM_UART_PORT)
#endif
#if !defined(BL_CONFIG_LPUART_2)
#define BL_CONFIG_LPUART_2 (BL_FEATURE_ROM_UART_PORT)
#endif
#define BL_CONFIG_LPUART (BL_CONFIG_LPUART_0 || BL_CONFIG_LPUART_1 || BL_CONFIG_LPUART_2)
#if !defined(BL_CONFIG_LPI2C_0)
#define BL_CONFIG_LPI2C_0 (0)
#endif
#if !defined(BL_CONFIG_LPI2C_1)
#define BL_CONFIG_LPI2C_1 (1)
#endif
#if !defined(BL_CONFIG_LPI2C_2)
#define BL_CONFIG_LPI2C_2 (0)
#endif
#define BL_CONFIG_LPI2C (BL_CONFIG_LPI2C_0 || BL_CONFIG_LPI2C_1 || BL_CONFIG_LPI2C_2)
#if !defined(BL_CONFIG_LPSPI_0)
#define BL_CONFIG_LPSPI_0 (0)
#endif
#if !defined(BL_CONFIG_LPSPI_1)
#define BL_CONFIG_LPSPI_1 (0)
#endif
#if !defined(BL_CONFIG_LPSPI_2)
#define BL_CONFIG_LPSPI_2 (1)
#endif
#define BL_CONFIG_LPSPI (BL_CONFIG_LPSPI_0 || BL_CONFIG_LPSPI_1 || BL_CONFIG_LPSPI_2)
#if !defined(BL_CONFIG_USB_HID)
#define BL_CONFIG_USB_HID (1)
#endif
#if !defined(BL_CONFIG_USB_MSC)
#define BL_CONFIG_USB_MSC (1)
#endif
//@}
#if !defined(BL_TARGET_FLASH) && !defined(BL_TARGET_RAM)
#define BL_TARGET_FLASH (1)
#endif
#if defined(BL_TARGET_RAM)
#define BL_FEATURE_FLASH_SECURITY (0)
#else
#define BL_FEATURE_FLASH_SECURITY (1)
#endif
#define BL_FEATURE_MIN_PROFILE (0)
#define BL_FEATURE_ERASEALL_UNSECURE (0)
#define BL_FEATURE_FLASH_VERIFY_DISABLE (0)
#if !defined(BL_TARGET_RAM)
#define BL_FEATURE_CRC_CHECK (1)
#endif
#define BL_FEATURE_READ_MEMORY (1)
#define BL_FEATURE_QSPI_MODULE (0)
#define BL_FEATURE_ENCRYPTION_MMCAU (1)
#define BL_FEATURE_ENCRYPTION (BL_FEATURE_ENCRYPTION_MMCAU)
#define BL_FEATURE_UART_AUTOBAUD_IRQ (1)
#define BL_HAS_MULTI_CORE (0)
#define BL_FEATURE_UART_RX_PULLUP (1)
// Bootloader peripheral detection default timeout in milliseconds
// After coming out of reset the bootloader will spin in a peripheral detection
// loop for this amount of time. A zero value means no time out.
#if DEBUG
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 0
#else
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 5000
#endif // DEBUG
// The bootloader will check this address for the application vector table upon startup.
#if !defined(BL_APP_VECTOR_TABLE_ADDRESS)
#define BL_APP_VECTOR_TABLE_ADDRESS 0xA000
#endif
// The bootloader will calculate the start address and end address of RAM based on following definitions.
#define RAM_LOWER_PART (1)
#define RAM_UPPER_PART (3)
/* Serial Port Info */
/**************************************************************************
* Note:
*
* Because of the changes to the UART modules, we can no longer define
* the TERM_PORT as a base pointer. The uart functions have been modified
* accommodate this change. Now, TERM_PORT_NUM must be defined as the
* number of the UART port desired to use
*
* TERM_PORT_NUM = 0 -- This allows you to use UART0; default pins are
* PTA14 and PTA15
*
* TERM_PORT_NUM = 1 -- This allows you to use UART1; default pins are
* PTC3 and PTC4
*
* TERM_PORT_NUM = 2 -- This allows you to use UART2; default pins are
* PTD2 and PTD3
*
*************************************************************************/
#define TERM_PORT_NUM 0
#define TERMINAL_BAUD 19200
#undef HW_FLOW_CONTROL
#endif // __BOOTLOADER_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL28Z7/src/clock_config_MKL28Z7.c Normal file
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/*
* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h"
#include "bootloader/bl_context.h"
#include "property/property.h"
#include "fsl_device_registers.h"
#include "utilities/fsl_assert.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
typedef enum _clock_soruce_enum
{
kClockSource_SystemOSC = 1u,
kClockSource_SlowIRC = 2u,
kClockSource_FastIRC = 3u,
kClockSource_RtcOSC = 4u,
kClockSource_SystemCFM = 5u,
kClockSource_SystemPLL = 6u,
kClockSource_UsbPhyPLL = 7u,
} clock_source_type_t;
enum
{
kFIRC48M = 48000000ul,
kFIRC52M = 52000000ul,
kFIRC56M = 56000000ul,
kFIRC60M = 60000000ul,
kIRC8M = 8000000ul,
kIRC2M = 2000000ul,
//! The minimum core clock with usb workable is
kMinCoreClockWithUsbSupport = 20000000u,
};
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
//! return the frequency of HIRC
uint32_t get_firc_clock(void);
//! return the frequency of SIRC
uint32_t get_sirc_clock(void);
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
uint32_t get_firc_clock(void)
{
uint32_t range = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
uint32_t clockFreq = 0;
switch (range)
{
case 0:
clockFreq = kFIRC48M;
break;
case 1:
clockFreq = kFIRC52M;
break;
case 2:
clockFreq = kFIRC56M;
break;
case 4:
clockFreq = kFIRC60M;
break;
default:
assert(false);
break;
}
return clockFreq;
}
uint32_t get_sirc_clock(void)
{
uint32_t range = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
return range ? kIRC8M : kIRC2M;
}
// See bootloader_common.h for documentation on this function.
void configure_clocks(bootloader_clock_option_t option)
{
#if defined(BL_TARGET_FLASH)
// General procedure to be implemented:
// 1. Read clock flags and divider from bootloader config in property store
bootloader_configuration_data_t *config = &g_bootloaderContext.propertyInterface->store->configurationData;
uint8_t options = config->clockFlags;
// Check if the USB HID peripheral is enabled. If it is enabled, we always
// use the 48MHz IRC.
bool isUsbEnabled = config->enabledPeripherals & kPeripheralType_USB_HID;
// 2. If NOT High Speed and USB is NOT enabled, do nothing (use reset clock config)
if ((options & kClockFlag_HighSpeed) && !isUsbEnabled)
{
// High speed flag is set (meaning disabled), so just use default clocks.
return;
}
// 3. Set DIVCORE based on divider in config. OUTDIV4 starts out at /1.
// The divider values are masked by the maximum bits per divider.
uint32_t divCore = ((~config->clockDivider) & (SCG_CSR_DIVCORE_MASK >> SCG_CSR_DIVCORE_SHIFT)) + 1;
uint32_t divSlow = ((SCG->CSR & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT) + 1;
uint32_t firc_clock = get_firc_clock();
// If USB is enabled, the CPU clock must not be allowed to go below 20 MHz. So the max
// DIVCORE divider is 2.
if (isUsbEnabled)
{
while ((divCore * kMinCoreClockWithUsbSupport) > firc_clock)
{
divCore--;
assert(divCore);
}
}
// Update SystemCoreClock global.
SystemCoreClock = firc_clock / divCore;
// 4. Keep bus freq below max.
//
// The bus/flash clock is divided by DIVSLOW in addition to DIVCORE:
// SCGCLOCK -> DIVCORE -> DIVSLOW -> bus_clk
uint32_t freq = SystemCoreClock;
while ((kMaxBusClock * divSlow) < freq)
{
// Increase bus/flash clock divider.
++divSlow;
}
// 5. Now set the dividers before we switch to the 48MHz clock.
uint32_t tmp = SCG->RCCR;
tmp &= (uint32_t) ~(SCG_RCCR_DIVCORE_MASK | SCG_RCCR_DIVSLOW_MASK);
tmp |= SCG_RCCR_DIVCORE(divCore - 1) | SCG_RCCR_DIVSLOW(divSlow - 1);
SCG->RCCR = tmp;
// 6. Turn on 48MHz IRC
uint32_t clockSource = (SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT;
;
if (clockSource != kClockSource_FastIRC)
{
SCG->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK;
tmp = SCG->RCCR;
tmp &= (uint32_t)~SCG_RCCR_SCS_MASK;
tmp |= SCG_RCCR_SCS(kClockSource_FastIRC);
SCG->RCCR = tmp;
}
// Wait until the switch to HIRC is completed.
while (!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK))
{
}
#endif // defined(BL_TARGET_FLASH)
}
// See bootloader_common.h for documentation on this function.
uint32_t get_system_core_clock(void)
{
uint32_t systemCoreClock = SystemCoreClock;
// Update SystemCoreClock out of reset.
clock_source_type_t clocksource = (clock_source_type_t)((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT);
// Default clock source: FastIRC
uint32_t systemClock = get_firc_clock();
// Clock source is Slow IRC
if (clocksource == kClockSource_SlowIRC)
{
systemClock = get_sirc_clock();
}
uint32_t coreClockDivider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
systemCoreClock = systemClock / coreClockDivider;
return systemCoreClock;
}
// See bootloader_common.h for documentation on this function.
uint32_t get_bus_clock(void)
{
uint32_t busClockDivider = ((SCG->CSR & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT) + 1;
return SystemCoreClock / busClockDivider;
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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targets/MKL28Z7/src/hardware_init_MKL28Z7.c Normal file
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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h"
#include "bootloader/bl_context.h"
#include "fsl_device_registers.h"
#include "intmux/fsl_intmux.h"
#include "smc/smc.h"
#include "lpuart/fsl_lpuart.h"
#include "utilities/fsl_assert.h"
#include "wdog32/fsl_wdog32.h"
#if BL_ENABLE_CRC_CHECK
#include "bootloader/bl_app_crc_check.h"
#endif
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
enum
{
//! @brief Mask for the bit of RCM_MR[BOOTROM] indicating that the BOOTCFG0 pin was asserted.
kBootedViaPinMask = 1
};
enum _peripheral_clock_source
{
kPeripheralClockSource_CLKOFF = 0,
kPeripheralClockSource_OSCCLK = 1,
kPeripheralClockSource_SCGIRCLK = 2,
kPeripheralClockSource_SCGFIRCLK = 3,
kPeripheralClockSource_SCGPCLK = 6
};
static INTMUX_Type *const s_intmuxBase[] = INTMUX_BASE_PTRS;
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
//! return the frequency of HIRC
extern uint32_t get_firc_clock(void);
//! return the frequency of SIRC
extern uint32_t get_sirc_clock(void);
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void init_hardware(void)
{
#if defined(BL_TARGET_ROM)
// If we are in VLPR mode, exit it
//! @todo If exiting from VLPR mode, we need to raise/restore clocks afterwards.
exit_vlpr();
#endif
// Enable clocks to ports.
PCC0->CLKCFG[PCC_PORTA_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_CGC_MASK;
PCC0->CLKCFG[PCC_PORTB_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_CGC_MASK;
PCC0->CLKCFG[PCC_PORTC_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_CGC_MASK;
PCC0->CLKCFG[PCC_PORTD_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_CGC_MASK;
PCC0->CLKCFG[PCC_PORTE_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_CGC_MASK;
// Configure Divider for SLOW_SRC_CLK
uint32_t tmp = SCG->SIRCDIV;
tmp &= SCG_SIRCDIV_SIRCDIV3_MASK;
tmp |= SCG_SIRCDIV_SIRCDIV3(1);
SCG->SIRCDIV = tmp;
// Select the SCGIRCLK as LPUARTx clock source.
PCC0->CLKCFG[PCC_LPUART2_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
PCC0->CLKCFG[PCC_LPUART1_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
PCC1->CLKCFG[PCC_LPUART0_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
// Select the SCGIRCLK as LPSPIx/I2Cx clock source.
PCC0->CLKCFG[PCC_LPSPI2_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
PCC0->CLKCFG[PCC_LPSPI1_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
PCC1->CLKCFG[PCC_LPSPI0_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
PCC0->CLKCFG[PCC_LPI2C2_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
PCC0->CLKCFG[PCC_LPI2C1_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
PCC1->CLKCFG[PCC_LPI2C0_INDEX & PCC_PERIPHERAL_MASK] |= PCC_CLKCFG_PCS(kPeripheralClockSource_SCGIRCLK);
SystemCoreClock = get_system_core_clock();
// Enable clock to INTMUX0 and reset all channels
INTMUX_Init((INTMUX_Type *)s_intmuxBase[0]);
}
void deinit_hardware(void)
{
#if BL_ENABLE_CRC_CHECK && BL_FEATURE_CRC_ASSERT
restore_crc_check_failure_pin();
#endif
PCC0->CLKCFG[PCC_PORTA_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_CGC_MASK;
PCC0->CLKCFG[PCC_PORTB_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_CGC_MASK;
PCC0->CLKCFG[PCC_PORTC_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_CGC_MASK;
PCC0->CLKCFG[PCC_PORTD_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_CGC_MASK;
PCC0->CLKCFG[PCC_PORTE_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_CGC_MASK;
// Restore SIM/PCC related bits being changed
SIM->SOPT1 &= (uint32_t)~SIM_SOPT1_USBREGEN_MASK;
// Disable peripheral clock
PCC0->CLKCFG[PCC_LPUART2_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC0->CLKCFG[PCC_LPUART1_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC1->CLKCFG[PCC_LPUART0_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC0->CLKCFG[PCC_LPSPI2_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC0->CLKCFG[PCC_LPSPI1_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC1->CLKCFG[PCC_LPSPI0_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC0->CLKCFG[PCC_LPI2C2_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC0->CLKCFG[PCC_LPI2C1_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC1->CLKCFG[PCC_LPI2C0_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
PCC0->CLKCFG[PCC_USB0FS_INDEX & PCC_PERIPHERAL_MASK] &= (uint32_t)~PCC_CLKCFG_PCS_MASK;
INTMUX_Deinit((INTMUX_Type *)s_intmuxBase[0]);
// Restore SCG_SIRCDIV_SIRCDIV3 to default value.
SCG->SIRCDIV &= (uint32_t)~SCG_SIRCDIV_SIRCDIV3_MASK;
WDOG32_Deinit(WDOG0);
}
bool usb_clock_init(void)
{
// Select IRC48M clock
// Configure USB
// Enable USB-FS IP clocking
PCC0->CLKCFG[PCC_USB0FS_INDEX & PCC_PERIPHERAL_MASK] |=
PCC_CLKCFG_PCS(kPeripheralClockSource_SCGFIRCLK) | PCC_CLKCFG_CGC_MASK;
// Configure enable USB regulator for device
SIM->SOPT1 |= SIM_SOPT1_USBREGEN_MASK;
SCG->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK;
SCG->RCCR = ((~SCG_RCCR_SCS_MASK) & SCG->RCCR) | SCG_RCCR_SCS(3);
while (!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK))
{
}
// Configure Divider for FAST_SRC_CLK
SCG->FIRCDIV = ((~SCG_FIRCDIV_FIRCDIV1_MASK) & SCG->FIRCDIV) | SCG_FIRCDIV_FIRCDIV1(1);
// Configure enable USB regulator for device
SIM->SOPT1 |= SIM_SOPT1_USBREGEN_MASK;
SCG->FIRCCSR = ((~SCG_FIRCCSR_FIRCTREN_MASK) & SCG->FIRCCSR) | SCG_FIRCCSR_FIRCTREN(1);
USB0->USBCTRL = USB_CONTROL_DPPULLUPNONOTG_MASK;
USB0->USBTRC0 |= 0x40; /* Software must set this bit to 1 */
// need to set the clock_recover_en and irc_en register
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
// Update global SystemCoreClock variable
SystemCoreClock = get_system_core_clock();
return true;
}
uint32_t get_uart_clock(uint32_t instance)
{
return get_sirc_clock();
}
bool is_boot_pin_asserted(void)
{
return false;
}
#if DEBUG && __ICCARM__
// Included only to satisfy linker.
size_t __write(int handle, const unsigned char *buf, size_t size)
{
return size;
}
#endif // DEBUG && __ICCARM__
void debug_init(void)
{
}
void update_available_peripherals()
{
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "memory/memory.h"
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
//! @brief Memory map for KL28T512.
//!
//! This map is not const because it is updated at runtime with the actual sizes of
//! flash and RAM for the chip we're running on.
memory_map_entry_t g_memoryMap[] = {
{ 0x00000000, 0x0007ffff, kMemoryIsExecutable, &g_flashMemoryInterface }, // 512kB Flash array
{ 0x1fff8000, 0x20017fff, kMemoryIsExecutable, &g_normalMemoryInterface }, // 128kB SRAM
{ 0x40000000, 0x4007ffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS0 peripherals
{ 0x40080000, 0x400fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS1 peripherals
{ 0x44000000, 0x5fffffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // BME
{ 0xf0000000, 0xf0006fff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // M0+ Private Peripheral Bus 0 (CPU0)
{ 0xf8000000, 0xffffffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // IOPORT (single-cycle GPIO)
{ 0 } // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "bootloader/bl_peripheral_interface.h"
#include "packet/serial_packet.h"
extern void uart_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void i2c_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void spi_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
//! @brief Peripheral array for KL43Z4.
const peripheral_descriptor_t g_peripherals[] = {
#if BL_CONFIG_LPUART_0
// LPUART0
{.typeMask = kPeripheralType_UART,
.instance = 0,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_lpuartControlInterface,
.byteInterface = &g_lpuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPUART_0
#if BL_CONFIG_LPUART_1
// LPUART1
{.typeMask = kPeripheralType_UART,
.instance = 1,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_lpuartControlInterface,
.byteInterface = &g_lpuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPUART_1
#if BL_CONFIG_LPUART_2
// LPUART2
{.typeMask = kPeripheralType_UART,
.instance = 2,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_lpuartControlInterface,
.byteInterface = &g_lpuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPUART_1
#if BL_CONFIG_LPI2C_0
// LPI2C0
{.typeMask = kPeripheralType_I2CSlave,
.instance = 0,
.pinmuxConfig = i2c_pinmux_config,
.controlInterface = &g_lpi2cControlInterface,
.byteInterface = &g_lpi2cByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPI2C_0
#if BL_CONFIG_LPI2C_1
// LPI2C1
{.typeMask = kPeripheralType_I2CSlave,
.instance = 1,
.pinmuxConfig = i2c_pinmux_config,
.controlInterface = &g_lpi2cControlInterface,
.byteInterface = &g_lpi2cByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPI2C_1
#if BL_CONFIG_LPI2C_2
// LPI2C2
{.typeMask = kPeripheralType_I2CSlave,
.instance = 2,
.pinmuxConfig = i2c_pinmux_config,
.controlInterface = &g_lpi2cControlInterface,
.byteInterface = &g_lpi2cByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPI2C_2
#if BL_CONFIG_LPSPI_0
// LPSPI0
{.typeMask = kPeripheralType_SPISlave,
.instance = 0,
.pinmuxConfig = spi_pinmux_config,
.controlInterface = &g_lpspiControlInterface,
.byteInterface = &g_lpspiByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPSPI_0
#if BL_CONFIG_LPSPI_1
// LPSPI1
{.typeMask = kPeripheralType_SPISlave,
.instance = 1,
.pinmuxConfig = spi_pinmux_config,
.controlInterface = &g_lpspiControlInterface,
.byteInterface = &g_lpspiByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPSPI_1
#if BL_CONFIG_LPSPI_2
// LPSPI2
{.typeMask = kPeripheralType_SPISlave,
.instance = 2,
.pinmuxConfig = spi_pinmux_config,
.controlInterface = &g_lpspiControlInterface,
.byteInterface = &g_lpspiByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // BL_CONFIG_LPSPI_2
#if (BL_CONFIG_USB_HID || BL_CONFIG_USB_MSC)
// usbhid
{.typeMask = kPeripheralType_USB_HID,
.instance = 0,
.pinmuxConfig = NULL,
.controlInterface = &g_usbHidControlInterface,
.byteInterface = NULL,
.packetInterface = &g_usbHidPacketInterface },
#endif // BL_CONFIG_USB_HID
{ 0 } // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! peripheral enable configurations
#define BL_ENABLE_PINMUX_UART0 (BL_CONFIG_LPUART_0)
#define BL_ENABLE_PINMUX_UART1 (BL_CONFIG_LPUART_1)
#define BL_ENABLE_PINMUX_UART2 (BL_CONFIG_LPUART_2)
#define BL_ENABLE_PINMUX_SPI0 (BL_CONFIG_LPSPI_0)
#define BL_ENABLE_PINMUX_SPI1 (BL_CONFIG_LPSPI_1)
#define BL_ENABLE_PINMUX_SPI2 (BL_CONFIG_LPSPI_2)
#define BL_ENABLE_PINMUX_I2C0 (BL_CONFIG_LPI2C_0)
#define BL_ENABLE_PINMUX_I2C1 (BL_CONFIG_LPI2C_1)
#define BL_ENABLE_PINMUX_I2C2 (BL_CONFIG_LPI2C_2)
//! UART pinmux configurations
#if TOWER
#define UART0_RX_PORT_BASE PORTA
#define UART0_RX_GPIO_BASE GPIOA
#define UART0_RX_GPIO_PIN_NUM 1 // PTA1
#define UART0_RX_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for UART0 RX functionality
#define UART0_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO functionality
#define UART0_RX_GPIO_IRQn PORTA_IRQn
#define UART0_RX_GPIO_IRQHandler PORTA_IRQHandler
#define UART0_TX_PORT_BASE PORTA
#define UART0_TX_GPIO_PIN_NUM 2 // PTA2
#define UART0_TX_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for UART0 TX functionality
#else
#define UART0_RX_PORT_BASE PORTB
#define UART0_RX_GPIO_BASE GPIOB
#define UART0_RX_GPIO_PIN_NUM 16 // PTB16
#define UART0_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART0 RX functionality
#define UART0_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO functionality
#define UART0_RX_GPIO_IRQn PORTB_IRQn
#define UART0_RX_GPIO_IRQHandler PORTB_IRQHandler
#define UART0_TX_PORT_BASE PORTB
#define UART0_TX_GPIO_PIN_NUM 17 // PTB17
#define UART0_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART0 TX functionality
#endif // TOWER
#define UART1_RX_PORT_BASE PORTC
#define UART1_RX_GPIO_BASE GPIOC
#define UART1_RX_GPIO_PIN_NUM 3 // PIN 3 in the PTC group
#define UART1_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 RX functionality for pin 3
#define UART1_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO functionality for pin 3
#define UART1_RX_GPIO_IRQn PORTC_IRQn
#define UART1_RX_GPIO_IRQHandler PORTC_IRQHandler
#define UART1_TX_PORT_BASE PORTC
#define UART1_TX_GPIO_PIN_NUM 4 // PIN 4 in the PTC group
#define UART1_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 TX functionality for pin 4
#define UART2_RX_PORT_BASE PORTD
#define UART2_RX_GPIO_BASE GPIOD
#define UART2_RX_GPIO_PIN_NUM 2 // PIN 2 in the PTD group
#define UART2_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART2 RX functionality for pin 2
#define UART2_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO functionality for pin 2
#define UART2_RX_GPIO_IRQn PORTD_IRQn
#define UART2_RX_GPIO_IRQHandler PORTD_IRQHandler
#define UART2_TX_PORT_BASE PORTD
#define UART2_TX_GPIO_PIN_NUM 3 // PIN 3 in the PTD group
#define UART2_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART2 TX functionality for pin 3
//! I2C pinmux configurations
#define I2C0_SCL_PORT_BASE PORTE
#define I2C0_SCL_GPIO_PIN_NUM 24 // PIN 24 in the PTE group
#define I2C0_SCL_FUNC_ALT_MODE kPORT_MuxAlt5 // ALT mode for I2C0 SCL functionality for pin 24
#define I2C0_SDA_PORT_BASE PORTE
#define I2C0_SDA_GPIO_PIN_NUM 25 // PIN 25 in the PTE group
#define I2C0_SDA_FUNC_ALT_MODE kPORT_MuxAlt5 // ALT mode for I2C0 SDA functionality for pin 25
#if FREEDOM
#define I2C1_SCL_PORT_BASE PORTC
#define I2C1_SCL_GPIO_PIN_NUM 1 // PTC1
#define I2C1_SCL_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C1 SCL functionality
#define I2C1_SDA_PORT_BASE PORTC
#define I2C1_SDA_GPIO_PIN_NUM 2 // PTC2
#define I2C1_SDA_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C1 SDA functionality
#else
#define I2C1_SCL_PORT_BASE PORTE
#define I2C1_SCL_GPIO_PIN_NUM 1 // PIN 1 in the PTE group
#define I2C1_SCL_FUNC_ALT_MODE kPORT_MuxAlt6 // ALT mode for I2C1 SCL functionality for pin 1
#define I2C1_SDA_PORT_BASE PORTE
#define I2C1_SDA_GPIO_PIN_NUM 0 // PIN 0 in the PTE group
#define I2C1_SDA_FUNC_ALT_MODE kPORT_MuxAlt6 // ALT mode for I2C1 SDA functionality for pin 0
#endif // FREEDOM
#define I2C2_SCL_PORT_BASE PORTA
#define I2C2_SCL_GPIO_PIN_NUM 12 // PIN 12 in the PTA group
#define I2C2_SCL_FUNC_ALT_MODE kPORT_MuxAlt5 // ALT mode for I2C2 SCL functionality for pin 12
#define I2C2_SDA_PORT_BASE PORTA
#define I2C2_SDA_GPIO_PIN_NUM 11 // PIN 11 in the PTA group
#define I2C2_SDA_FUNC_ALT_MODE kPORT_MuxAlt5 // ALT mode for I2C2 SDA functionality for pin 11
//! SPI pinmux configurations
#define SPI0_SELECTED_PCS 0
#define SPI0_PCS_PORT_BASE PORTA
#define SPI0_PCS_GPIO_PIN_NUM 14 // PIN 14 in the PTA group
#define SPI0_PCS_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI0 PCS functionality for pin 14
#define SPI0_SCK_PORT_BASE PORTA
#define SPI0_SCK_GPIO_PIN_NUM 15 // PIN 15 in the PTA group
#define SPI0_SCK_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI0 SCK functionality for pin 15
#define SPI0_SOUT_PORT_BASE PORTA
#define SPI0_SOUT_GPIO_PIN_NUM 16 // PIN 16 in the PTA group
#define SPI0_SOUT_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI0 SOUT functionality for pin 16
#define SPI0_SIN_PORT_BASE PORTA
#define SPI0_SIN_GPIO_PIN_NUM 17 // PIN 17 in the PTA group
#define SPI0_SIN_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI0 SIN functionality for pin 17
#define SPI1_SELECTED_PCS 0
#define SPI1_PCS_PORT_BASE PORTD
#define SPI1_PCS_GPIO_PIN_NUM 4 // PIN 4 in the PTD group
#define SPI1_PCS_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 PCS functionality for pin 4
#define SPI1_SCK_PORT_BASE PORTD
#define SPI1_SCK_GPIO_PIN_NUM 5 // PIN 5 in the PTD group
#define SPI1_SCK_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SCK functionality for pin 5
#define SPI1_SOUT_PORT_BASE PORTD
#define SPI1_SOUT_GPIO_PIN_NUM 6 // PIN 6 in the PTD group
#define SPI1_SOUT_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SOUT functionality for pin 6
#define SPI1_SIN_PORT_BASE PORTD
#define SPI1_SIN_GPIO_PIN_NUM 7 // PIN 7 in the PTD group
#define SPI1_SIN_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SIN functionality for pin 7
#define SPI2_SELECTED_PCS 0
#define SPI2_PCS_PORT_BASE PORTB
#define SPI2_PCS_GPIO_PIN_NUM 20 // PIN 20 in the PTB group
#define SPI2_PCS_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI2 PCS functionality for pin 20
#define SPI2_SCK_PORT_BASE PORTB
#define SPI2_SCK_GPIO_PIN_NUM 21 // PIN 21 in the PTB group
#define SPI2_SCK_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI2 SCK functionality for pin 21
#define SPI2_SOUT_PORT_BASE PORTB
#define SPI2_SOUT_GPIO_PIN_NUM 22 // PIN 22 in the PTB group
#define SPI2_SOUT_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI2 SOUT functionality for pin 22
#define SPI2_SIN_PORT_BASE PORTB
#define SPI2_SIN_GPIO_PIN_NUM 23 // PIN 23 in the PTB group
#define SPI2_SIN_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI2 SIN functionality for pin 23
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/* ---------------------------------------------------------------------------------------*/
/* @file: startup_MKL28Z7.s */
/* @purpose: CMSIS Cortex-M0P Core Device Startup File */
/* MKL28Z7 */
/* @version: 1.12 */
/* @date: 2015-6-3 */
/* @build: b150609 */
/* ---------------------------------------------------------------------------------------*/
/* */
/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without modification, */
/* are permitted provided that the following conditions are met: */
/* */
/* o Redistributions of source code must retain the above copyright notice, this list */
/* of conditions and the following disclaimer. */
/* */
/* o Redistributions in binary form must reproduce the above copyright notice, this */
/* list of conditions and the following disclaimer in the documentation and/or */
/* other materials provided with the distribution. */
/* */
/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
/* contributors may be used to endorse or promote products derived from this */
/* software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv6-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_04_IRQHandler /* DMA0 channel 0/4 transfer complete*/
.long DMA0_15_IRQHandler /* DMA0 channel 1/5 transfer complete*/
.long DMA0_26_IRQHandler /* DMA0 channel 2/6 transfer complete*/
.long DMA0_37_IRQHandler /* DMA0 channel 3/7 transfer complete*/
.long CTI0_DMA0_Error_IRQHandler /* CTI0 or DMA0 error*/
.long FLEXIO0_IRQHandler /* FLEXIO0*/
.long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
.long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
.long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
.long LPIT0_IRQHandler /* LPIT0 interrupt*/
.long LPSPI0_IRQHandler /* LPSPI0 single interrupt vector for all sources*/
.long LPSPI1_IRQHandler /* LPSPI1 single interrupt vector for all sources*/
.long LPUART0_IRQHandler /* LPUART0 status and error*/
.long LPUART1_IRQHandler /* LPUART1 status and error*/
.long LPI2C0_IRQHandler /* LPI2C0 interrupt*/
.long LPI2C1_IRQHandler /* LPI2C1 interrupt*/
.long Reserved32_IRQHandler /* Reserved interrupt*/
.long PORTA_IRQHandler /* PORTA Pin detect*/
.long PORTB_IRQHandler /* PORTB Pin detect*/
.long PORTC_IRQHandler /* PORTC Pin detect*/
.long PORTD_IRQHandler /* PORTD Pin detect*/
.long PORTE_IRQHandler /* PORTE Pin detect*/
.long LLWU0_IRQHandler /* Low leakage wakeup 0*/
.long I2S0_IRQHandler /* I2S0 interrupt*/
.long USB0_IRQHandler /* USB0 interrupt*/
.long ADC0_IRQHandler /* ADC0 interrupt*/
.long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
.long RTC_Seconds_IRQHandler /* RTC seconds*/
.long INTMUX0_0_IRQHandler /* INTMUX0 channel 0 interrupt*/
.long INTMUX0_1_IRQHandler /* INTMUX0 channel 1 interrupt*/
.long INTMUX0_2_IRQHandler /* INTMUX0 channel 2 interrupt*/
.long INTMUX0_3_IRQHandler /* INTMUX0 channel 3 interrupt*/
.long LPTMR1_IRQHandler /* LPTMR1 interrupt (INTMUX source IRQ0)*/
.long Reserved49_IRQHandler /* Reserved interrupt*/
.long Reserved50_IRQHandler /* Reserved interrupt*/
.long Reserved51_IRQHandler /* Reserved interrupt*/
.long LPSPI2_IRQHandler /* LPSPI2 single interrupt vector for all sources (INTMUX source IRQ4)*/
.long LPUART2_IRQHandler /* LPUART2 status and error (INTMUX source IRQ5)*/
.long EMVSIM0_IRQHandler /* EMVSIM0 interrupt (INTMUX source IRQ6)*/
.long LPI2C2_IRQHandler /* LPI2C2 interrupt (INTMUX source IRQ7)*/
.long TSI0_IRQHandler /* TSI0 interrupt (INTMUX source IRQ8)*/
.long PMC_IRQHandler /* PMC interrupt (INTMUX source IRQ9)*/
.long FTFA_IRQHandler /* FTFA interrupt (INTMUX source IRQ10)*/
.long SCG_IRQHandler /* SCG interrupt (INTMUX source IRQ11)*/
.long WDOG0_IRQHandler /* WDOG0 interrupt (INTMUX source IRQ12)*/
.long DAC0_IRQHandler /* DAC0 interrupt (INTMUX source IRQ13)*/
.long TRNG_IRQHandler /* TRNG interrupt (INTMUX source IRQ14)*/
.long RCM_IRQHandler /* RCM interrupt (INTMUX source IRQ15)*/
.long CMP0_IRQHandler /* CMP0 interrupt (INTMUX source IRQ16)*/
.long CMP1_IRQHandler /* CMP1 interrupt (INTMUX source IRQ17)*/
.long RTC_IRQHandler /* RTC Alarm interrupt (INTMUX source IRQ18)*/
.long Reserved67_IRQHandler /* Reserved interrupt*/
.long Reserved68_IRQHandler /* Reserved interrupt*/
.long Reserved69_IRQHandler /* Reserved interrupt*/
.long Reserved70_IRQHandler /* Reserved interrupt*/
.long Reserved71_IRQHandler /* Reserved interrupt*/
.long Reserved72_IRQHandler /* Reserved interrupt*/
.long Reserved73_IRQHandler /* Reserved interrupt*/
.long Reserved74_IRQHandler /* Reserved interrupt*/
.long Reserved75_IRQHandler /* Reserved interrupt*/
.long Reserved76_IRQHandler /* Reserved interrupt*/
.long Reserved77_IRQHandler /* Reserved interrupt*/
.long Reserved78_IRQHandler /* Reserved interrupt*/
.long Reserved79_IRQHandler /* Reserved interrupt*/
.long DefaultISR /* 80*/
.long DefaultISR /* 81*/
.long DefaultISR /* 82*/
.long DefaultISR /* 83*/
.long DefaultISR /* 84*/
.long DefaultISR /* 85*/
.long DefaultISR /* 86*/
.long DefaultISR /* 87*/
.long DefaultISR /* 88*/
.long DefaultISR /* 89*/
.long DefaultISR /* 90*/
.long DefaultISR /* 91*/
.long DefaultISR /* 92*/
.long DefaultISR /* 93*/
.long DefaultISR /* 94*/
.long DefaultISR /* 95*/
.long DefaultISR /* 96*/
.long DefaultISR /* 97*/
.long DefaultISR /* 98*/
.long DefaultISR /* 99*/
.long DefaultISR /* 100*/
.long DefaultISR /* 101*/
.long DefaultISR /* 102*/
.long DefaultISR /* 103*/
.long DefaultISR /* 104*/
.long DefaultISR /* 105*/
.long DefaultISR /* 106*/
.long DefaultISR /* 107*/
.long DefaultISR /* 108*/
.long DefaultISR /* 109*/
.long DefaultISR /* 110*/
.long DefaultISR /* 111*/
.long DefaultISR /* 112*/
.long DefaultISR /* 113*/
.long DefaultISR /* 114*/
.long DefaultISR /* 115*/
.long DefaultISR /* 116*/
.long DefaultISR /* 117*/
.long DefaultISR /* 118*/
.long DefaultISR /* 119*/
.long DefaultISR /* 120*/
.long DefaultISR /* 121*/
.long DefaultISR /* 122*/
.long DefaultISR /* 123*/
.long DefaultISR /* 124*/
.long DefaultISR /* 125*/
.long DefaultISR /* 126*/
.long DefaultISR /* 127*/
.long DefaultISR /* 128*/
.long DefaultISR /* 129*/
.long DefaultISR /* 130*/
.long DefaultISR /* 131*/
.long DefaultISR /* 132*/
.long DefaultISR /* 133*/
.long DefaultISR /* 134*/
.long DefaultISR /* 135*/
.long DefaultISR /* 136*/
.long DefaultISR /* 137*/
.long DefaultISR /* 138*/
.long DefaultISR /* 139*/
.long DefaultISR /* 140*/
.long DefaultISR /* 141*/
.long DefaultISR /* 142*/
.long DefaultISR /* 143*/
.long DefaultISR /* 144*/
.long DefaultISR /* 145*/
.long DefaultISR /* 146*/
.long DefaultISR /* 147*/
.long DefaultISR /* 148*/
.long DefaultISR /* 149*/
.long DefaultISR /* 150*/
.long DefaultISR /* 151*/
.long DefaultISR /* 152*/
.long DefaultISR /* 153*/
.long DefaultISR /* 154*/
.long DefaultISR /* 155*/
.long DefaultISR /* 156*/
.long DefaultISR /* 157*/
.long DefaultISR /* 158*/
.long DefaultISR /* 159*/
.long DefaultISR /* 160*/
.long DefaultISR /* 161*/
.long DefaultISR /* 162*/
.long DefaultISR /* 163*/
.long DefaultISR /* 164*/
.long DefaultISR /* 165*/
.long DefaultISR /* 166*/
.long DefaultISR /* 167*/
.long DefaultISR /* 168*/
.long DefaultISR /* 169*/
.long DefaultISR /* 170*/
.long DefaultISR /* 171*/
.long DefaultISR /* 172*/
.long DefaultISR /* 173*/
.long DefaultISR /* 174*/
.long DefaultISR /* 175*/
.long DefaultISR /* 176*/
.long DefaultISR /* 177*/
.long DefaultISR /* 178*/
.long DefaultISR /* 179*/
.long DefaultISR /* 180*/
.long DefaultISR /* 181*/
.long DefaultISR /* 182*/
.long DefaultISR /* 183*/
.long DefaultISR /* 184*/
.long DefaultISR /* 185*/
.long DefaultISR /* 186*/
.long DefaultISR /* 187*/
.long DefaultISR /* 188*/
.long DefaultISR /* 189*/
.long DefaultISR /* 190*/
.long DefaultISR /* 191*/
.long DefaultISR /* 192*/
.long DefaultISR /* 193*/
.long DefaultISR /* 194*/
.long DefaultISR /* 195*/
.long DefaultISR /* 196*/
.long DefaultISR /* 197*/
.long DefaultISR /* 198*/
.long DefaultISR /* 199*/
.long DefaultISR /* 200*/
.long DefaultISR /* 201*/
.long DefaultISR /* 202*/
.long DefaultISR /* 203*/
.long DefaultISR /* 204*/
.long DefaultISR /* 205*/
.long DefaultISR /* 206*/
.long DefaultISR /* 207*/
.long DefaultISR /* 208*/
.long DefaultISR /* 209*/
.long DefaultISR /* 210*/
.long DefaultISR /* 211*/
.long DefaultISR /* 212*/
.long DefaultISR /* 213*/
.long DefaultISR /* 214*/
.long DefaultISR /* 215*/
.long DefaultISR /* 216*/
.long DefaultISR /* 217*/
.long DefaultISR /* 218*/
.long DefaultISR /* 219*/
.long DefaultISR /* 220*/
.long DefaultISR /* 221*/
.long DefaultISR /* 222*/
.long DefaultISR /* 223*/
.long DefaultISR /* 224*/
.long DefaultISR /* 225*/
.long DefaultISR /* 226*/
.long DefaultISR /* 227*/
.long DefaultISR /* 228*/
.long DefaultISR /* 229*/
.long DefaultISR /* 230*/
.long DefaultISR /* 231*/
.long DefaultISR /* 232*/
.long DefaultISR /* 233*/
.long DefaultISR /* 234*/
.long DefaultISR /* 235*/
.long DefaultISR /* 236*/
.long DefaultISR /* 237*/
.long DefaultISR /* 238*/
.long DefaultISR /* 239*/
#ifdef BL_HAS_BOOTLOADER_CONFIG
//__bootloaderConfigurationArea ; 0x3c0
// .long 'kcfg' // [00:03] tag - Tag value used to validate the bootloader configuration data. Must be set to 'kcfg'
.long 0x6766636b
.long 0xFFFFFFFF // [04:07] crcStartAddress
.long 0xFFFFFFFF // [08:0b] crcByteCount
.long 0xFFFFFFFF // [0c:0f] crcExpectedValue
.byte 0xFF // [10:10] enabledPeripherals
.byte 0xFF // [11:11] i2cSlaveAddress
.short 5000 // [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code
.short 0xFFFF // [14:15] usbVid
.short 0xFFFF // [16:17] usbPid
.long 0xFFFFFFFF // [18:1b] usbStringsPointer
.byte 0xFF // [1c:1c] clockFlags - High Speed and other clock options
.byte 0xFF // [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1
.short 0xFFFF // [1e:1f] reserved
// Fill to align with flash configuration field.
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF // Reserved for user TRIM value
#else
//Fill to align with flash configuration field.
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF // Reserved for user TRIM value
#endif // BL_HAS_BOOTLOADER_CONFIG
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFF3DFE
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
bl init_data_bss
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
bl __START
#else
bl __libc_init_array
bl main
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
ldr r0, =DefaultISR
bx r0
.size DefaultISR, . - DefaultISR
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_04_IRQHandler
def_irq_handler DMA0_15_IRQHandler
def_irq_handler DMA0_26_IRQHandler
def_irq_handler DMA0_37_IRQHandler
def_irq_handler CTI0_DMA0_Error_IRQHandler
def_irq_handler FLEXIO0_IRQHandler
def_irq_handler TPM0_IRQHandler
def_irq_handler TPM1_IRQHandler
def_irq_handler TPM2_IRQHandler
def_irq_handler LPIT0_IRQHandler
def_irq_handler LPSPI0_IRQHandler
def_irq_handler LPSPI1_IRQHandler
def_irq_handler LPUART0_IRQHandler
def_irq_handler LPUART1_IRQHandler
def_irq_handler LPI2C0_IRQHandler
def_irq_handler LPI2C1_IRQHandler
def_irq_handler Reserved32_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler LLWU0_IRQHandler
def_irq_handler I2S0_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler INTMUX0_0_IRQHandler
def_irq_handler INTMUX0_1_IRQHandler
def_irq_handler INTMUX0_2_IRQHandler
def_irq_handler INTMUX0_3_IRQHandler
def_irq_handler LPTMR1_IRQHandler
def_irq_handler Reserved49_IRQHandler
def_irq_handler Reserved50_IRQHandler
def_irq_handler Reserved51_IRQHandler
def_irq_handler LPSPI2_IRQHandler
def_irq_handler LPUART2_IRQHandler
def_irq_handler EMVSIM0_IRQHandler
def_irq_handler LPI2C2_IRQHandler
def_irq_handler TSI0_IRQHandler
def_irq_handler PMC_IRQHandler
def_irq_handler FTFA_IRQHandler
def_irq_handler SCG_IRQHandler
def_irq_handler WDOG0_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler TRNG_IRQHandler
def_irq_handler RCM_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler CMP1_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler Reserved67_IRQHandler
def_irq_handler Reserved68_IRQHandler
def_irq_handler Reserved69_IRQHandler
def_irq_handler Reserved70_IRQHandler
def_irq_handler Reserved71_IRQHandler
def_irq_handler Reserved72_IRQHandler
def_irq_handler Reserved73_IRQHandler
def_irq_handler Reserved74_IRQHandler
def_irq_handler Reserved75_IRQHandler
def_irq_handler Reserved76_IRQHandler
def_irq_handler Reserved77_IRQHandler
def_irq_handler Reserved78_IRQHandler
def_irq_handler Reserved79_IRQHandler
.end

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targets/MKL28Z7/src/startup/iar/startup_MKL28Z7.s Normal file
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targets/MKL28Z7/src/startup/system_MKL28Z7.c Normal file
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/*
** ###################################################################
** Processors: MKL25Z128FM4
** MKL25Z128FT4
** MKL25Z128LH4
** MKL25Z128VLK4
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012
** Version: rev. 1.3, 2012-10-04
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2012 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-06-13)
** Initial version.
** - rev. 1.1 (2012-06-21)
** Update according to reference manual rev. 1.
** - rev. 1.2 (2012-08-01)
** Device type UARTLP changed to UART0.
** - rev. 1.3 (2012-10-04)
** Update according to reference manual rev. 3.
**
** ###################################################################
*/
/**
* @file MKL25Z4
* @version 1.3
* @date 2012-10-04
* @brief Device specific configuration file for MKL25Z4 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "system_MKL28Z7.h"
#include "fsl_device_registers.h"
#include "wdog32/fsl_wdog32.h"
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif // DISABLE_WDOG
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit(void)
{
#if (DISABLE_WDOG)
wdog32_config_t config;
WDOG32_GetDefaultConfig(&config);
config.enableWdog32 = false;
WDOG32_Init(WDOG0, &config);
#endif /* (DISABLE_WDOG) */
#if defined(BL_TARGET_ROM)
// Set Force ROM bits in RCM. We only set bit 2, so the RCM_MR register doesn't
// falsely show that the ROM was booted via boot pin assertion.
RCM_WR_FM_FORCEROM(RCM, 2);
#else
RCM->FM &= RCM_FM_FORCEROM_MASK;
#endif
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate(void)
{
}

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/*
** ###################################################################
** Processors: MKL02Z32CAF4
** MKL02Z32VFG4
** MKL02Z16VFG4
** MKL02Z8VFG4
** MKL02Z32VFK4
** MKL02Z16VFK4
** MKL02Z32VFM4
** MKL02Z16VFM4
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL02RM, Rev.2, Dec 2012
** Version: rev. 1.1, 2013-04-05
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-10-04)
** Initial version.
** - rev. 1.1 (2013-04-05)
** Changed start of doxygen comment.
**
** ###################################################################
*/
/*!
* @file MKL02Z4
* @version 1.1
* @date 2013-04-05
* @brief Device specific configuration file for MKL02Z4 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_MKL28Z7_H_
#define _SYSTEM_MKL28Z7_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(_SYSTEM_MKL28T7_H_) */

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__TARGET_CONFIG_H__)
#define __TARGET_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief Constants for clock frequencies.
enum _target_clocks
{
//! Frequency of the HIRC.
kHIRC = 48000000,
//! 8MHz low frequency IRC.
kLIRC8M = 8000000,
//! 2MHz low frequency IRC.
kLIRC2M = 2000000,
//! The core clock cannot go above 72MHz.
kMaxCoreClock = 72000000u,
//! The bus clock cannot go above 24MHz.
kMaxBusClock = 24000000,
kDivider_Min = 1,
kDivider_Max = 16,
};
//! @brief Constants for sram partition
enum
{
kSram_LowerPart = 1,
kSram_UpperPart = 3,
};
//! @brief Version constants for the target.
enum _target_version_constants
{
kTarget_Version_Name = 'T',
kTarget_Version_Major = 1,
kTarget_Version_Minor = 0,
kTarget_Version_Bugfix = 0
};
//! CRC check pinmux configurations
// Note: This default muxing slot of selected crc check failure pin must be ALT0
#define CRC_CHECK_FAILURE_PIN_NUMBER 6
#define CRC_CHECK_FAILURE_PIN_PORT PORTA
#define CRC_CHECK_FAILURE_PIN_GPIO GPIOA
#define CRC_CHECK_FAILURE_PIN_DEFAULT_MODE 0
#define CRC_CHECK_FAILURE_PIN_GPIO_MODE 1
#endif // __TARGET_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __USB_DEVICE_CONFIG_H__
#define __USB_DEVICE_CONFIG_H__ 1
#include "bootloader_common.h"
/*!
* @addtogroup usb_device_configuration
* @{
*/
/*!
* @name Hardware instance define
* @{
*/
/*! @brief KHCI instance count */
#define USB_DEVICE_CONFIG_KHCI (BL_CONFIG_USB_HID | BL_CONFIG_USB_MSC)
/*! @brief EHCI instance count */
#define USB_DEVICE_CONFIG_EHCI (0U)
/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/
#define USB_DEVICE_CONFIG_NUM (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI)
/* @} */
/*!
* @name class instance define
* @{
*/
/*! @brief HID instance count */
#define USB_DEVICE_CONFIG_HID (BL_CONFIG_USB_HID)
/*! @brief CDC ACM instance count */
#define USB_DEVICE_CONFIG_CDC_ACM (0U)
/*! @brief MSC instance count */
#define USB_DEVICE_CONFIG_MSC (BL_CONFIG_USB_MSC)
/*! @brief Audio instance count */
#define USB_DEVICE_CONFIG_AUDIO (0U)
/*! @brief PHDC instance count */
#define USB_DEVICE_CONFIG_PHDC (0U)
/*! @brief Video instance count */
#define USB_DEVICE_CONFIG_VIDEO (0U)
/*! @brief CCID instance count */
#define USB_DEVICE_CONFIG_CCID (0U)
/*! @brief Printer instance count */
#define USB_DEVICE_CONFIG_PRINTER (0U)
/*! @brief DFU instance count */
#define USB_DEVICE_CONFIG_DFU (0U)
/* @} */
/*! @brief Whether device is self power. 1 supported, 0 not supported */
#define USB_DEVICE_CONFIG_SELF_POWER (1U)
/*! @brief Whether device remote wakeup supported. 1 supported, 0 not supported */
#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
/*! @brief How many endpoints are supported in the stack. */
#define USB_DEVICE_CONFIG_ENDPOINTS (8U)
/*! @brief Whether the device task is enabled. */
#define USB_DEVICE_CONFIG_USE_TASK (0U)
/*! @brief How many the notification message are supported when the device task enabled. */
#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U)
#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
/*! @brief The MAX buffer length for the KHCI DMA workaround.*/
/* clang-format off */
#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U)
/*! @brief Whether handle the USB KHCI bus error. */
#define USB_DEVICE_CONFIG_KHCI_ERROR_HANDLING (0U)
/* clang-format on */
#endif
#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
/*! @brief How many the DTD are supported. */
/* clang-format off */
#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
/*! @brief Whether handle the USB EHCI bus error. */
#define USB_DEVICE_CONFIG_EHCI_ERROR_HANDLING (0U)
/*! @brief Whether test mode enabled. */
#define USB_DEVICE_CONFIG_EHCI_TEST_MODE (0U)
/*! @brief Whether the EHCI ID pin detect feature enabled. */
#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U)
/* clang-format on */
#endif
/*! @brief Whether the keep alive feature enabled. */
/* clang-format off */
#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U)
/*! @brief Whether the transfer buffer is cache-enabled or not. */
#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
/*! @brief Whether the low power mode is enabled or not. */
#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
/*! @brief Whether the device detached feature is enabled or not. */
#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
/* clang-format on */
/* @} */
#endif /* __USB_DEVICE_CONFIG_H__ */