Add KBOOT.
This commit is contained in:
László Monda
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<?xml version="1.0" encoding="iso-8859-1"?>
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<workspace>
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<batchBuild><batchDefinition><name>all</name><member><project>tower_bootloader</project><configuration>Debug</configuration></member><member><project>tower_bootloader</project><configuration>Release</configuration></member><member><project>freedom_bootloader</project><configuration>Debug</configuration></member><member><project>freedom_bootloader</project><configuration>Release</configuration></member></batchDefinition><batchDefinition><name>Debug</name><member><project>tower_bootloader</project><configuration>Debug</configuration></member><member><project>freedom_bootloader</project><configuration>Debug</configuration></member></batchDefinition><batchDefinition><name>Release</name><member><project>tower_bootloader</project><configuration>Release</configuration></member><member><project>freedom_bootloader</project><configuration>Release</configuration></member></batchDefinition></batchBuild>
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<project><path>$WS_DIR$/iar/tower_bootloader/tower_bootloader.ewp</path></project><project><path>$WS_DIR$/iar/freedom_bootloader/freedom_bootloader.ewp</path></project></workspace>
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File diff suppressed because one or more lines are too long
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off set tcp auto-retry on set tcp connect-timeout 30"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value="USB1"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="7224"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
|
||||
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|
||||
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/freedom_bootloader.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="freedom_bootloader"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1792027861"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
|
||||
<listEntry value="/freedom_bootloader"/></listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
@@ -0,0 +1,62 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
|
||||
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|
||||
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|
||||
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|
||||
<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
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||||
<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
|
||||
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|
||||
<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
|
||||
<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihostingIoclientTelnet" value="false"/>
|
||||
<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
|
||||
<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
|
||||
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|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSwo" value="true"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.firstResetSpeed" value="30"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.firstResetType" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off set tcp auto-retry on set tcp connect-timeout 30"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerConnection" value="usb"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerConnectionAddress" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDebugInterface" value="swd"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceEndianness" value="little"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceName" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceSpeed" value="30"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerExecutable" value="${jlink_path}/JLinkGDBServerCL"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerGdbPortNumber" value="7224"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerLog" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerOther" value="-s"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerSwoPortNumber" value="2332"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.interfaceSpeed" value="auto"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="-1"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherInitCommands" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="-1"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value="USB1"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.secondResetType" value=""/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetSwoFreq" value="0"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="127.0.0.1"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="7224"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release/freedom_bootloader.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="freedom_bootloader"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1792027861"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
|
||||
<listEntry value="/freedom_bootloader"/></listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<workspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="workingsets.xsd">
|
||||
<projects>
|
||||
</projects>
|
||||
<workingsets>
|
||||
</workingsets>
|
||||
<cdtconfigurations>
|
||||
</cdtconfigurations>
|
||||
</workspace>
|
||||
@@ -0,0 +1,200 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?>
|
||||
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
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|
||||
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|
||||
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|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1792027861" name="debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="" artifactExtension="elf">
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.2014665560" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
|
||||
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|
||||
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|
||||
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|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.670689833" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.654501139" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.967248865" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="false" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.1390211406" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="false" valueType="boolean"/>
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@@ -0,0 +1,62 @@
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@@ -0,0 +1,80 @@
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|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release/tower_bootloader.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="tower_bootloader"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1792027861"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
|
||||
<listEntry value="/tower_bootloader"/></listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"> <gdbmemoryBlockExpression address="0" label="0"/> </memoryBlockExpressionList> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
@@ -0,0 +1,199 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="KL25Z128M4"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_IP" value="127.0.0.1"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_PORT" value="7224"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="6"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.sda."/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_UP_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.STARTUP_USE_SWD" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_UP_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.STARTUP_USE_SWD" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doFirstReset" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateConsole" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerInitRegs" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerLocalOnly" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerSilent" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerVerifyDownload" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doSecondReset" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableFlashBreakpoints" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSwo" value="true"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.firstResetSpeed" value="30"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.firstResetType" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off set tcp auto-retry on set tcp connect-timeout 30"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerConnection" value="usb"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerConnectionAddress" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDebugInterface" value="swd"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceEndianness" value="little"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceName" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceSpeed" value="30"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerExecutable" value="${jlink_path}/JLinkGDBServerCL"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerGdbPortNumber" value="7224"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerLog" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerOther" value="-s"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerSwoPortNumber" value="2332"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.interfaceSpeed" value="auto"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="-1"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherInitCommands" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="-1"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value="USB1"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
|
||||
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|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
|
||||
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|
||||
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|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.secondResetType" value=""/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetSwoFreq" value="0"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="false"/>
|
||||
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
|
||||
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
|
||||
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="127.0.0.1"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="7224"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release/tower_bootloader.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="tower_bootloader"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1792027861"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
|
||||
<listEntry value="/tower_bootloader"/></listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<workspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="workingsets.xsd">
|
||||
<projects>
|
||||
</projects>
|
||||
<workingsets>
|
||||
</workingsets>
|
||||
<cdtconfigurations>
|
||||
</cdtconfigurations>
|
||||
</workspace>
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
<WorkspaceName>WorkSpace</WorkspaceName>
|
||||
<project><PathAndName>freedom_bootloader.uvprojx</PathAndName><NodeIsActive>1</NodeIsActive></project></ProjectWorkspace>
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,31 @@
|
||||
[STARTUP]
|
||||
CPUTARGETTYPENAME=KL25Z128M4
|
||||
USE_CYCLONEPRO_RELAYS=0
|
||||
CYCLONEPRO_POWEROFFONEXIT=0
|
||||
CYCLONEPRO_CURRENTVOLTAGE=128
|
||||
CYCLONEPRO_POWERDOWNDELAY=250
|
||||
CYCLONEPRO_POWERUPDELAY=250
|
||||
MULTILINK_POWERDOWNDELAY=250
|
||||
MULTILINK_POWERUPDELAY=1000
|
||||
USE_SWD=1
|
||||
IO_DELAY_CNT=0
|
||||
FREQ_FX=4
|
||||
FREQ_NORMAL=0
|
||||
FREQ_OSJTAG=0
|
||||
FREQ_CYCLONE=3
|
||||
FREQ_TRACELINK=3
|
||||
FREQ_LIGHTNING=1
|
||||
FREQ_OPENSDA=0
|
||||
RESET_DELAY=0
|
||||
PORT=
|
||||
PORT_NAME_STRING=
|
||||
INTERFACE_SELECTION=7
|
||||
SHOWDIALOG=0
|
||||
|
||||
[PEDEBUG]
|
||||
ERASE_PROGRAM_WITHOUT_ASKING=1
|
||||
CURRENTDEVICE=KL25Z128M4
|
||||
|
||||
[DEVICE]
|
||||
CHIPMODE=KL25Z128M4
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
[STARTUP]
|
||||
CPUTARGETTYPENAME=KL25Z128M4
|
||||
USE_CYCLONEPRO_RELAYS=0
|
||||
CYCLONEPRO_POWEROFFONEXIT=0
|
||||
CYCLONEPRO_CURRENTVOLTAGE=128
|
||||
CYCLONEPRO_POWERDOWNDELAY=250
|
||||
CYCLONEPRO_POWERUPDELAY=250
|
||||
MULTILINK_POWERDOWNDELAY=250
|
||||
MULTILINK_POWERUPDELAY=1000
|
||||
USE_SWD=1
|
||||
IO_DELAY_CNT=0
|
||||
FREQ_FX=4
|
||||
FREQ_NORMAL=0
|
||||
FREQ_OSJTAG=0
|
||||
FREQ_CYCLONE=3
|
||||
FREQ_TRACELINK=3
|
||||
FREQ_LIGHTNING=1
|
||||
FREQ_OPENSDA=0
|
||||
RESET_DELAY=0
|
||||
PORT=
|
||||
PORT_NAME_STRING=
|
||||
INTERFACE_SELECTION=7
|
||||
SHOWDIALOG=0
|
||||
|
||||
[PEDEBUG]
|
||||
ERASE_PROGRAM_WITHOUT_ASKING=1
|
||||
CURRENTDEVICE=KL25Z128M4
|
||||
|
||||
[DEVICE]
|
||||
CHIPMODE=KL25Z128M4
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
<WorkspaceName>WorkSpace</WorkspaceName>
|
||||
<project><PathAndName>tower_bootloader.uvprojx</PathAndName><NodeIsActive>1</NodeIsActive></project></ProjectWorkspace>
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,136 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef __BOOTLOADER_CONFIG_H__
|
||||
#define __BOOTLOADER_CONFIG_H__
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// Bootloader configuration options
|
||||
//
|
||||
|
||||
//! @name Peripheral configuration macros
|
||||
//@{
|
||||
|
||||
#if !defined(BL_CONFIG_UART)
|
||||
#define BL_CONFIG_UART (1)
|
||||
#endif
|
||||
#if !defined(BL_CONFIG_I2C)
|
||||
#define BL_CONFIG_I2C (1)
|
||||
#endif
|
||||
#if !defined(BL_CONFIG_SPI)
|
||||
#define BL_CONFIG_SPI (1)
|
||||
#endif
|
||||
#if !defined(BL_CONFIG_USB_HID)
|
||||
#define BL_CONFIG_USB_HID (1)
|
||||
#endif
|
||||
#if !defined(BL_CONFIG_USB_MSC)
|
||||
#define BL_CONFIG_USB_MSC (1)
|
||||
#endif
|
||||
|
||||
//@}
|
||||
|
||||
#if !defined(BL_TARGET_FLASH)
|
||||
#define BL_TARGET_FLASH (1)
|
||||
#endif
|
||||
|
||||
#if defined(BL_TARGET_RAM)
|
||||
#define BL_FEATURE_FLASH_SECURITY (0)
|
||||
#else
|
||||
#define BL_FEATURE_FLASH_SECURITY (1)
|
||||
#endif
|
||||
|
||||
#if !defined(BL_FEATURE_MIN_PROFILE)
|
||||
#define BL_FEATURE_MIN_PROFILE (0)
|
||||
#endif
|
||||
|
||||
#define BL_FEATURE_ERASEALL_UNSECURE (0)
|
||||
|
||||
#define BL_FEATURE_FLASH_VERIFY_DISABLE (0)
|
||||
|
||||
#define BL_FEATURE_CRC_CHECK (0)
|
||||
|
||||
#define BL_FEATURE_UART_AUTOBAUD_IRQ (1)
|
||||
|
||||
#define BL_FEATURE_QSPI_MODULE (0)
|
||||
|
||||
#define BL_FEATURE_ENCRYPTION (0)
|
||||
|
||||
#define BL_FEATURE_BYPASS_WATCHDOG (0)
|
||||
|
||||
// Bootloader peripheral detection default timeout in milliseconds
|
||||
// After coming out of reset the bootloader will spin in a peripheral detection
|
||||
// loop for this amount of time. A zero value means no time out.
|
||||
#if DEBUG
|
||||
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 0
|
||||
#else
|
||||
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 5000
|
||||
#endif // DEBUG
|
||||
|
||||
// The bootloader will check this address for the application vector table upon startup.
|
||||
#if !defined(BL_APP_VECTOR_TABLE_ADDRESS)
|
||||
#define BL_APP_VECTOR_TABLE_ADDRESS 0x8000
|
||||
#endif
|
||||
|
||||
// The bootloader will calculate the start address and end address of RAM based on following definitions.
|
||||
#define RAM_LOWER_PART (1)
|
||||
#define RAM_UPPER_PART (3)
|
||||
|
||||
/* Serial Port Info */
|
||||
|
||||
/**************************************************************************
|
||||
* Note:
|
||||
*
|
||||
* Because of the changes to the UART modules, we can no longer define
|
||||
* the TERM_PORT as a base pointer. The uart functions have been modified
|
||||
* accommodate this change. Now, TERM_PORT_NUM must be defined as the
|
||||
* number of the UART port desired to use
|
||||
*
|
||||
* TERM_PORT_NUM = 0 -- This allows you to use UART0; default pins are
|
||||
* PTA14 and PTA15
|
||||
*
|
||||
* TERM_PORT_NUM = 1 -- This allows you to use UART1; default pins are
|
||||
* PTC3 and PTC4
|
||||
*
|
||||
* TERM_PORT_NUM = 2 -- This allows you to use UART2; default pins are
|
||||
* PTD2 and PTD3
|
||||
*
|
||||
*************************************************************************/
|
||||
#define TERM_PORT_NUM 0
|
||||
|
||||
#define TERMINAL_BAUD 19200
|
||||
#undef HW_FLOW_CONTROL
|
||||
|
||||
#endif // __BOOTLOADER_CONFIG_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,258 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "bootloader_common.h"
|
||||
#include "bootloader/bl_context.h"
|
||||
#include "property/property.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "utilities/fsl_assert.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Clock mode types
|
||||
typedef enum _target_clock_mode
|
||||
{
|
||||
kClockMode_FEI = 0,
|
||||
kClockMode_FEE = 1,
|
||||
kClockMode_FBI = 2,
|
||||
kClockMode_FBE = 3,
|
||||
kClockMode_PEE = 4,
|
||||
kClockMode_PBE = 5,
|
||||
kClockMode_Default = kClockMode_FEI,
|
||||
} target_clock_mode_t;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Prototypes
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// This function implements clock mode switch between FEI and PEE mode used in this bootloader
|
||||
void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Code
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// See bootloader_common.h for documentation on this function.
|
||||
void configure_clocks(bootloader_clock_option_t option)
|
||||
{
|
||||
#if BL_TARGET_FLASH
|
||||
static uint32_t s_defaultClockDivider;
|
||||
static target_clock_mode_t s_currentClockMode = kClockMode_FEI;
|
||||
|
||||
if (option == kClockOption_EnterBootloader)
|
||||
{
|
||||
s_defaultClockDivider = SIM->CLKDIV1;
|
||||
|
||||
// General procedure to be implemented:
|
||||
// 1. Read clock flags and divider from bootloader config in property store
|
||||
bootloader_configuration_data_t *config = &g_bootloaderContext.propertyInterface->store->configurationData;
|
||||
uint8_t options = config->clockFlags;
|
||||
|
||||
// Check if the USB HID peripheral is enabled. If it is enabled, we always
|
||||
// use the external OSC.
|
||||
bool isUsbEnabled = config->enabledPeripherals & kPeripheralType_USB_HID;
|
||||
|
||||
// 2. If NOT High Speed and USB is NOT enabled, do nothing (use reset clock config)
|
||||
if ((options & kClockFlag_HighSpeed) && !isUsbEnabled)
|
||||
{
|
||||
// High speed flag is set (meaning disabled), so just use default clocks.
|
||||
uint32_t coreClockDivider = (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1);
|
||||
SystemCoreClock = kDefaultMcgOutWithoutUsb / coreClockDivider;
|
||||
SIM->SOPT2 &=
|
||||
(uint32_t)~SIM_SOPT2_PLLFLLSEL_MASK; // USe the FLL clock for various peripheral clocking options.
|
||||
return;
|
||||
}
|
||||
|
||||
// 3. Set OUTDIV1 based on divider in config. OUTDIV4 starts out at /1.
|
||||
// The divider values are masked by the maximum bits per divider.
|
||||
uint32_t div1 = ((~config->clockDivider) & (SIM_CLKDIV1_OUTDIV1_MASK >> SIM_CLKDIV1_OUTDIV1_SHIFT)) + 1;
|
||||
uint32_t div4 = 1;
|
||||
|
||||
// 4. Calculate MCGOUTCLK
|
||||
uint32_t McgOutClk = kDefaultMcgOutkWithUsb;
|
||||
|
||||
// 5. Keep core clock up kMinCoreClockWithUsbSupport if usb is supported.
|
||||
uint32_t freq = McgOutClk;
|
||||
// If USB is enabled, the CPU clock must not be allowed to go below 20 MHz
|
||||
if (isUsbEnabled)
|
||||
{
|
||||
while ((freq / div1) < kMinCoreClockWithUsbSupport)
|
||||
{
|
||||
--div1;
|
||||
}
|
||||
}
|
||||
|
||||
// 6. Keep core clock <= Max supported core clock
|
||||
while ((freq / div1) > kMaxCoreClock)
|
||||
{
|
||||
++div1;
|
||||
}
|
||||
|
||||
// 7. Update SystemCoreClock global.
|
||||
assert((div1 >= kDivider1_Min) && (div1 <= kDivider1_Max));
|
||||
SystemCoreClock = McgOutClk / div1;
|
||||
|
||||
// 8. Keep bus freq below max.
|
||||
//
|
||||
// The bus clock is divided by OUTDIV4 in addition to OUTDIV1:
|
||||
// MCGOUTCLK -> OUTDIV1 -> OUTDIV4 -> bus_clk
|
||||
freq = SystemCoreClock;
|
||||
while ((freq / div4) > kMaxBusClock)
|
||||
{
|
||||
// Increase bus/flash clock divider.
|
||||
++div4;
|
||||
}
|
||||
assert((div4 >= kDivider4_Min) && (div4 <= kDivider4_Max));
|
||||
|
||||
// 9. Now set the dividers
|
||||
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(div1 - 1) | SIM_CLKDIV1_OUTDIV4(div4 - 1); /* Update system prescalers */
|
||||
|
||||
// Switch to PEE mode
|
||||
clock_mode_switch(s_currentClockMode, kClockMode_PEE);
|
||||
|
||||
s_currentClockMode = kClockMode_PEE;
|
||||
}
|
||||
else if (option == kClockOption_ExitBootloader)
|
||||
{
|
||||
// Restore from PEE mode to FEI mode
|
||||
clock_mode_switch(s_currentClockMode, kClockMode_FEI);
|
||||
|
||||
// Restore clock divider
|
||||
SIM->CLKDIV1 = s_defaultClockDivider;
|
||||
}
|
||||
|
||||
#endif // BL_TARGET_FLASH
|
||||
}
|
||||
|
||||
void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode)
|
||||
{
|
||||
// Note: here only implements clock switch between FEI and PEE,
|
||||
// The other modes are not supported.
|
||||
assert(currentMode == kClockMode_PEE || currentMode == kClockMode_FEI);
|
||||
assert(expectedMode == kClockMode_PEE || expectedMode == kClockMode_FEI);
|
||||
|
||||
if (currentMode == expectedMode)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (expectedMode == kClockMode_PEE)
|
||||
{
|
||||
/* SIM->SCGC5: PORTA=1 */
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
|
||||
/* PORTA->PCR18: ISF=0,MUX=0 */
|
||||
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
|
||||
/* PORTA->PCR19: ISF=0,MUX=0 */
|
||||
PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
|
||||
OSC0->CR = (uint8_t)0x89U;
|
||||
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x24U;
|
||||
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x9AU;
|
||||
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
||||
MCG->C4 &= (uint8_t) ~(uint8_t)0xE0U;
|
||||
/* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||
MCG->C5 = (uint8_t)0x01U;
|
||||
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x00U;
|
||||
while ((MCG->S & MCG_S_IREFST_MASK) != 0x00U)
|
||||
{ /* Check that the source of the FLL reference clock is the external reference clock. */
|
||||
}
|
||||
while ((MCG->S & 0x0CU) != 0x08U)
|
||||
{ /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
/* Switch to PBE Mode */
|
||||
/* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x40U;
|
||||
while ((MCG->S & 0x0CU) != 0x08U)
|
||||
{ /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
while ((MCG->S & MCG_S_LOCK0_MASK) == 0x00U)
|
||||
{ /* Wait until locked */
|
||||
}
|
||||
/* Switch to PEE Mode */
|
||||
/* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x1AU;
|
||||
while ((MCG->S & 0x0CU) != 0x0CU)
|
||||
{ /* Wait until output of the PLL is selected */
|
||||
}
|
||||
}
|
||||
else if (expectedMode == kClockMode_FEI)
|
||||
{
|
||||
/* Switch to PBE mode */
|
||||
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x9AU;
|
||||
/* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x40U;
|
||||
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x24U;
|
||||
while ((MCG->S & 0x0CU) != 0x08U) /* Wait until external reference clock is selected */
|
||||
{
|
||||
}
|
||||
|
||||
/* Switch to FBE mode */
|
||||
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x00U;
|
||||
|
||||
while ((MCG->S & MCG_S_PLLST_MASK) != 0x00U) /* Wait until source of PLLS clock is FLL clock */
|
||||
{
|
||||
}
|
||||
|
||||
/* Switch to FEI mode */
|
||||
/* MCG->C1: CLKS=0,FRDIV=3,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x1EU;
|
||||
while ((MCG->S & MCG_S_IREFST_MASK) == 0x0U)
|
||||
{
|
||||
}
|
||||
|
||||
while ((MCG->S & 0x0CU) != 0x00U) /* Wait until output of FLL is selected */
|
||||
{
|
||||
}
|
||||
|
||||
OSC0->CR = (uint8_t)0x0U;
|
||||
while ((MCG->S & MCG_S_OSCINIT0_MASK) != 0x00U) /* Wait until OSC is off */
|
||||
{
|
||||
}
|
||||
|
||||
/* Restore Registers */
|
||||
/* MCG->C2: LOCRE0=1,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x80U;
|
||||
MCG->C1 = (uint8_t)0x04U;
|
||||
MCG->C5 = (uint8_t)0x00U;
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,213 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "bootloader_common.h"
|
||||
#include "bootloader/bl_context.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "uart/fsl_uart.h"
|
||||
#include "drivers/systick/systick.h"
|
||||
#include "drivers/watchdog/fsl_watchdog.h"
|
||||
#include "utilities/fsl_rtos_abstraction.h"
|
||||
#include "smc/smc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define BOOT_PIN_NUMBER 3
|
||||
#define BOOT_PIN_PORT PORTC
|
||||
#define BOOT_PIN_GPIO GPIOC
|
||||
#define BOOT_PIN_ALT_MODE 1
|
||||
#define BOOT_PIN_DEBOUNCE_READ_COUNT 500
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Variables
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Code
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void init_hardware(void)
|
||||
{
|
||||
exit_vlpr();
|
||||
|
||||
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
|
||||
SIM_SCGC5_PORTE_MASK);
|
||||
|
||||
SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_MASK // set PLLFLLSEL to select the PLL for this clock source
|
||||
| SIM_SOPT2_UART0SRC(1); // select the PLLFLLCLK as UART0 clock source
|
||||
|
||||
#if DEBUG
|
||||
// Enable the pins for the debug UART1
|
||||
PORTC->PCR[3] = PORT_PCR_MUX(3); // UART1_RX is PTC3 in ALT3
|
||||
PORTC->PCR[4] = PORT_PCR_MUX(3); // UART1_TX is PTC4 in ALT3
|
||||
#endif
|
||||
}
|
||||
|
||||
void deinit_hardware(void)
|
||||
{
|
||||
SIM->SCGC5 &= (uint32_t) ~(SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |
|
||||
SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
|
||||
|
||||
// Restore SIM_SOPTx related bits being changed
|
||||
SIM->SOPT1 &= (uint32_t) ~(SIM_SOPT1_USBREGEN_MASK);
|
||||
SIM->SOPT2 &= (uint32_t) ~(SIM_SOPT2_UART0SRC_MASK | SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
|
||||
}
|
||||
|
||||
uint32_t get_bus_clock(void)
|
||||
{
|
||||
uint32_t busClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1;
|
||||
return SystemCoreClock / busClockDivider;
|
||||
}
|
||||
|
||||
// Keep this function here to ensure compatibility, all usb related configuration
|
||||
// is maintained by usb stack itself.
|
||||
bool usb_clock_init(void)
|
||||
{
|
||||
SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
|
||||
SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
|
||||
|
||||
SIM->SOPT1CFG |= SIM_SOPT1CFG_URWE_MASK;
|
||||
SIM->SOPT1 |= SIM_SOPT1_USBREGEN_MASK;
|
||||
/* reset USB CTRL register */
|
||||
USB0->USBCTRL = 0;
|
||||
|
||||
/* Enable internal pull-up resistor */
|
||||
USB0->CONTROL = USB_CONTROL_DPPULLUPNONOTG_MASK;
|
||||
USB0->USBTRC0 |= 0x40; /* Software must set this bit to 1 */
|
||||
return true;
|
||||
}
|
||||
|
||||
uint32_t get_uart_clock(uint32_t instance)
|
||||
{
|
||||
switch (instance)
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
uint32_t coreClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1;
|
||||
uint32_t McgOutClk = SystemCoreClock * coreClockDivider;
|
||||
|
||||
// if PLL/2 is the UART0 clock
|
||||
if (MCG->S & MCG_S_PLLST_MASK)
|
||||
{
|
||||
return McgOutClk / 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return McgOutClk;
|
||||
}
|
||||
}
|
||||
case 1:
|
||||
{
|
||||
// UART1 always uses the system clock / OUTDIV4
|
||||
const uint32_t busClockDivider =
|
||||
((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1;
|
||||
return (SystemCoreClock / busClockDivider);
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
// UART2 always uses the system clock / OUTDIV4
|
||||
uint32_t busClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1;
|
||||
return (SystemCoreClock / busClockDivider);
|
||||
}
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
bool is_boot_pin_asserted(void)
|
||||
{
|
||||
#if defined(BL_TARGET_FLASH) & !defined(FREEDOM)
|
||||
// Initialize boot pin for GPIO
|
||||
BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= PORT_PCR_MUX(BOOT_PIN_ALT_MODE);
|
||||
|
||||
// Set boot pin as an input
|
||||
BOOT_PIN_GPIO->PDDR &= (uint32_t) ~(1 << BOOT_PIN_NUMBER);
|
||||
// Set boot pin pullup enabled, pullup select, filter enable
|
||||
BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_PFE_MASK);
|
||||
|
||||
uint32_t readCount = 0;
|
||||
|
||||
// Sample the pin a number of times
|
||||
for (uint32_t i = 0; i < BOOT_PIN_DEBOUNCE_READ_COUNT; i++)
|
||||
{
|
||||
readCount += ((BOOT_PIN_GPIO->PDIR) >> BOOT_PIN_NUMBER) & 1;
|
||||
}
|
||||
|
||||
// boot pin is pulled high so we are measuring lows, make sure most of our measurements
|
||||
// registered as low
|
||||
return (readCount < (BOOT_PIN_DEBOUNCE_READ_COUNT / 2));
|
||||
#else
|
||||
// Boot pin for Flash only target
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
void dummy_byte_callback(uint8_t byte)
|
||||
{
|
||||
(void)byte;
|
||||
}
|
||||
|
||||
void update_available_peripherals()
|
||||
{
|
||||
}
|
||||
|
||||
// @brief Initialize watchdog
|
||||
void bootloader_watchdog_init(void)
|
||||
{
|
||||
systick_init(SystemCoreClock / 64);
|
||||
systick_set_hook(bootloader_watchdog_service);
|
||||
}
|
||||
|
||||
void bootloader_watchdog_service(void)
|
||||
{
|
||||
lock_acquire();
|
||||
fsl_watchdog_service();
|
||||
lock_release();
|
||||
}
|
||||
|
||||
void bootloader_watchdog_deinit(void)
|
||||
{
|
||||
systick_shutdown();
|
||||
}
|
||||
|
||||
#if __ICCARM__
|
||||
|
||||
size_t __write(int handle, const unsigned char *buf, size_t size)
|
||||
{
|
||||
return size;
|
||||
}
|
||||
|
||||
#endif // __ICCARM__
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2013, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "bootloader/bl_context.h"
|
||||
#include "memory/memory.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Variables
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @brief Memory map for KL25Z128.
|
||||
//!
|
||||
//! This map is not const because it is updated at runtime with the actual sizes of
|
||||
//! flash and RAM for the chip we're running on.
|
||||
memory_map_entry_t g_memoryMap[] = {
|
||||
{ 0x00000000, 0x0001ffff, kMemoryIsExecutable, &g_flashMemoryInterface }, // Flash array
|
||||
{ 0x1ffff000, 0x20002fff, kMemoryIsExecutable, &g_normalMemoryInterface }, // SRAM (SRAM_L + SRAM_U)
|
||||
#if !defined(BL_TARGET_RAM)
|
||||
{ 0x40000000, 0x4007ffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS peripherals
|
||||
{ 0x400ff000, 0x400fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // GPIO
|
||||
{ 0x44000000, 0x5fffffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // BME
|
||||
{ 0xe0000000, 0xe00fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // M0+ private peripherals
|
||||
{ 0xf0003000, 0xf0003fff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // MCM
|
||||
{ 0xf8000000, 0xffffffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // IOPORT (single-cycle GPIO)
|
||||
#endif // !BL_TARGET_RAM
|
||||
{ 0 } // Terminator
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "bootloader/bl_context.h"
|
||||
#include "bootloader/bl_peripheral_interface.h"
|
||||
#include "packet/serial_packet.h"
|
||||
|
||||
extern void uart_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
|
||||
extern void i2c_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
|
||||
extern void spi_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Variables
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#if !BL_CONFIG_UART && !BL_CONFIG_I2C && !BL_CONFIG_SPI && !BL_CONFIG_USB_HID
|
||||
#error At least one peripheral must be enabled!
|
||||
#endif
|
||||
|
||||
//! @brief Peripheral array for KL25Z4.
|
||||
const peripheral_descriptor_t g_peripherals[] = {
|
||||
#if BL_CONFIG_UART
|
||||
// UART0
|
||||
{.typeMask = kPeripheralType_UART,
|
||||
.instance = 0,
|
||||
.pinmuxConfig = uart_pinmux_config,
|
||||
.controlInterface = &g_uart0ControlInterface,
|
||||
.byteInterface = &g_uart0ByteInterface,
|
||||
.packetInterface = &g_framingPacketInterface },
|
||||
#endif // BL_CONFIG_UART
|
||||
#if BL_CONFIG_I2C
|
||||
// I2C0
|
||||
{.typeMask = kPeripheralType_I2CSlave,
|
||||
.instance = 0,
|
||||
.pinmuxConfig = i2c_pinmux_config,
|
||||
.controlInterface = &g_i2cControlInterface,
|
||||
.byteInterface = &g_i2cByteInterface,
|
||||
.packetInterface = &g_framingPacketInterface },
|
||||
#endif // BL_CONFIG_I2C
|
||||
#if BL_CONFIG_SPI
|
||||
// SPI0
|
||||
{.typeMask = kPeripheralType_SPISlave,
|
||||
.instance = 0,
|
||||
.pinmuxConfig = spi_pinmux_config,
|
||||
.controlInterface = &g_spiControlInterface,
|
||||
.byteInterface = &g_spiByteInterface,
|
||||
.packetInterface = &g_framingPacketInterface },
|
||||
#endif // BL_CONFIG_SPI
|
||||
#if (BL_CONFIG_USB_HID || BL_CONFIG_USB_MSC)
|
||||
// USB HID
|
||||
{.typeMask = kPeripheralType_USB_HID,
|
||||
.instance = 0,
|
||||
.pinmuxConfig = NULL,
|
||||
.controlInterface = &g_usbHidControlInterface,
|
||||
.byteInterface = NULL,
|
||||
.packetInterface = &g_usbHidPacketInterface },
|
||||
#endif // BL_CONFIG_USB_HID
|
||||
{ 0 } // Terminator
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! peripheral enable configurations
|
||||
#define BL_ENABLE_PINMUX_UART0 (BL_CONFIG_UART)
|
||||
#define BL_ENABLE_PINMUX_SPI0 (BL_CONFIG_SPI)
|
||||
#define BL_ENABLE_PINMUX_I2C0 (BL_CONFIG_I2C)
|
||||
|
||||
//! UART pinmux configurations
|
||||
#ifdef TOWER
|
||||
#define UART0_RX_PORT_BASE PORTA
|
||||
#define UART0_RX_GPIO_BASE PTA
|
||||
#define UART0_RX_GPIO_PIN_NUM 15 // PTA15
|
||||
#define UART0_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 RX functionality
|
||||
#define UART0_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO functionality
|
||||
#define UART0_RX_GPIO_IRQn PORTA_IRQn
|
||||
#define UART0_RX_GPIO_IRQHandler PORTA_IRQHandler
|
||||
#define UART0_TX_PORT_BASE PORTA
|
||||
#define UART0_TX_GPIO_PIN_NUM 14 // PTA14
|
||||
#define UART0_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 TX functionality
|
||||
#else // FREEDOM
|
||||
#define UART0_RX_PORT_BASE PORTA
|
||||
#define UART0_RX_GPIO_BASE PTA
|
||||
#define UART0_RX_GPIO_PIN_NUM 1 // PTA1
|
||||
#define UART0_RX_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for UART1 RX functionality
|
||||
#define UART0_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO functionality
|
||||
#define UART0_RX_GPIO_IRQn PORTA_IRQn
|
||||
#define UART0_RX_GPIO_IRQHandler PORTA_IRQHandler
|
||||
#define UART0_TX_PORT_BASE PORTA
|
||||
#define UART0_TX_GPIO_PIN_NUM 2 // PTA2
|
||||
#define UART0_TX_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for UART1 TX functionality
|
||||
#endif
|
||||
|
||||
//! I2C pinmux configurations
|
||||
#ifdef TOWER
|
||||
#define I2C0_SCL_PORT_BASE PORTE
|
||||
#define I2C0_SCL_GPIO_PIN_NUM 24 // PTE24
|
||||
#define I2C0_SCL_FUNC_ALT_MODE kPORT_MuxAlt5 // ALT mode for I2C1 SCL functionality
|
||||
#define I2C0_SDA_PORT_BASE PORTE
|
||||
#define I2C0_SDA_GPIO_PIN_NUM 25 // PTE25
|
||||
#define I2C0_SDA_FUNC_ALT_MODE kPORT_MuxAlt5 // ALT mode for I2C1 SDA functionality
|
||||
#else // FREEDOM
|
||||
#define I2C0_SCL_PORT_BASE PORTC
|
||||
#define I2C0_SCL_GPIO_PIN_NUM 8 // PTC8
|
||||
#define I2C0_SCL_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C1 SCL functionality
|
||||
#define I2C0_SDA_PORT_BASE PORTC
|
||||
#define I2C0_SDA_GPIO_PIN_NUM 9 // PTC9
|
||||
#define I2C0_SDA_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C1 SDA functionality
|
||||
#endif
|
||||
|
||||
//! SPI pinmux configurations
|
||||
#define SPI0_PCS_PORT_BASE PORTD
|
||||
#define SPI0_PCS_GPIO_PIN_NUM 0 // PTD0
|
||||
#define SPI0_PCS_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 PCS functionality
|
||||
#define SPI0_SCK_PORT_BASE PORTD
|
||||
#define SPI0_SCK_GPIO_PIN_NUM 1 // PTD1
|
||||
#define SPI0_SCK_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SCK functionality
|
||||
#define SPI0_SOUT_PORT_BASE PORTD
|
||||
#define SPI0_SOUT_GPIO_PIN_NUM 2 // PTD2
|
||||
#define SPI0_SOUT_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SOUT functionality
|
||||
#define SPI0_SIN_PORT_BASE PORTD
|
||||
#define SPI0_SIN_GPIO_PIN_NUM 3 // PTD3
|
||||
#define SPI0_SIN_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SIN functionality
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,241 @@
|
||||
/* ---------------------------------------------------------------------------------------*/
|
||||
/* @file: startup_MKL25Z4.s */
|
||||
/* @purpose: CMSIS Cortex-M0P Core Device Startup File */
|
||||
/* MKL25Z4 */
|
||||
/* @version: 2.4 */
|
||||
/* @date: 2014-10-14 */
|
||||
/* @build: b150128 */
|
||||
/* ---------------------------------------------------------------------------------------*/
|
||||
/* */
|
||||
/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without modification, */
|
||||
/* are permitted provided that the following conditions are met: */
|
||||
/* */
|
||||
/* o Redistributions of source code must retain the above copyright notice, this list */
|
||||
/* of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* o Redistributions in binary form must reproduce the above copyright notice, this */
|
||||
/* list of conditions and the following disclaimer in the documentation and/or */
|
||||
/* other materials provided with the distribution. */
|
||||
/* */
|
||||
/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
|
||||
/* contributors may be used to endorse or promote products derived from this */
|
||||
/* software without specific prior written permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
|
||||
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
|
||||
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
|
||||
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
|
||||
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
|
||||
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
|
||||
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
|
||||
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
|
||||
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/*****************************************************************************/
|
||||
/* Version: GCC for ARM Embedded Processors */
|
||||
/*****************************************************************************/
|
||||
.syntax unified
|
||||
.arch armv6-m
|
||||
|
||||
.section .isr_vector, "a"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler*/
|
||||
.long HardFault_Handler /* Hard Fault Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long SVC_Handler /* SVCall Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long PendSV_Handler /* PendSV Handler*/
|
||||
.long SysTick_Handler /* SysTick Handler*/
|
||||
|
||||
/* External Interrupts*/
|
||||
.long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
|
||||
.long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
|
||||
.long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
|
||||
.long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
|
||||
.long Reserved20_IRQHandler /* Reserved interrupt*/
|
||||
.long FTFA_IRQHandler /* Command complete and read collision*/
|
||||
.long LVD_LVW_IRQHandler /* Low-voltage detect, low-voltage warning*/
|
||||
.long LLW_IRQHandler /* Low leakage wakeup*/
|
||||
.long I2C0_IRQHandler /* I2C0 interrupt*/
|
||||
.long I2C1_IRQHandler /* I2C1 interrupt*/
|
||||
.long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
|
||||
.long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
|
||||
.long UART0_IRQHandler /* UART0 status and error*/
|
||||
.long UART1_IRQHandler /* UART1 status and error*/
|
||||
.long UART2_IRQHandler /* UART2 status and error*/
|
||||
.long ADC0_IRQHandler /* ADC0 interrupt*/
|
||||
.long CMP0_IRQHandler /* CMP0 interrupt*/
|
||||
.long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
|
||||
.long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
|
||||
.long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
|
||||
.long RTC_IRQHandler /* RTC alarm*/
|
||||
.long RTC_Seconds_IRQHandler /* RTC seconds*/
|
||||
.long PIT_IRQHandler /* PIT interrupt*/
|
||||
.long Reserved39_IRQHandler /* Reserved interrupt*/
|
||||
.long USB0_IRQHandler /* USB0 interrupt*/
|
||||
.long DAC0_IRQHandler /* DAC0 interrupt*/
|
||||
.long TSI0_IRQHandler /* TSI0 interrupt*/
|
||||
.long MCG_IRQHandler /* MCG interrupt*/
|
||||
.long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
|
||||
.long Reserved45_IRQHandler /* Reserved interrupt*/
|
||||
.long PORTA_IRQHandler /* PORTA Pin detect*/
|
||||
.long PORTD_IRQHandler /* PORTD Pin detect*/
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Bootloader Config Area */
|
||||
.section .BootloaderConfig, "a"
|
||||
|
||||
#ifdef BL_HAS_BOOTLOADER_CONFIG
|
||||
|
||||
//__bootloaderConfigurationArea ; 0x3c0
|
||||
// .long 'kcfg' // [00:03] tag - Tag value used to validate the bootloader configuration data. Must be set to 'kcfg'
|
||||
.long 0x6766636b
|
||||
.long 0xFFFFFFFF // [04:07] crcStartAddress
|
||||
.long 0xFFFFFFFF // [08:0b] crcByteCount
|
||||
.long 0xFFFFFFFF // [0c:0f] crcExpectedValue
|
||||
.byte 0xFF // [10:10] enabledPeripherals
|
||||
.byte 0xFF // [11:11] i2cSlaveAddress
|
||||
.short 5000 // [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code
|
||||
.short 0xFFFF // [14:15] usbVid
|
||||
.short 0xFFFF // [16:17] usbPid
|
||||
.long 0xFFFFFFFF // [18:1b] usbStringsPointer
|
||||
.byte 0xFF // [1c:1c] clockFlags - High Speed and other clock options
|
||||
.byte 0xFF // [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1
|
||||
.short 0xFFFF // [1e:1f] reserved
|
||||
// Fill to align with flash configuration field.
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF // Reserved for user TRIM value
|
||||
#else
|
||||
//Fill to align with flash configuration field.
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF // Reserved for user TRIM value
|
||||
#endif // BL_HAS_BOOTLOADER_CONFIG
|
||||
|
||||
/* Flash Configuration */
|
||||
.section .FlashConfig, "a"
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFE
|
||||
|
||||
.text
|
||||
.thumb
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
cpsid i /* Mask interrupts */
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
bl init_data_bss
|
||||
cpsie i /* Unmask interrupts */
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
#ifndef __ATOLLIC__
|
||||
bl __START
|
||||
#else
|
||||
bl __libc_init_array
|
||||
bl main
|
||||
#endif
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DefaultISR
|
||||
.type DefaultISR, %function
|
||||
DefaultISR:
|
||||
ldr r0, =DefaultISR
|
||||
bx r0
|
||||
.size DefaultISR, . - DefaultISR
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, DefaultISR
|
||||
.endm
|
||||
|
||||
/* Exception Handlers */
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DMA0_IRQHandler
|
||||
def_irq_handler DMA1_IRQHandler
|
||||
def_irq_handler DMA2_IRQHandler
|
||||
def_irq_handler DMA3_IRQHandler
|
||||
def_irq_handler Reserved20_IRQHandler
|
||||
def_irq_handler FTFA_IRQHandler
|
||||
def_irq_handler LVD_LVW_IRQHandler
|
||||
def_irq_handler LLW_IRQHandler
|
||||
def_irq_handler I2C0_IRQHandler
|
||||
def_irq_handler I2C1_IRQHandler
|
||||
def_irq_handler SPI0_IRQHandler
|
||||
def_irq_handler SPI1_IRQHandler
|
||||
def_irq_handler UART0_IRQHandler
|
||||
def_irq_handler UART1_IRQHandler
|
||||
def_irq_handler UART2_IRQHandler
|
||||
def_irq_handler ADC0_IRQHandler
|
||||
def_irq_handler CMP0_IRQHandler
|
||||
def_irq_handler TPM0_IRQHandler
|
||||
def_irq_handler TPM1_IRQHandler
|
||||
def_irq_handler TPM2_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler RTC_Seconds_IRQHandler
|
||||
def_irq_handler PIT_IRQHandler
|
||||
def_irq_handler Reserved39_IRQHandler
|
||||
def_irq_handler USB0_IRQHandler
|
||||
def_irq_handler DAC0_IRQHandler
|
||||
def_irq_handler TSI0_IRQHandler
|
||||
def_irq_handler MCG_IRQHandler
|
||||
def_irq_handler LPTMR0_IRQHandler
|
||||
def_irq_handler Reserved45_IRQHandler
|
||||
def_irq_handler PORTA_IRQHandler
|
||||
def_irq_handler PORTD_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,258 @@
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_MKL25Z4.s
|
||||
; * @purpose: CMSIS Cortex-M0plus Core Device Startup File
|
||||
; * MKL25Z4
|
||||
; * @version: 1.3
|
||||
; * @date: 2012-10-4
|
||||
; *----------------------------------------------------------------------------
|
||||
; *
|
||||
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
EXTERN g_bootloaderTree
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
__vector_table_0x1c
|
||||
DCD g_bootloaderTree
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
|
||||
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
|
||||
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
|
||||
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
|
||||
DCD Reserved20_IRQHandler ; Reserved interrupt 20
|
||||
DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C0 interrupt 25
|
||||
DCD SPI0_IRQHandler ; SPI0 interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 interrupt
|
||||
DCD UART0_IRQHandler ; UART0 status/error interrupt
|
||||
DCD UART1_IRQHandler ; UART1 status/error interrupt
|
||||
DCD UART2_IRQHandler ; UART2 status/error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
|
||||
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
|
||||
DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
|
||||
DCD PIT_IRQHandler ; PIT timer interrupt
|
||||
DCD Reserved39_IRQHandler ; Reserved interrupt 39
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD DAC0_IRQHandler ; DAC0 interrupt
|
||||
DCD TSI0_IRQHandler ; TSI0 interrupt
|
||||
DCD MCG_IRQHandler ; MCG interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD Reserved45_IRQHandler ; Reserved interrupt 45
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
; Fill to align with flash configuration field.
|
||||
REPT (768/4) ; 0xc0 - 0x3FF 832
|
||||
DCD 0
|
||||
ENDR
|
||||
__Vectors_End
|
||||
|
||||
#ifdef BL_HAS_BOOTLOADER_CONFIG
|
||||
|
||||
__bootloaderConfigurationArea ; 0x3c0
|
||||
DCD 'kcfg' ; [00:03] tag - Tag value used to validate the bootloader configuration data. Must be set to 'kcfg'.
|
||||
DCD 0xFFFFFFFF ; [04:07] crcStartAddress
|
||||
DCD 0xFFFFFFFF ; [08:0b] crcByteCount
|
||||
DCD 0xFFFFFFFF ; [0c:0f] crcExpectedValue
|
||||
DCB 0xFF ; [10:10] enabledPeripherals
|
||||
DCB 0xFF ; [11:11] i2cSlaveAddress
|
||||
DCW 5000 ; [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code
|
||||
DCW 0xFFFF ; [14:15] usbVid
|
||||
DCW 0xFFFF ; [16:17] usbPid
|
||||
DCD 0xFFFFFFFF ; [18:1b] usbStringsPointer
|
||||
DCB 0xFF ; [1c:1c] clockFlags - High Speed and other clock options
|
||||
DCB 0xFF ; [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1
|
||||
DCW 0xFFFF ; [1e:1f] reserved
|
||||
; Fill to align with flash configuration field.
|
||||
REPT (0x400-0x3e0)/4 ; 0x3E0 - 0x3FF
|
||||
DCD 0xFFFFFFFF ; Reserved for user TRIM value
|
||||
ENDR
|
||||
#else
|
||||
; Fill to align with flash configuration field.
|
||||
REPT (0x400-0x3c0)/4 ; 0x3c0:0x400
|
||||
DCD 0xFFFFFFFF ; Reserved for user TRIM value
|
||||
ENDR
|
||||
#endif // BL_HAS_BOOTLOADER_CONFIG
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Flash configuration field.
|
||||
;;
|
||||
__flash_config
|
||||
DCD 0xFFFFFFFF ; 0x400
|
||||
DCD 0xFFFFFFFF ; 0x404
|
||||
DCD 0xFFFFFFFF ; 0x408
|
||||
DCD 0xFFFFFFFE ; 0x40c, FSEC=0xFE
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DMA0_IRQHandler
|
||||
PUBWEAK DMA1_IRQHandler
|
||||
PUBWEAK DMA2_IRQHandler
|
||||
PUBWEAK DMA3_IRQHandler
|
||||
PUBWEAK Reserved20_IRQHandler
|
||||
PUBWEAK FTFA_IRQHandler
|
||||
PUBWEAK LVD_LVW_IRQHandler
|
||||
PUBWEAK LLW_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK UART0_IRQHandler
|
||||
PUBWEAK UART1_IRQHandler
|
||||
PUBWEAK UART2_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK TPM0_IRQHandler
|
||||
PUBWEAK TPM1_IRQHandler
|
||||
PUBWEAK TPM2_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK RTC_Seconds_IRQHandler
|
||||
PUBWEAK PIT_IRQHandler
|
||||
PUBWEAK Reserved39_IRQHandler
|
||||
PUBWEAK USB0_IRQHandler
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
PUBWEAK TSI0_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPTimer_IRQHandler
|
||||
PUBWEAK Reserved45_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTD_IRQHandler
|
||||
PUBWEAK DefaultISR
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
Reserved20_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
TPM0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT_IRQHandler
|
||||
Reserved39_IRQHandler
|
||||
USB0_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
Reserved45_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
DefaultISR
|
||||
B .
|
||||
|
||||
|
||||
END
|
||||
@@ -0,0 +1,165 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "system_MKL25Z4.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "target_config.h"
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 0
|
||||
#endif
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = kDefaultMcgOutWithoutUsb;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if (DISABLE_WDOG)
|
||||
/* Disable the WDOG module */
|
||||
/* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
|
||||
SIM->COPC = (uint32_t)0x00u;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
}
|
||||
|
||||
uint32_t GetSystemMCGPLLClock(void)
|
||||
{
|
||||
#if (CLOCK_SETUP == 0)
|
||||
// 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
|
||||
// Reference clock source for MCG module is the slow internal clock source 32.768kHz
|
||||
// Core clock = 41.94MHz, BusClock = 13.98MHz
|
||||
// FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
|
||||
// condtions occur:
|
||||
// • C1[CLKS] bits are written to 00
|
||||
// • C1[IREFS] bit is written to 1
|
||||
// • C6[PLLS] bit is written to 0
|
||||
// In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32
|
||||
// kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as
|
||||
// selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the
|
||||
// C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power state
|
||||
// unless C5[PLLCLKEN0] is set.
|
||||
// MCG->C1 = (uint8_t)0x06U; IREFS = 1 IRCLKEN = 1, slow interal clock selected
|
||||
// MCG->C2 = (uint8_t)0x00U;
|
||||
// MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U); DRST_DRS = 1, DMX32 = 0 FLL Factor =
|
||||
// 1280
|
||||
// MCG->C5 = (uint8_t)0x00U; PLL Disabled
|
||||
// MCG->C6 = (uint8_t)0x00U; FLL Selected
|
||||
|
||||
return 0;
|
||||
|
||||
#elif(CLOCK_SETUP == 1)
|
||||
// 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
|
||||
// Reference clock source for MCG module is an external crystal 8MHz
|
||||
// Core clock = 48MHz, BusClock = 24MHz
|
||||
// PLL Engaged External (PEE) mode is entered when all the following conditions occur:
|
||||
// • C1[CLKS] bits are written to 00
|
||||
// • C1[IREFS] bit is written to 0
|
||||
// • C6[PLLS] bit is written to 1
|
||||
// In PEE mode, the MCGOUTCLK is derived from the PLL clock, which is controlled by the external
|
||||
// reference clock. The PLL clock frequency locks to a multiplication factor, as specified by C6[VDIV0],
|
||||
// times the external reference frequency, as specified by C5[PRDIV0]. The PLL's programmable
|
||||
// reference divider must be configured to produce a valid PLL reference clock. The FLL is
|
||||
// disabled in
|
||||
// a low-power state.
|
||||
// MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0
|
||||
// MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
|
||||
// MCG->C4: DMX32=0,DRST_DRS=0
|
||||
// MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1
|
||||
// MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0
|
||||
// MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0
|
||||
// MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
|
||||
// C6[VDIV0] = 24x
|
||||
// C5[PRDIV0] = /2
|
||||
// MCG PLL output then /2 again
|
||||
|
||||
return (((CPU_XTAL_CLK_HZ * 24) / 2) / 2);
|
||||
|
||||
#elif(CLOCK_SETUP == 2)
|
||||
// 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
|
||||
// Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
|
||||
// Core clock = 8MHz, BusClock = 8MHz
|
||||
// Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:
|
||||
// • C1[CLKS] bits are written to 10
|
||||
// • C1[IREFS] bit is written to 0
|
||||
// • C2[LP] bit is written to 1
|
||||
// In BLPE mode, MCGOUTCLK is derived from the external reference clock. The FLL is disabled and
|
||||
// PLL is disabled even if the C5[PLLCLKEN0] is set to 1.
|
||||
|
||||
return 0;
|
||||
|
||||
#endif // (CLOCK_SETUP == 2)
|
||||
}
|
||||
|
||||
uint32_t GetSystemMCGFLLClock(void)
|
||||
{
|
||||
#if (CLOCK_SETUP == 0)
|
||||
// 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
|
||||
// Reference clock source for MCG module is the slow internal clock source 32.768kHz
|
||||
// Core clock = 41.94MHz, BusClock = 13.98MHz
|
||||
// MCG->C1 = (uint8_t)0x06U; IREFS = 1 IRCLKEN = 1, slow interal clock selected
|
||||
// MCG->C2 = (uint8_t)0x00U;
|
||||
// MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U); DRST_DRS = 1, DMX32 = 0 FLL Factor =
|
||||
// 1280
|
||||
// MCG->C5 = (uint8_t)0x00U; PLL Disabled
|
||||
// MCG->C6 = (uint8_t)0x00U; FLL Selected
|
||||
|
||||
return (CPU_INT_SLOW_CLK_HZ * 1280);
|
||||
|
||||
#elif(CLOCK_SETUP == 1)
|
||||
// FLL Clock disabled
|
||||
|
||||
return 0;
|
||||
|
||||
#elif(CLOCK_SETUP == 2)
|
||||
// 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
|
||||
// Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
|
||||
// Core clock = 8MHz, BusClock = 8MHz
|
||||
// Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:
|
||||
// • C1[CLKS] bits are written to 10
|
||||
// • C1[IREFS] bit is written to 0
|
||||
// • C2[LP] bit is written to 1
|
||||
// In BLPE mode, MCGOUTCLK is derived from the external reference clock. The FLL is disabled and
|
||||
// PLL is disabled even if the C5[PLLCLKEN0] is set to 1.
|
||||
|
||||
return 0;
|
||||
|
||||
#endif // (CLOCK_SETUP == 2)
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,346 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MKL25Z128FM4
|
||||
** MKL25Z128FT4
|
||||
** MKL25Z128LH4
|
||||
** MKL25Z128VLK4
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** GNU C Compiler - CodeSourcery Sourcery G++
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012
|
||||
** Version: rev. 2.5, 2015-02-19
|
||||
** Build: b150224
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2012-06-13)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2012-06-21)
|
||||
** Update according to reference manual rev. 1.
|
||||
** - rev. 1.2 (2012-08-01)
|
||||
** Device type UARTLP changed to UART0.
|
||||
** - rev. 1.3 (2012-10-04)
|
||||
** Update according to reference manual rev. 3.
|
||||
** - rev. 1.4 (2012-11-22)
|
||||
** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
|
||||
** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
|
||||
** - rev. 1.5 (2013-04-05)
|
||||
** Changed start of doxygen comment.
|
||||
** - rev. 2.0 (2013-10-29)
|
||||
** Register accessor macros added to the memory map.
|
||||
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||
** System initialization updated.
|
||||
** - rev. 2.1 (2014-07-16)
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
** System initialization and startup updated.
|
||||
** - rev. 2.2 (2014-08-22)
|
||||
** System initialization updated - default clock config changed.
|
||||
** - rev. 2.3 (2014-08-28)
|
||||
** Update of startup files - possibility to override DefaultISR added.
|
||||
** - rev. 2.4 (2014-10-14)
|
||||
** Interrupt INT_LPTimer renamed to INT_LPTMR0.
|
||||
** - rev. 2.5 (2015-02-19)
|
||||
** Renamed interrupt vector LLW to LLWU.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MKL25Z4
|
||||
* @version 2.5
|
||||
* @date 2015-02-19
|
||||
* @brief Device specific configuration file for MKL25Z4 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MKL25Z4_H_
|
||||
#define _SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* MCG mode constants */
|
||||
|
||||
#define MCG_MODE_FEI 0U
|
||||
#define MCG_MODE_FBI 1U
|
||||
#define MCG_MODE_BLPI 2U
|
||||
#define MCG_MODE_FEE 3U
|
||||
#define MCG_MODE_FBE 4U
|
||||
#define MCG_MODE_BLPE 5U
|
||||
#define MCG_MODE_PBE 6U
|
||||
#define MCG_MODE_PEE 7U
|
||||
|
||||
/* Predefined clock setups
|
||||
0 ... Default part configuration
|
||||
Multipurpose Clock Generator (MCG) in FEI mode.
|
||||
Reference clock source for MCG module: Slow internal reference clock
|
||||
Core clock = 20.97152MHz
|
||||
Bus clock = 20.97152MHz
|
||||
1 ... Maximum achievable clock frequency configuration
|
||||
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||
Reference clock source for MCG module: System oscillator reference clock
|
||||
Core clock = 48MHz
|
||||
Bus clock = 24MHz
|
||||
2 ... Chip internaly clocked, ready for Very Low Power Run mode
|
||||
Multipurpose Clock Generator (MCG) in BLPI mode.
|
||||
Reference clock source for MCG module: Fast internal reference clock
|
||||
Core clock = 4MHz
|
||||
Bus clock = 0.8MHz
|
||||
3 ... Chip externally clocked, ready for Very Low Power Run mode
|
||||
Multipurpose Clock Generator (MCG) in BLPE mode.
|
||||
Reference clock source for MCG module: System oscillator reference clock
|
||||
Core clock = 4MHz
|
||||
Bus clock = 1MHz
|
||||
4 ... USB clock setup
|
||||
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||
Reference clock source for MCG module: System oscillator reference clock
|
||||
Core clock = 48MHz
|
||||
Bus clock = 24MHz
|
||||
*/
|
||||
|
||||
/* Define clock source values */
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
|
||||
/* RTC oscillator setting */
|
||||
|
||||
/* Low power mode enable */
|
||||
/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
|
||||
#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
|
||||
|
||||
/* Internal reference clock trim */
|
||||
/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
|
||||
#ifdef CLOCK_SETUP
|
||||
#if (CLOCK_SETUP == 0)
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 1)
|
||||
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
|
||||
/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 2)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=4 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 3)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=3 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x10030000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 4)
|
||||
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
|
||||
/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
|
||||
|
||||
#endif
|
||||
#else
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
/**
|
||||
* @brief Returns the MCG PLL Clock frequency
|
||||
*
|
||||
*/
|
||||
uint32_t GetSystemMCGPLLClock(void);
|
||||
|
||||
/**
|
||||
* @brief Returns the MCG FLL Clock frequency
|
||||
*
|
||||
*/
|
||||
uint32_t GetSystemMCGFLLClock(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* #if !defined(_SYSTEM_MKL25Z4_H_) */
|
||||
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#if !defined(__TARGET_CONFIG_H__)
|
||||
#define __TARGET_CONFIG_H__
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @brief Constants for clock frequencies.
|
||||
enum
|
||||
{
|
||||
kDefaultMcgOutWithoutUsb = 20971520u,
|
||||
kDefaultMcgOutkWithUsb = 96000000u,
|
||||
kMinCoreClockWithUsbSupport = 20000000u,
|
||||
kMaxCoreClock = 48000000u,
|
||||
kMaxBusClock = 24000000u,
|
||||
kDivider1_Min = 1,
|
||||
kDivider1_Max = 16,
|
||||
kDivider4_Min = 1,
|
||||
kDivider4_Max = 8
|
||||
};
|
||||
|
||||
//! @brief Constants for sram partition
|
||||
enum _sram_partition
|
||||
{
|
||||
kSram_LowerPart = 1,
|
||||
kSram_UpperPart = 3,
|
||||
};
|
||||
|
||||
//! @brief Version constants for the target.
|
||||
enum _target_version_constants
|
||||
{
|
||||
kTarget_Version_Name = 'T',
|
||||
kTarget_Version_Major = 1,
|
||||
kTarget_Version_Minor = 0,
|
||||
kTarget_Version_Bugfix = 0
|
||||
};
|
||||
|
||||
#endif // __TARGET_CONFIG_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __USB_DEVICE_CONFIG_H__
|
||||
#define __USB_DEVICE_CONFIG_H__ 1
|
||||
|
||||
#include "bootloader_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup usb_device_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Hardware instance define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief KHCI instance count */
|
||||
#define USB_DEVICE_CONFIG_KHCI (1U)
|
||||
|
||||
/*! @brief EHCI instance count */
|
||||
#define USB_DEVICE_CONFIG_EHCI (0U)
|
||||
|
||||
/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/
|
||||
#define USB_DEVICE_CONFIG_NUM (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI)
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name class instance define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief HID instance count */
|
||||
#define USB_DEVICE_CONFIG_HID (BL_CONFIG_USB_HID)
|
||||
|
||||
/*! @brief CDC ACM instance count */
|
||||
#define USB_DEVICE_CONFIG_CDC_ACM (0U)
|
||||
|
||||
/*! @brief MSC instance count */
|
||||
#define USB_DEVICE_CONFIG_MSC (BL_CONFIG_USB_MSC)
|
||||
|
||||
/*! @brief Audio instance count */
|
||||
#define USB_DEVICE_CONFIG_AUDIO (0U)
|
||||
|
||||
/*! @brief PHDC instance count */
|
||||
#define USB_DEVICE_CONFIG_PHDC (0U)
|
||||
|
||||
/*! @brief Video instance count */
|
||||
#define USB_DEVICE_CONFIG_VIDEO (0U)
|
||||
|
||||
/*! @brief CCID instance count */
|
||||
#define USB_DEVICE_CONFIG_CCID (0U)
|
||||
|
||||
/*! @brief Printer instance count */
|
||||
#define USB_DEVICE_CONFIG_PRINTER (0U)
|
||||
|
||||
/*! @brief DFU instance count */
|
||||
#define USB_DEVICE_CONFIG_DFU (0U)
|
||||
|
||||
/* @} */
|
||||
|
||||
/*! @brief Whether device is self power. 1 supported, 0 not supported */
|
||||
#define USB_DEVICE_CONFIG_SELF_POWER (1U)
|
||||
|
||||
/*! @brief Whether device remote wakeup supported. 1 supported, 0 not supported */
|
||||
#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
|
||||
|
||||
/*! @brief How many endpoints are supported in the stack. */
|
||||
#define USB_DEVICE_CONFIG_ENDPOINTS (8U)
|
||||
|
||||
/*! @brief Whether the device task is enabled. */
|
||||
#define USB_DEVICE_CONFIG_USE_TASK (0U)
|
||||
|
||||
/*! @brief How many the notification message are supported when the device task enabled. */
|
||||
#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U)
|
||||
|
||||
#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
|
||||
|
||||
/*! @brief The MAX buffer length for the KHCI DMA workaround.*/
|
||||
/* clang-format off */
|
||||
#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U)
|
||||
/*! @brief Whether handle the USB KHCI bus error. */
|
||||
#define USB_DEVICE_CONFIG_KHCI_ERROR_HANDLING (0U)
|
||||
/* clang-format on */
|
||||
#endif
|
||||
|
||||
#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
|
||||
/*! @brief How many the DTD are supported. */
|
||||
/* clang-format off */
|
||||
#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
|
||||
/*! @brief Whether handle the USB EHCI bus error. */
|
||||
#define USB_DEVICE_CONFIG_EHCI_ERROR_HANDLING (0U)
|
||||
/*! @brief Whether test mode enabled. */
|
||||
#define USB_DEVICE_CONFIG_EHCI_TEST_MODE (0U)
|
||||
/*! @brief Whether the EHCI ID pin detect feature enabled. */
|
||||
#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U)
|
||||
/* clang-format on */
|
||||
#endif
|
||||
|
||||
/*! @brief Whether the keep alive feature enabled. */
|
||||
/* clang-format off */
|
||||
#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U)
|
||||
|
||||
/*! @brief Whether the transfer buffer is cache-enabled or not. */
|
||||
#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
|
||||
|
||||
/*! @brief Whether the low power mode is enabled or not. */
|
||||
#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
|
||||
|
||||
/*! @brief Whether the device detached feature is enabled or not. */
|
||||
#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
|
||||
/* clang-format on */
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* __USB_DEVICE_CONFIG_H__ */
|
||||
Reference in New Issue
Block a user