Add KBOOT.

This commit is contained in:
László Monda
2016-08-10 01:45:15 +02:00
commit e6c1fce5b4
9392 changed files with 3751375 additions and 0 deletions

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View File

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View File

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View File

@@ -0,0 +1,62 @@
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View File

@@ -0,0 +1,80 @@
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View File

@@ -0,0 +1,199 @@
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View File

@@ -0,0 +1,9 @@
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View File

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View File

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View File

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@@ -0,0 +1,62 @@
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View File

@@ -0,0 +1,80 @@
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View File

@@ -0,0 +1,199 @@
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View File

@@ -0,0 +1,9 @@
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View File

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View File

@@ -0,0 +1,199 @@
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View File

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View File

@@ -0,0 +1,199 @@
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<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doConnectToRunning" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doFirstReset" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateConsole" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerInitRegs" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerLocalOnly" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerSilent" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerVerifyDownload" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doSecondReset" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doStartGdbServer" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableFlashBreakpoints" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSwo" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.firstResetSpeed" value="30"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.firstResetType" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set tcp auto-retry on&#13;&#10;set tcp connect-timeout 30"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerConnection" value="usb"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerConnectionAddress" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDebugInterface" value="swd"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceEndianness" value="little"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceName" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceSpeed" value="30"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerExecutable" value="${jlink_path}/JLinkGDBServerCL"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerGdbPortNumber" value="7224"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerLog" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerOther" value="-s"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerSwoPortNumber" value="2332"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.interfaceSpeed" value="auto"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="-1"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherInitCommands" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="-1"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value="USB1"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.secondResetType" value=""/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetCpuFreq" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetPortMask" value="0x1"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetSwoFreq" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="127.0.0.1"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="7224"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release/tower_bootloader.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="tower_bootloader"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1792027861"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/tower_bootloader"/></listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

View File

@@ -0,0 +1,9 @@
<?xml version="1.0"?>
<workspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="workingsets.xsd">
<projects>
</projects>
<workingsets>
</workingsets>
<cdtconfigurations>
</cdtconfigurations>
</workspace>

View File

@@ -0,0 +1,40 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void Setup (void) {
SP = _RDWORD(0x1FFF0000); // Setup Stack Pointer
PC = _RDWORD(0x1FFF0004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x1FFF0000); // Setup Vector Table Offset Register
}
LOAD %L INCREMENTAL // Download to RAM
Setup();
g, main

View File

@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<WorkspaceName>WorkSpace</WorkspaceName>
<project><PathAndName>flashloader.uvprojx</PathAndName><NodeIsActive>1</NodeIsActive></project></ProjectWorkspace>

View File

@@ -0,0 +1,338 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>flashloader Debug</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\output\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>0</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Quick Start Guide (TWR-K60D100M)</Title>
<Path>C:\DevTools\Keil_v5\ARM\PACK\Keil\Kinetis_K60_DFP\1.4.0\Documents\TWR-K60D100MQSG.pdf</Path>
</Book>
<Book>
<Number>1</Number>
<Title>Schematic (TWR-K60D100M)</Title>
<Path>C:\DevTools\Keil_v5\ARM\PACK\Keil\Kinetis_K60_DFP\1.4.0\Documents\TWR-K60D100M_SCH.pdf</Path>
</Book>
<Book>
<Number>2</Number>
<Title>User Manual (TWR-K60D100M)</Title>
<Path>C:\DevTools\Keil_v5\ARM\PACK\Keil\Kinetis_K60_DFP\1.4.0\Documents\TWRK60D100MUM.pdf</Path>
</Book>
<Book>
<Number>3</Number>
<Title>TWR-K60D100M Web Page (TWR-K60D100M)</Title>
<Path>http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=TWR-K60D100M</Path>
</Book>
</Books>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>0</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>12</nTsel>
<sDll/>
<sDllPa/>
<sDlgDll/>
<sDlgPa/>
<sIfile/>
<tDll/>
<tDllPa/>
<tDlgDll/>
<tDlgPa/>
<tIfile>.\Debug_RAM.ini</tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MK_P2M0 -FS00 -FL0200000 -FP0($$Device:MK65FN2M0xxx18$Flash\MK_P2M0.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable/>
<LintConfigFile/>
<bLintAuto>0</bLintAuto>
</TargetOption>
</Target>
<Target>
<TargetName>flashloader Release</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\output\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>0</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Quick Start Guide (TWR-K60D100M)</Title>
<Path>C:\DevTools\Keil_v5\ARM\PACK\Keil\Kinetis_K60_DFP\1.4.0\Documents\TWR-K60D100MQSG.pdf</Path>
</Book>
<Book>
<Number>1</Number>
<Title>Schematic (TWR-K60D100M)</Title>
<Path>C:\DevTools\Keil_v5\ARM\PACK\Keil\Kinetis_K60_DFP\1.4.0\Documents\TWR-K60D100M_SCH.pdf</Path>
</Book>
<Book>
<Number>2</Number>
<Title>User Manual (TWR-K60D100M)</Title>
<Path>C:\DevTools\Keil_v5\ARM\PACK\Keil\Kinetis_K60_DFP\1.4.0\Documents\TWRK60D100MUM.pdf</Path>
</Book>
<Book>
<Number>3</Number>
<Title>TWR-K60D100M Web Page (TWR-K60D100M)</Title>
<Path>http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=TWR-K60D100M</Path>
</Book>
</Books>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>12</nTsel>
<sDll/>
<sDllPa/>
<sDlgDll/>
<sDlgPa/>
<sIfile/>
<tDll/>
<tDllPa/>
<tDlgDll/>
<tDlgPa/>
<tIfile>.\Debug_RAM.ini</tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MK_P2M0 -FS00 -FL0200000 -FP0($$Device:MK65FN2M0xxx18$Flash\MK_P2M0.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable/>
<LintConfigFile/>
<bLintAuto>0</bLintAuto>
</TargetOption>
</Target>
</ProjectOpt>

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[STARTUP]
CPUTARGETTYPENAME=K65FN2M0M18
USE_CYCLONEPRO_RELAYS=0
CYCLONEPRO_POWEROFFONEXIT=0
CYCLONEPRO_CURRENTVOLTAGE=128
CYCLONEPRO_POWERDOWNDELAY=250
CYCLONEPRO_POWERUPDELAY=250
MULTILINK_POWERDOWNDELAY=250
MULTILINK_POWERUPDELAY=1000
USE_SWD=1
IO_DELAY_CNT=0
FREQ_FX=4
FREQ_NORMAL=0
FREQ_OSJTAG=0
FREQ_CYCLONE=3
FREQ_TRACELINK=3
FREQ_LIGHTNING=1
FREQ_OPENSDA=0
RESET_DELAY=0
PORT=
PORT_NAME_STRING=
INTERFACE_SELECTION=7
SHOWDIALOG=0
[PEDEBUG]
ERASE_PROGRAM_WITHOUT_ASKING=1
CURRENTDEVICE=K65FN2M0M18
[DEVICE]
CHIPMODE=K65FN2M0M18

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<WorkspaceName>WorkSpace</WorkspaceName>
<project><PathAndName>flashloader_loader.uvprojx</PathAndName><NodeIsActive>1</NodeIsActive></project></ProjectWorkspace>

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[STARTUP]
CPUTARGETTYPENAME=K65FN2M0M18
USE_CYCLONEPRO_RELAYS=0
CYCLONEPRO_POWEROFFONEXIT=0
CYCLONEPRO_CURRENTVOLTAGE=128
CYCLONEPRO_POWERDOWNDELAY=250
CYCLONEPRO_POWERUPDELAY=250
MULTILINK_POWERDOWNDELAY=250
MULTILINK_POWERUPDELAY=1000
USE_SWD=1
IO_DELAY_CNT=0
FREQ_FX=4
FREQ_NORMAL=0
FREQ_OSJTAG=0
FREQ_CYCLONE=3
FREQ_TRACELINK=3
FREQ_LIGHTNING=1
FREQ_OPENSDA=0
RESET_DELAY=0
PORT=
PORT_NAME_STRING=
INTERFACE_SELECTION=7
SHOWDIALOG=0
[PEDEBUG]
ERASE_PROGRAM_WITHOUT_ASKING=1
CURRENTDEVICE=K65FN2M0M18
[DEVICE]
CHIPMODE=K65FN2M0M18

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[STARTUP]
CPUTARGETTYPENAME=K65FN2M0M18
USE_CYCLONEPRO_RELAYS=0
CYCLONEPRO_POWEROFFONEXIT=0
CYCLONEPRO_CURRENTVOLTAGE=128
CYCLONEPRO_POWERDOWNDELAY=250
CYCLONEPRO_POWERUPDELAY=250
MULTILINK_POWERDOWNDELAY=250
MULTILINK_POWERUPDELAY=1000
USE_SWD=1
IO_DELAY_CNT=0
FREQ_FX=4
FREQ_NORMAL=0
FREQ_OSJTAG=0
FREQ_CYCLONE=3
FREQ_TRACELINK=3
FREQ_LIGHTNING=1
FREQ_OPENSDA=0
RESET_DELAY=0
PORT=
PORT_NAME_STRING=
INTERFACE_SELECTION=7
SHOWDIALOG=0
[PEDEBUG]
ERASE_PROGRAM_WITHOUT_ASKING=1
CURRENTDEVICE=K65FN2M0M18
[DEVICE]
CHIPMODE=K65FN2M0M18

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<WorkspaceName>WorkSpace</WorkspaceName>
<project><PathAndName>tower_bootloader.uvprojx</PathAndName><NodeIsActive>1</NodeIsActive></project></ProjectWorkspace>

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************
*
* $FileName: interrupt_vector_numbers_MK65F18.h$
* $Version :
* $Date :
*
* Comments:
*
*
*
*END************************************************************************/
#ifndef ____INTERRUPT_VECTOR_NUMBERS_MK65F18_H__
#define ____INTERRUPT_VECTOR_NUMBERS_MK65F18_H__
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
typedef enum
{
INT_Initial_Stack_Pointer = 0, /**< Initial Stack Pointer */
INT_Initial_Program_Counter = 1, /**< Initial Program Counter */
INT_NMI = 2, /**< Non-maskable Interrupt (NMI) */
INT_Hard_Fault = 3, /**< Hard Fault */
INT_Mem_Manage_Fault = 4, /**< MemManage Fault */
INT_Bus_Fault = 5, /**< Bus Fault */
INT_Usage_Fault = 6, /**< Usage Fault */
INT_Reserved7 = 7, /**< Reserved interrupt 7 */
INT_Reserved8 = 8, /**< Reserved interrupt 8 */
INT_Reserved9 = 9, /**< Reserved interrupt 9 */
INT_Reserved10 = 10, /**< Reserved interrupt 10 */
INT_SVCall = 11, /**< Supervisor call (SVCall) */
INT_DebugMonitor = 12, /**< Debug Monitor */
INT_Reserved13 = 13, /**< Reserved interrupt 13 */
INT_PendableSrvReq = 14, /**< Pendable request for system service (PendableSrvReq) */
INT_SysTick = 15, /**< SysTick Interrupt */
INT_DMA0_DMA16 = 16, /**< DMA Channel 0, 16 Transfer Complete */
INT_DMA1_DMA17 = 17, /**< DMA Channel 1, 17 Transfer Complete */
INT_DMA2_DMA18 = 18, /**< DMA Channel 2, 18 Transfer Complete */
INT_DMA3_DMA19 = 19, /**< DMA Channel 3, 19 Transfer Complete */
INT_DMA4_DMA20 = 20, /**< DMA Channel 4, 20 Transfer Complete */
INT_DMA5_DMA21 = 21, /**< DMA Channel 5, 21 Transfer Complete */
INT_DMA6_DMA22 = 22, /**< DMA Channel 6, 22 Transfer Complete */
INT_DMA7_DMA23 = 23, /**< DMA Channel 7, 23 Transfer Complete */
INT_DMA8_DMA24 = 24, /**< DMA Channel 8, 24 Transfer Complete */
INT_DMA9_DMA25 = 25, /**< DMA Channel 9, 25 Transfer Complete */
INT_DMA10_DMA26 = 26, /**< DMA Channel 10, 26 Transfer Complete */
INT_DMA11_DMA27 = 27, /**< DMA Channel 11, 27 Transfer Complete */
INT_DMA12_DMA28 = 28, /**< DMA Channel 12, 28 Transfer Complete */
INT_DMA13_DMA29 = 29, /**< DMA Channel 13, 29 Transfer Complete */
INT_DMA14_DMA30 = 30, /**< DMA Channel 14, 30 Transfer Complete */
INT_DMA15_DMA31 = 31, /**< DMA Channel 15, 31 Transfer Complete */
INT_DMA_Error = 32, /**< DMA Error Interrupt */
INT_MCM = 33, /**< Normal Interrupt */
INT_FTFE = 34, /**< FTFE Command complete interrupt */
INT_Read_Collision = 35, /**< Read Collision Interrupt */
INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */
INT_LLW = 37, /**< Low Leakage Wakeup */
INT_Watchdog = 38, /**< WDOG Interrupt */
INT_RNG = 39, /**< RNG Interrupt */
INT_I2C0 = 40, /**< I2C0 interrupt */
INT_I2C1 = 41, /**< I2C1 interrupt */
INT_SPI0 = 42, /**< SPI0 Interrupt */
INT_SPI1 = 43, /**< SPI1 Interrupt */
INT_I2S0_Tx = 44, /**< I2S0 transmit interrupt */
INT_I2S0_Rx = 45, /**< I2S0 receive interrupt */
INT_UART0_LON = 46, /**< UART0 LON interrupt */
INT_UART0_RX_TX = 47, /**< UART0 Receive/Transmit interrupt */
INT_UART0_ERR = 48, /**< UART0 Error interrupt */
INT_UART1_RX_TX = 49, /**< UART1 Receive/Transmit interrupt */
INT_UART1_ERR = 50, /**< UART1 Error interrupt */
INT_UART2_RX_TX = 51, /**< UART2 Receive/Transmit interrupt */
INT_UART2_ERR = 52, /**< UART2 Error interrupt */
INT_UART3_RX_TX = 53, /**< UART3 Receive/Transmit interrupt */
INT_UART3_ERR = 54, /**< UART3 Error interrupt */
INT_ADC0 = 55, /**< ADC0 interrupt */
INT_CMP0 = 56, /**< CMP0 interrupt */
INT_CMP1 = 57, /**< CMP1 interrupt */
INT_FTM0 = 58, /**< FTM0 fault, overflow and channels interrupt */
INT_FTM1 = 59, /**< FTM1 fault, overflow and channels interrupt */
INT_FTM2 = 60, /**< FTM2 fault, overflow and channels interrupt */
INT_CMT = 61, /**< CMT interrupt */
INT_RTC = 62, /**< RTC interrupt */
INT_RTC_Seconds = 63, /**< RTC seconds interrupt */
INT_PIT0 = 64, /**< PIT timer channel 0 interrupt */
INT_PIT1 = 65, /**< PIT timer channel 1 interrupt */
INT_PIT2 = 66, /**< PIT timer channel 2 interrupt */
INT_PIT3 = 67, /**< PIT timer channel 3 interrupt */
INT_PDB0 = 68, /**< PDB0 Interrupt */
INT_USB0 = 69, /**< USB0 interrupt */
INT_USBDCD = 70, /**< USBDCD Interrupt */
INT_Reserved71 = 71, /**< Reserved interrupt 71 */
INT_DAC0 = 72, /**< DAC0 interrupt */
INT_MCG = 73, /**< MCG Interrupt */
INT_LPTimer = 74, /**< LPTimer interrupt */
INT_PORTA = 75, /**< Port A interrupt */
INT_PORTB = 76, /**< Port B interrupt */
INT_PORTC = 77, /**< Port C interrupt */
INT_PORTD = 78, /**< Port D interrupt */
INT_PORTE = 79, /**< Port E interrupt */
INT_SWI = 80, /**< Software interrupt */
INT_SPI2 = 81, /**< SPI2 Interrupt */
INT_UART4_RX_TX = 82, /**< UART4 Receive/Transmit interrupt */
INT_UART4_ERR = 83, /**< UART4 Error interrupt */
INT_Reserved84 = 84, /**< Reserved interrupt 84 */
INT_Reserved85 = 85, /**< Reserved interrupt 85 */
INT_CMP2 = 86, /**< CMP2 interrupt */
INT_FTM3 = 87, /**< FTM3 fault, overflow and channels interrupt */
INT_DAC1 = 88, /**< DAC1 interrupt */
INT_ADC1 = 89, /**< ADC1 interrupt */
INT_I2C2 = 90, /**< I2C2 interrupt */
INT_CAN0_ORed_Message_buffer = 91, /**< CAN0 OR'd message buffers interrupt */
INT_CAN0_Bus_Off = 92, /**< CAN0 bus off interrupt */
INT_CAN0_Error = 93, /**< CAN0 error interrupt */
INT_CAN0_Tx_Warning = 94, /**< CAN0 Tx warning interrupt */
INT_CAN0_Rx_Warning = 95, /**< CAN0 Rx warning interrupt */
INT_CAN0_Wake_Up = 96, /**< CAN0 wake up interrupt */
INT_SDHC = 97, /**< SDHC interrupt */
INT_ENET_1588_Timer = 98, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
INT_ENET_Transmit = 99, /**< Ethernet MAC Transmit Interrupt */
INT_ENET_Receive = 100, /**< Ethernet MAC Receive Interrupt */
INT_ENET_Error = 101, /**< Ethernet MAC Error and miscelaneous Interrupt */
INT_LPUART0 = 102, /**< LPUART0 status/error interrupt */
INT_TSI0 = 103, /**< TSI0 interrupt */
INT_TPM1 = 104, /**< TPM1 fault, overflow and channels interrupt */
INT_TPM2 = 105, /**< TPM2 fault, overflow and channels interrupt */
INT_USBHSDCD = 106, /**< USBHSDCD, USBHS Phy Interrupt */
INT_I2C3 = 107, /**< I2C3 interrupt */
INT_CMP3 = 108, /**< CMP3 interrupt */
INT_USBHS = 109, /**< USB high speed OTG interrupt */
INT_CAN1_ORed_Message_buffer = 110, /**< CAN1 OR'd message buffers interrupt */
INT_CAN1_Bus_Off = 111, /**< CAN1 bus off interrupt */
INT_CAN1_Error = 112, /**< CAN1 error interrupt */
INT_CAN1_Tx_Warning = 113, /**< CAN1 Tx warning interrupt */
INT_CAN1_Rx_Warning = 114, /**< CAN1 Rx warning interrupt */
INT_CAN1_Wake_Up = 115 /**< CAN1 wake up interrupt */
} IRQInterruptIndex;
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
#endif

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/*
* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BOOTLOADER_CONFIG_H__
#define __BOOTLOADER_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//
// Bootloader configuration options
//
//! @name Peripheral configuration macros
//@{
#if !defined(BL_CONFIG_SCUART)
#define BL_CONFIG_SCUART (1)
#endif
#if !defined(BL_CONFIG_I2C)
#define BL_CONFIG_I2C (1)
#endif
#if !defined(BL_CONFIG_DSPI)
#define BL_CONFIG_DSPI (1)
#endif
/* Either FS USB or HS USB to be enabled, not both are enabled at the same time.
* HS USB is not supported in flashloader build, due to extral dependence. */
#if !defined(BL_CONFIG_USB_HID)
#define BL_CONFIG_USB_HID (1)
#endif
#if !defined(BL_CONFIG_USB_MSC)
#define BL_CONFIG_USB_MSC (1)
#endif
#if !defined(BL_CONFIG_HS_USB_HID)
#define BL_CONFIG_HS_USB_HID (0) // For TOWER and FRDM boards
#endif
#if !defined(BL_CONFIG_HS_USB_MSC)
#define BL_CONFIG_HS_USB_MSC (0) // For TOWER and FRDM boards
#endif
//@}
#if !defined(BL_TARGET_FLASH) && !defined(BL_TARGET_RAM)
#define BL_TARGET_FLASH (1)
#endif
#if defined(BL_TARGET_RAM)
#define BL_FEATURE_FLASH_SECURITY (0)
#else
#define BL_FEATURE_FLASH_SECURITY (1)
#endif
#if !defined(BL_TARGET_RAM)
#define BL_FEATURE_CRC_CHECK (1)
#endif
#define BL_FEATURE_QSPI_MODULE (0)
#define BL_FEATURE_ENCRYPTION_MMCAU (1)
#define BL_FEATURE_ENCRYPTION (BL_FEATURE_ENCRYPTION_MMCAU)
#define BL_FEATURE_ENCRYPTION_KEY_ADDRESS 0xb000 // NOTE: this address must be 4-byte aligned.
#define BL_FEATURE_UART_AUTOBAUD_IRQ (1)
// Bootloader peripheral detection default timeout in milliseconds
// After coming out of reset the bootloader will spin in a peripheral detection
// loop for this amount of time. A zero value means no time out.
#if DEBUG
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 0
#else
#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 5000
#endif // DEBUG
#define BL_FEATURE_POWERDOWN (0)
// Bootloader powerdown timeout in milliseconds
// The bootloader enters a low power mode after waiting for this amount of time. A zero value means // no time out. Only
// applicable if BL_FEATURE_POWERDOWN is enabled.
#if DEBUG
#define BL_DEFAULT_POWERDOWN_TIMEOUT 10000
#else
#define BL_DEFAULT_POWERDOWN_TIMEOUT 600000
#endif // DEBUG
// The bootloader will check this address for the application vector table upon startup.
#if !defined(BL_APP_VECTOR_TABLE_ADDRESS)
#define BL_APP_VECTOR_TABLE_ADDRESS 0xa000
#endif
/* Backup application Info */
#if !defined(BL_TARGET_RAM)
#define BL_FEATURE_RELIABLE_UPDATE (1)
#define BL_FEATURE_HARDWARE_SWAP_UPDATE (1)
// Note the BAKCUP APP START address must be sector-aligned.
#define BL_BACKUP_APP_START (0x105000)
#endif // BL_TARGET_RAM
#define BL_FEATURE_ENABLE_FLASH_PROGRAM_SECTION (1)
/* Serial Port Info */
/**************************************************************************
* Note:
*
* Because of the changes to the UART modules, we can no longer define
* the TERM_PORT as a base pointer. The uart functions have been modified
* accommodate this change. Now, TERM_PORT_NUM must be defined as the
* number of the UART port desired to use
*
* TERM_PORT_NUM = 0 -- This allows you to use UART0; default pins are
* PTA14 and PTA15
*
* TERM_PORT_NUM = 1 -- This allows you to use UART1; default pins are
* PTC3 and PTC4
*
* TERM_PORT_NUM = 2 -- This allows you to use UART2; default pins are
* PTD2 and PTD3
*
*************************************************************************/
#define TERM_PORT_NUM 0
#define TERMINAL_BAUD 19200
#undef HW_FLOW_CONTROL
#endif // __BOOTLOADER_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bootloader.h"
#include "bootloader_tree_MK65F18.h"
// Followings should be in a SDK driver header file and included by application
status_t DSPI_DRV_SlaveTransferBlocking(const peripheral_descriptor_t *self, const uint8_t *buffer, uint32_t byteCount);
status_t I2C_DRV_SlaveTransferBlocking(const peripheral_descriptor_t *self, const uint8_t *buffer, uint32_t byteCount);
// Should be defined in each SOC's header file
#define BOOTLOADER_TREE_ENTRY 0x0000001c
// Cast it to bootloader_tree_t pointer
#define bootloader_tree_entry (uint32_t *)(BOOTLOADER_TREE_ENTRY)
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
status_t DSPI_DRV_SlaveTransferBlocking(const peripheral_descriptor_t *self, const uint8_t *buffer, uint32_t byteCount)
{
return (((bootloader_tree_t *)(*bootloader_tree_entry))->dspi_write)(self, buffer, byteCount);
}
status_t I2C_DRV_SlaveTransferBlocking(const peripheral_descriptor_t *self, const uint8_t *buffer, uint32_t byteCount)
{
return (((bootloader_tree_t *)(*bootloader_tree_entry))->i2c_write)(self, buffer, byteCount);
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bootloader.h"
#include "drivers/flash/fsl_flash.h"
typedef struct BootloaderTree
{
/* General information */
void (*runBootloader)(void *arg); //!< Function to start the bootloader executing.
standard_version_t version; //!< Bootloader version number.
const char *copyright; //!< Copyright string.
/* Flash driver APIs */
standard_version_t flash_version; //!< flash driver API version number.
status_t (*flash_init)(flash_driver_t *driver);
status_t (*flash_erase_all)(flash_driver_t *driver, uint32_t key);
status_t (*flash_erase_all_unsecure)(flash_driver_t *driver, uint32_t key);
status_t (*flash_erase)(flash_driver_t *driver, uint32_t start, uint32_t lengthInBytes, uint32_t key);
status_t (*flash_program)(flash_driver_t *driver, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
status_t (*flash_get_security_state)(flash_driver_t *driver, flash_security_state_t *state);
status_t (*flash_security_bypass)(flash_driver_t *driver, const uint8_t *backdoorKey);
status_t (*flash_verify_erase_all)(flash_driver_t *driver, flash_margin_value_t margin);
status_t (*flash_verify_erase)(flash_driver_t *driver,
uint32_t start,
uint32_t lengthInBytes,
flash_margin_value_t margin);
status_t (*flash_verify_program)(flash_driver_t *driver,
uint32_t start,
uint32_t lengthInBytes,
const uint8_t *expectedData,
flash_margin_value_t margin,
uint32_t *failedAddress,
uint32_t *failedData);
status_t (*flash_get_property)(flash_driver_t *driver, flash_property_t whichProperty, uint32_t *value);
status_t (*flash_register_callback)(flash_driver_t *driver, flash_callback_t callback);
status_t (*flash_program_once)(flash_driver_t *driver, uint32_t index, uint32_t *src, uint32_t lengthInBytes);
status_t (*flash_read_once)(flash_driver_t *driver, uint32_t index, uint32_t *dst, uint32_t lengthInBytes);
status_t (*flash_read_resource)(flash_driver_t *driver,
uint32_t start,
uint32_t *dst,
uint32_t lengthInBytes,
flash_read_resource_option_t option);
status_t (*flash_prepare_execute_in_ram_functions)(flash_driver_t *driver);
/* AES APIs */
void (*aes_init)(uint32_t *key);
void (*aes_encrypt)(uint32_t *in, uint32_t *key, uint32_t *out);
void (*aes_decrypt)(uint32_t *in, uint32_t *key, uint32_t *out);
/* Peripherals APIs */
status_t (*dspi_write)(const peripheral_descriptor_t *self, const uint8_t *buffer, uint32_t byteCount);
status_t (*i2c_write)(const peripheral_descriptor_t *self, const uint8_t *buffer, uint32_t byteCount);
} bootloader_tree_t;
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bootloader.h"
#include "bootloader_tree_MK65F18.h"
#include "drivers/flash/fsl_flash.h"
#if BL_FEATURE_ENCRYPTION
#include "security/aes_security.h"
#endif // #if BL_FEATURE_ENCRYPTION
// Shoudl be put into some header files.
extern status_t dspi_write(const peripheral_descriptor_t *self, const uint8_t *buffer, uint32_t byteCount);
extern status_t i2c_write(const peripheral_descriptor_t *self, const uint8_t *buffer, uint32_t byteCount);
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
const char bootloaderCopyright[] = "Copyright (c) 2013-2014 Freescale Semiconductor, Inc. All rights reserved.";
const bootloader_tree_t g_bootloaderTree = {
.runBootloader = bootloader_user_entry,
.version = {.name = kBootloader_Version_Name,
.major = kBootloader_Version_Major,
.minor = kBootloader_Version_Minor,
.bugfix = kBootloader_Version_Bugfix },
.copyright = bootloaderCopyright,
.flash_version = {.name = kFlashDriver_Version_Name,
.major = kFlashDriver_Version_Major,
.minor = kFlashDriver_Version_Minor,
.bugfix = kFlashDriver_Version_Bugfix },
.flash_init = flash_init,
.flash_erase_all = flash_erase_all,
.flash_erase_all_unsecure = flash_erase_all_unsecure,
.flash_erase = flash_erase,
.flash_program = flash_program,
.flash_get_security_state = flash_get_security_state,
.flash_security_bypass = flash_security_bypass,
.flash_verify_erase_all = flash_verify_erase_all,
.flash_verify_erase = flash_verify_erase,
.flash_verify_program = flash_verify_program,
.flash_get_property = flash_get_property,
.flash_register_callback = flash_register_callback,
#if !BL_FEATURE_MIN_PROFILE
.flash_program_once = flash_program_once,
.flash_read_once = flash_read_once,
.flash_read_resource = flash_read_resource,
#else
.flash_program_once = NULL,
.flash_read_once = NULL,
.flash_read_resource = NULL,
#endif
#if BL_TARGET_FLASH
.flash_prepare_execute_in_ram_functions = flash_prepare_execute_in_ram_functions,
#else
.flash_prepare_execute_in_ram_functions = NULL,
#endif
#if AES_SECURITY_SUPPORTED
.aes_init = aes_init,
.aes_encrypt = aes_encrypt,
.aes_decrypt = aes_decrypt
#else
.aes_init = NULL,
.aes_encrypt = NULL,
.aes_decrypt = NULL,
#endif
.dspi_write = dspi_write,
.i2c_write = i2c_write,
};
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h"
#include "bootloader/bl_context.h"
#include "property/property.h"
#include "fsl_device_registers.h"
#include <assert.h>
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
// Clock mode types
typedef enum _target_clock_mode
{
kClockMode_FEI = 0,
kClockMode_FEE = 1,
kClockMode_FBI = 2,
kClockMode_FBE = 3,
kClockMode_PEE = 4,
kClockMode_PBE = 5,
kClockMode_Default = kClockMode_FEI,
} target_clock_mode_t;
////////////////////////////////////////////////////////////////////////////////
// Prototypes
////////////////////////////////////////////////////////////////////////////////
// This function implements clock mode switch between FEI and PEE mode used in this bootloader
void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode);
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
// See bootloader_common.h for documentation on this function.
void configure_clocks(bootloader_clock_option_t option)
{
#if 0
static uint32_t s_defaultClockDivider;
static target_clock_mode_t s_currentClockMode = kClockMode_FEI;
if (option == kClockOption_EnterBootloader)
{
s_defaultClockDivider = SIM->CLKDIV1;
// General procedure to be implemented:
// 1. Read clock flags and divider from bootloader config in property store
bootloader_configuration_data_t * config = &g_bootloaderContext.propertyInterface->store->configurationData;
uint8_t options = config->clockFlags;
// Check if the USB HID peripheral is enabled. If it is enabled, we always
// use the 48MHz IRC.
bool isUsbEnabled = config->enabledPeripherals & kPeripheralType_USB_HID;
// 2. If NOT High Speed, do nothing (use reset clock config)
if ((!isUsbEnabled) && (options & kClockFlag_HighSpeed) )
{
// High speed flag is set (meaning disabled), so just use default clocks.
SystemCoreClock = kDefaultClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1);
return;
}
// 3. Set OUTDIV1 based on divider in config. OUTDIV4 starts out at /1.
// The divider values are masked by the maximum bits per divider.
uint32_t div1 = ((~config->clockDivider) & (SIM_CLKDIV1_OUTDIV1_MASK >> SIM_CLKDIV1_OUTDIV1_SHIFT)) + 1;
// 4. Get MCGOUTCLK
uint32_t McgOutClk = kMcgOutWithHighSpeedUsb;
// 5. Bypass core clock divider when HighSpeed USB is enabled.
div1 = 1;
// 6. Keep core clock below kMaxCoreClock
uint32_t freq = McgOutClk;
while ((freq / div1) > kMaxCoreClock)
{
++div1;
}
assert((div1 >= kDivider_Min) && (div1 <= kDivider_Max));
uint32_t div2 = div1;
uint32_t div3 = div1;
uint32_t div4 = div1;
// 7. Keep bus freq below max.
//
// The bus clock is divided by OUTDIV2:
// MCGOUTCLK -> OUTDIV2 -> bus_clk
freq = McgOutClk;
while ((freq / div2) > kMaxBusClock)
{
// Increase bus clock divider.
++div2;
}
assert((div2 >= kDivider_Min) && (div2 <= kDivider_Max));
// 8. Keep flexbus clock below kMaxFlexBusClock
//
// MCGOUTCLK -> OUTDIV3 -> flexbus_clk
freq = McgOutClk;
while ((freq / div3) > kMaxFlexBusClock)
{
// Increase flexbus clock divider.
++div3;
}
assert((div3 >= kDivider_Min) && (div2 <= kDivider_Max));
// 9. Keep flash freq below max.
//
// The flash clock is diveded by OUTDIV4:
// MCGOUTCLK -> OUTDIV4 ->flash_clk
freq = McgOutClk;
while ((freq / div4) > kMaxFlashClock)
{
// Increase bus/flash clock divider.
++div4;
}
assert((div4 >= kDivider_Min) && (div4 <= kDivider_Max));
if((div1 == 1) && ((div2 > 8) || (div3 > 8) || (div4 > 8)))
{
return;
}
//10. Now set the dividers
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(div1 - 1) |
SIM_CLKDIV1_OUTDIV2(div2 - 1) |
SIM_CLKDIV1_OUTDIV2(div3 - 1) |
SIM_CLKDIV1_OUTDIV4(div4 - 1); // Update system prescalers
//11. Update SystemCoreClock global.
SystemCoreClock = McgOutClk / div1;
// 12. Change clock mode.
clock_mode_switch(s_currentClockMode, kClockMode_PEE);
s_currentClockMode = kClockMode_PEE;
// Change the Clock source to PLL because MCG switches from FEI to PEE mode
uint32_t tmp = SIM->SOPT2;
tmp &= (uint32_t)~SIM_SOPT2_PLLFLLSEL_MASK;
tmp |= SIM_SOPT2_PLLFLLSEL(1);
SIM->SOPT2 = tmp;
}
else if (option == kClockOption_ExitBootloader)
{
clock_mode_switch(s_currentClockMode, kClockMode_FEI);
SIM->CLKDIV1 = s_defaultClockDivider;
}
#endif
}
void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode)
{
// Note: here only implements clock switch between FEI and PEE,
// The other modes are not supported.
assert(currentMode == kClockMode_FEI || currentMode == kClockMode_FEE || currentMode == kClockMode_PEE);
assert(expectedMode == kClockMode_FEI || expectedMode == kClockMode_FEE || expectedMode == kClockMode_PEE);
if (currentMode == expectedMode)
{
return;
}
if (expectedMode == kClockMode_PEE)
{
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* PORTA->PCR18: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA->PCR19: ISF=0,MUX=0 */
PORTA->PCR[19] &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
MCG->SC = 0;
/* Switch to FBE Mode */
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = (uint8_t)0x80U;
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x24U;
/* MCG->C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0xA2U;
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t) ~(uint8_t)0xE0U;
/* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
MCG->C5 = (uint8_t)0x01U;
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00U;
while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) /* Wait until the oscillator is ready */
{
}
while ((MCG->S & MCG_S_IREFST_MASK) != 0x00U)
{ /* Check that the source of the FLL reference clock is the external reference clock. */
}
while ((MCG->S & 0x0CU) != 0x08U)
{ /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=14 */
MCG->C6 = (uint8_t)0x4EU;
while ((MCG->S & 0x0CU) != 0x08U)
{ /* Wait until external reference clock is selected as MCG output */
}
while ((MCG->S & MCG_S_LOCK0_MASK) == 0x00U)
{ /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG->C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 &= (uint8_t) ~(MCG_C1_CLKS_MASK);
while ((MCG->S & 0x0CU) != 0x0CU)
{ /* Wait until output of the PLL is selected */
}
while (MCG->S2 != 0)
{ /* Wait until output of the correct PLL is selected */
}
}
else if (expectedMode == kClockMode_FEI)
{
/* Switch to PBE mode */
uint8_t tmp = MCG->C1;
tmp &= (uint8_t) ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK);
tmp |= MCG_C1_CLKS(0x02);
MCG->C1 = tmp;
MCG->C6 |= MCG_C6_PLLS_MASK;
MCG->C2 &= (uint8_t)~MCG_C2_LP_MASK;
while ((MCG->S & 0x0CU) != 0x08U) /* Wait until external reference clock is selected */
{
}
/* Switch to FBE mode */
MCG->C1 |= MCG_C1_FRDIV(3);
MCG->C6 &= ~(MCG_C6_PLLS_MASK);
while ((MCG->S & MCG_S_PLLST_MASK) != 0x00U) /* Wait until source of PLLS clock is FLL clock */
{
}
/* Switch to FEI mode */
MCG->C1 |= ~(MCG_C1_CLKS_MASK);
MCG->C1 |= MCG_C1_IREFS(1);
while ((MCG->S & MCG_S_IREFST_MASK) == 0x0U)
{
}
while ((MCG->S & 0x0CU) != 0x00U) /* Wait until output of FLL is selected */
{
}
OSC->CR = (uint8_t)0x0U;
while ((MCG->S & MCG_S_OSCINIT0_MASK) != 0x00U) /* Wait until OSC is off */
{
}
/* Restore Registers */
/* MCG->C2: LOCRE0=1,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x80U;
MCG->C1 = (uint8_t)0x04U;
MCG->C5 = (uint8_t)0x00U;
}
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader_common.h"
#include "bootloader/bl_context.h"
#include "fsl_device_registers.h"
#include "uart/fsl_uart.h"
#include "utilities/kinetis_family.h"
#include "smc/smc.h"
#include "usb_device_config.h"
#include "usb.h"
#include "microseconds/microseconds.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
#if defined TOWER || defined FREEDOM
#define BOOT_PIN_NUMBER 10
#define BOOT_PIN_PORT PORTA
#define BOOT_PIN_GPIO GPIOA
#define BOOT_PIN_ALT_MODE 1
#endif
#define BOOT_PIN_DEBOUNCE_READ_COUNT 500
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void init_hardware(void)
{
exit_vlpr();
// Disable the MPU otherwise USB cannot access the bus
MPU->CESR = 0;
// Enable all the ports
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
SIM_SCGC5_PORTE_MASK);
}
void deinit_hardware(void)
{
SIM->SCGC5 &= (uint32_t) ~(SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
// Restore SIM_SOPTx related bits being changed
SIM->SOPT1 &= (uint32_t)~SIM_SOPT1_USBREGEN_MASK;
SIM->SOPT2 &= (uint32_t) ~(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
}
// Note: Keep this function here to ensure compatibility, all usb related clock
// configuration is maintained by USB stack itself.
bool usb_clock_init(void)
{
#if ((BL_CONFIG_USB_HID) || (BL_CONFIG_USB_MSC))
SIM->CLKDIV2 = (uint32_t)0x0UL; /* Update USB clock prescalers */
// Select IRC48M clock
SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
// Enable USB-OTG IP clocking
SIM->SCGC4 |= (SIM_SCGC4_USBOTG_MASK);
// Configure enable USB regulator for device
SIM->SOPT1 |= SIM_SOPT1_USBREGEN_MASK;
/* SIM_SOPT1: OSC32KSEL=0 */
SIM->SOPT1 &=
(uint32_t)~SIM_SOPT1_OSC32KSEL_MASK; /* System oscillator drives 32 kHz clock for various peripherals */
USB0->CLK_RECOVER_IRC_EN = 0x03;
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
USB0->CLK_RECOVER_CTRL |= 0x20;
#endif
#if ((BL_CONFIG_HS_USB_HID) || (BL_CONFIG_HS_USB_MSC))
MCG->C1 |= MCG_C1_IRCLKEN_MASK; // 32kHz IRC enable
OSC->CR |= OSC_CR_ERCLKEN_MASK; // external reference clock enable
// Configure EXT_PLL from USB HS PHY
SIM->SOPT2 |= SIM_SOPT2_USBREGEN_MASK; // | SIM_SOPT2_PLLFLLSEL(2); //enable USB PHY PLL regulator, needs to be
// enabled before enable PLL
SIM->SCGC3 |= SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK; // open HS USB PHY clock gate
microseconds_delay(1000);
SIM->USBPHYCTL =
SIM_USBPHYCTL_USB3VOUTTRG(6) | SIM_USBPHYCTL_USBVREGSEL_MASK; // trim the USB regulator output to be 3.13V
USBPHY->TRIM_OVERRIDE_EN = 0x001f; // override IFR value
USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; // power up PLL
if (BOARD_XTAL0_CLK_HZ == 24000000)
USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(0);
else if (BOARD_XTAL0_CLK_HZ == 16000000)
USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(1);
else if (BOARD_XTAL0_CLK_HZ == 12000000)
USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(2);
USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; // clear bypass bit
USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; // enable USB clock output from USB PHY PLL
while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
;
USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; // release PHY from reset
USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; // Clear to 0 to run clocks
USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
USBPHY->PWD = 0; // for normal operation
USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); // N=24
USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(4); // div by 4
USBPHY->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK;
USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
while (!(USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
{
}
USBPHY->TX |= 1 << 24;
USBHS->USBCMD |= USBHS_USBCMD_RST_MASK;
while (USBHS->USBCMD & USBHS_USBCMD_RST_MASK)
{ /* delay while resetting USB controller */
}
USBHS->USBMODE = USBHS_USBMODE_CM(2);
/* Set interrupt threshold control = 0 */
// USBHS_USBCMD &= ~( USBHS_USBCMD_ITC(0xFF));
/* Setup Lockouts Off */
// USBHS_USBMODE |= USBHS_USBMODE_SLOM_MASK;
#endif
return true;
}
uint32_t get_bus_clock(void)
{
uint32_t busClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1;
return (SystemCoreClock / busClockDivider);
}
// Return specified UART clock
// Note: LPUART0 is not supported here.
uint32_t get_uart_clock(uint32_t instance)
{
switch (instance)
{
case 0:
case 1:
// UART0 and UART1 always use the system clock
return SystemCoreClock;
case 2:
return get_bus_clock();
case 3:
case 4:
// UART2-4 always use the bus clock.
return get_bus_clock();
default:
return 0;
}
}
bool is_boot_pin_asserted(void)
{
#ifdef BL_TARGET_FLASH
// Initialize boot pin for GPIO
BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= PORT_PCR_MUX(BOOT_PIN_ALT_MODE);
// Set boot pin as an input
BOOT_PIN_GPIO->PDDR &= (uint32_t) ~(1 << BOOT_PIN_NUMBER);
// Set boot pin pullup enabled, pullup select, filter enable
BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_PFE_MASK);
uint32_t readCount = 0;
// Sample the pin a number of times
for (uint32_t i = 0; i < BOOT_PIN_DEBOUNCE_READ_COUNT; i++)
{
readCount += ((BOOT_PIN_GPIO->PDIR) >> BOOT_PIN_NUMBER) & 1;
}
// boot pin is pulled high so we are measuring lows, make sure most of our measurements
// registered as low
return (readCount < (BOOT_PIN_DEBOUNCE_READ_COUNT / 2));
#else
// Boot pin for Flash only target
return false;
#endif
}
void debug_init(void)
{
}
#if __ICCARM__
size_t __write(int handle, const unsigned char *buf, size_t size)
{
return size;
}
#endif // __ICCARM__
void update_available_peripherals()
{
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "memory/memory.h"
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
//! @brief Memory map for K60-2M (K65/K66)
//!
//! This map is not const because it is updated at runtime with the actual sizes of
//! flash and RAM for the chip we're running on.
memory_map_entry_t g_memoryMap[] = {
{ 0x00000000, 0x001fffff, kMemoryIsExecutable, &g_flashMemoryInterface }, // Flash array (2MB)
{ 0x1fff0000, 0x2002ffff, kMemoryIsExecutable, &g_normalMemoryInterface }, // SRAM (256KB)
{ 0x40000000, 0x4007ffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS peripherals
{ 0x400ff000, 0x400fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // GPIO
{ 0xe0000000, 0xe00fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // M4 private peripherals
{ 0 } // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bootloader/bl_context.h"
#include "bootloader/bl_peripheral_interface.h"
#include "packet/serial_packet.h"
extern void uart_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void i2c_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
extern void spi_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
#if !BL_CONFIG_SCUART && !BL_CONFIG_I2C && !BL_CONFIG_DSPI && !BL_CONFIG_USB_HID && !BL_CONFIG_HS_USB_HID && \
!BL_CONFIG_USB_MSC && !BL_CONFIG_HS_USB_MSC
#error At least one peripheral must be enabled!
#endif
//! @brief Peripheral array for K22F5256.
const peripheral_descriptor_t g_peripherals[] = {
#if BL_CONFIG_SCUART
#ifdef TOWER
// UART2
{.typeMask = kPeripheralType_UART,
.instance = 2,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_scuartControlInterface,
.byteInterface = &g_scuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#elif defined FREEDOM
// UART0
{.typeMask = kPeripheralType_UART,
.instance = 0,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_scuartControlInterface,
.byteInterface = &g_scuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#else
// UART4
{.typeMask = kPeripheralType_UART,
.instance = 4,
.pinmuxConfig = uart_pinmux_config,
.controlInterface = &g_scuartControlInterface,
.byteInterface = &g_scuartByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // defined TOWER
#endif // BL_CONFIG_SCUART
#if BL_CONFIG_I2C
#if defined FREEDOM
// I2C1
{.typeMask = kPeripheralType_I2CSlave,
.instance = 1,
.pinmuxConfig = i2c_pinmux_config,
.controlInterface = &g_i2cControlInterface,
.byteInterface = &g_i2cByteInterface,
.packetInterface = &g_framingPacketInterface },
#else
// I2C0
{.typeMask = kPeripheralType_I2CSlave,
.instance = 0,
.pinmuxConfig = i2c_pinmux_config,
.controlInterface = &g_i2cControlInterface,
.byteInterface = &g_i2cByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // FREEDOM
#endif // BL_CONFIG_I2C
#if BL_CONFIG_DSPI
#if defined FREEDOM
// SPI0
{.typeMask = kPeripheralType_SPISlave,
.instance = 0,
.pinmuxConfig = spi_pinmux_config,
.controlInterface = &g_dspiControlInterface,
.byteInterface = &g_dspiByteInterface,
.packetInterface = &g_framingPacketInterface },
#else
// SPI1
{.typeMask = kPeripheralType_SPISlave,
.instance = 2,
.pinmuxConfig = spi_pinmux_config,
.controlInterface = &g_dspiControlInterface,
.byteInterface = &g_dspiByteInterface,
.packetInterface = &g_framingPacketInterface },
#endif // FREEDOM
#endif // BL_CONFIG_DSPI
#if (BL_CONFIG_USB_HID || BL_CONFIG_USB_MSC)
// USB HID - Full speed
{.typeMask = kPeripheralType_USB_HID,
.instance = 0,
.pinmuxConfig = NULL,
.controlInterface = &g_usbHidControlInterface,
.byteInterface = NULL,
.packetInterface = &g_usbHidPacketInterface },
#endif // BL_CONFIG_USB_HID
#if (BL_CONFIG_HS_USB_HID || BL_CONFIG_HS_USB_MSC)
// USB HID - High speed
{.typeMask = kPeripheralType_USB_HID,
.instance = 2,
.pinmuxConfig = NULL,
.controlInterface = &g_usbHidControlInterface,
.byteInterface = NULL,
.packetInterface = &g_usbHidPacketInterface },
#endif // BL_CONFIG_HS_USB_HID
{ 0 } // Terminator
};
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! peripheral enable configurations
#if defined(TOWER)
#define BL_ENABLE_PINMUX_UART2 (BL_CONFIG_SCUART)
#define BL_ENABLE_PINMUX_I2C0 (BL_CONFIG_I2C)
#define BL_ENABLE_PINMUX_SPI2 (BL_CONFIG_DSPI)
#elif defined FREEDOM
#define BL_ENABLE_PINMUX_UART0 (BL_CONFIG_SCUART)
#define BL_ENABLE_PINMUX_I2C1 (BL_CONFIG_I2C)
#define BL_ENABLE_PINMUX_SPI0 (BL_CONFIG_DSPI)
#else
#define BL_ENABLE_PINMUX_UART4 (BL_CONFIG_SCUART)
#define BL_ENABLE_PINMUX_I2C0 (BL_CONFIG_I2C)
#define BL_ENABLE_PINMUX_SPI2 (BL_CONFIG_DSPI)
#endif // TOWER
//! UART pinmux configurations
#if defined(TOWER) // TWR board and tower_bootloader
#define UART2_RX_PORT_BASE PORTE
#define UART2_RX_GPIO_BASE PTE
#define UART2_RX_GPIO_PIN_NUM 17 // PTE17
#define UART2_RX_FUNC_ALT_MODE 3 // ALT mode for UART1 RX functionality
#define UART2_RX_GPIO_ALT_MODE 1 // ALT mdoe for GPIO functionality
#define UART2_RX_GPIO_IRQn PORTE_IRQn
#define UART2_RX_GPIO_IRQHandler PORTE_IRQHandler
#define UART2_TX_PORT_BASE PORTE
#define UART2_TX_GPIO_PIN_NUM 16 // PTE16
#define UART2_TX_FUNC_ALT_MODE 3 // ALT mode for UART1 TX functionality
#elif defined(FREEDOM)
#define UART0_RX_PORT_BASE PORTB
#define UART0_RX_GPIO_BASE PTB
#define UART0_RX_GPIO_PIN_NUM 16 // PTB16
#define UART0_RX_FUNC_ALT_MODE 3 // ALT mode for UART1 RX functionality
#define UART0_RX_GPIO_ALT_MODE 1 // ALT mdoe for GPIO functionality
#define UART0_RX_GPIO_IRQn PORTB_IRQn
#define UART0_RX_GPIO_IRQHandler PORTB_IRQHandler
#define UART0_TX_PORT_BASE PORTB
#define UART0_TX_GPIO_PIN_NUM 17 // PTB17
#define UART0_TX_FUNC_ALT_MODE 3 // ALT mode for UART1 TX functionality
#else // flashloader
#define UART4_RX_PORT_BASE PORTE
#define UART4_RX_GPIO_BASE PTE
#define UART4_RX_GPIO_PIN_NUM 25 // PTE25
#define UART4_RX_FUNC_ALT_MODE 3 // ALT mode for UART1 RX functionality
#define UART4_RX_GPIO_ALT_MODE 1 // ALT mdoe for GPIO functionality
#define UART4_RX_GPIO_IRQn PORTE_IRQn
#define UART4_RX_GPIO_IRQHandler PORTE_IRQHandler
#define UART4_TX_PORT_BASE PORTE
#define UART4_TX_GPIO_PIN_NUM 24 // PTE24
#define UART4_TX_FUNC_ALT_MODE 3 // ALT mode for UART1 TX functionality
#endif // TOWER
//! I2C pinmux configurations
#if defined FREEDOM
#define I2C1_SCL_PORT_BASE PORTC
#define I2C1_SCL_GPIO_PIN_NUM 10 // PTC10
#define I2C1_SCL_FUNC_ALT_MODE 2 // ALT mode for I2C1 SCL functionality
#define I2C1_SDA_PORT_BASE PORTC
#define I2C1_SDA_GPIO_PIN_NUM 11 // PTC11
#define I2C1_SDA_FUNC_ALT_MODE 2 // ALT mode for I2C1 SDA functionality
#else
#define I2C0_SCL_PORT_BASE PORTD
#define I2C0_SCL_GPIO_PIN_NUM 8 // PTD8
#define I2C0_SCL_FUNC_ALT_MODE 2 // ALT mode for I2C1 SCL functionality
#define I2C0_SDA_PORT_BASE PORTD
#define I2C0_SDA_GPIO_PIN_NUM 9 // PTD9
#define I2C0_SDA_FUNC_ALT_MODE 2 // ALT mode for I2C1 SDA functionality
#endif // FREEDOM
//! SPI pinmux configurations
#if defined FREEDOM
#define SPI0_PCS_PORT_BASE PORTD
#define SPI0_PCS_GPIO_PIN_NUM 0 // PTD0
#define SPI0_PCS_FUNC_ALT_MODE 2 // ALT mode for SPI1 PCS functionality
#define SPI0_SCK_PORT_BASE PORTD
#define SPI0_SCK_GPIO_PIN_NUM 1 // PTD1
#define SPI0_SCK_FUNC_ALT_MODE 2 // ALT mode for SPI1 SCK functionality
#define SPI0_SOUT_PORT_BASE PORTD
#define SPI0_SOUT_GPIO_PIN_NUM 2 // PTD2
#define SPI0_SOUT_FUNC_ALT_MODE 2 // ALT mode for SPI1 SOUT functionality
#define SPI0_SIN_PORT_BASE PORTD
#define SPI0_SIN_GPIO_PIN_NUM 3 // PTD3
#define SPI0_SIN_FUNC_ALT_MODE 2 // ALT mode for SPI1 SIN functionality
#else
#define SPI2_PCS_PORT_BASE PORTD
#define SPI2_PCS_GPIO_PIN_NUM 11 // PTD11
#define SPI2_PCS_FUNC_ALT_MODE 2 // ALT mode for SPI1 PCS functionality
#define SPI2_SCK_PORT_BASE PORTD
#define SPI2_SCK_GPIO_PIN_NUM 12 // PTD12
#define SPI2_SCK_FUNC_ALT_MODE 2 // ALT mode for SPI1 SCK functionality
#define SPI2_SOUT_PORT_BASE PORTD
#define SPI2_SOUT_GPIO_PIN_NUM 13 // PTD13
#define SPI2_SOUT_FUNC_ALT_MODE 2 // ALT mode for SPI1 SOUT functionality
#define SPI2_SIN_PORT_BASE PORTD
#define SPI2_SIN_GPIO_PIN_NUM 14 // PTD14
#define SPI2_SIN_FUNC_ALT_MODE 2 // ALT mode for SPI1 SIN functionality
#endif
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
** ###################################################################
** Processors: MK65FN2M0CAC18
** MK65FN2M0VMI18
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K65P169M180SF5RMV2, Rev. 1, Mar 2015
** Version: rev. 3.0, 2015-03-25
** Build: b150325
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-09-02)
** Initial version.
** - rev. 2.0 (2014-02-17)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** Update according to reference manual rev. 2
** - rev. 2.1 (2014-04-16)
** Update of SystemInit() and SystemCoreClockUpdate() functions.
** - rev. 2.2 (2014-10-14)
** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
** - rev. 2.3 (2014-11-20)
** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
** Update of SystemInit() to use 16MHz external crystal.
** - rev. 2.4 (2015-02-19)
** Renamed interrupt vector LLW to LLWU.
** - rev. 3.0 (2015-03-25)
** Registers updated according to the reference manual revision 1, March 2015
**
** ###################################################################
*/
/*!
* @file MK65F18
* @version 3.0
* @date 2015-03-25
* @brief Device specific configuration file for MK65F18 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_MK65F18_H_
#define _SYSTEM_MK65F18_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
#ifndef CLOCK_SETUP
#if (TOWER || FREEDOM)
#define CLOCK_SETUP 4
#else
#define CLOCK_SETUP 0
#endif // TOWER
#endif // #ifndef CLOCK_SETUP
/* MCG mode constants */
#define MCG_MODE_FEI 0U
#define MCG_MODE_FBI 1U
#define MCG_MODE_BLPI 2U
#define MCG_MODE_FEE 3U
#define MCG_MODE_FBE 4U
#define MCG_MODE_BLPE 5U
#define MCG_MODE_PBE 6U
#define MCG_MODE_PEE 7U
/* Predefined clock setups
0 ... Default part configuration
Multipurpose Clock Generator (MCG) in FEI mode.
Reference clock source for MCG module: Slow internal reference clock
Core clock = 20.97152MHz
Bus clock = 20.97152MHz
1 ... Maximal speed configuration
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 180MHz
Bus clock = 60MHz
2 ... Chip internally clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPI mode.
Reference clock source for MCG module: Fast internal reference clock
Core clock = 4MHz
Bus clock = 4MHz
3 ... Chip externally clocked, ready for Very Low Power Run mode.
Multipurpose Clock Generator (MCG) in BLPE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 4MHz
Bus clock = 4MHz
4 ... USB clock setup
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 120MHz
Bus clock = 60MHz
5 ... Maximum achievable clock frequency configuration in RUN mode
Multipurpose Clock Generator (MCG) in PEE mode.
Reference clock source for MCG module: System oscillator 0 reference clock
Core clock = 120MHz
Bus clock = 60MHz
*/
/* Define clock source values */
#if TOWER
#define CPU_XTAL_CLK_HZ \
16000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
#elif FREEDOM
#define CPU_XTAL_CLK_HZ 12000000U
#else
#define CPU_XTAL_CLK_HZ 16000000U
#endif
#define CPU_XTAL32k_CLK_HZ \
32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
*/
#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
/* RTC oscillator setting */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
/* Internal reference clock trim */
/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
#ifdef CLOCK_SETUP
#if (CLOCK_SETUP == 0)
#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
#define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
/* MCG_C11: PLLCS=0 */
#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x02U /* SIM_CLKDIV2 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 1)
#define DEFAULT_SYSTEM_CLOCK 180000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x1D */
#define SYSTEM_MCG_C6_VALUE 0x5DU /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* MCG_C9: PLL_CME=1,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
#define SYSTEM_MCG_C9_VALUE 0x20U /* MCG_C9 */
/* MCG_C11: PLLCS=0 */
#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=2,OUTDIV3=2,OUTDIV4=6 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x02260000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=6,USBFRAC=0 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x0CU /* SIM_CLKDIV2 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 2)
#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
#define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
/* MCG_C11: PLLCS=0 */
#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x00U /* SIM_CLKDIV2 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 3)
#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
#define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
/* MCG_C11: PLLCS=0 */
#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=3,OUTDIV2=3,OUTDIV3=3,OUTDIV4=0x0F */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x333F0000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x00U /* SIM_CLKDIV2 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 4)
#define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x0E */
#define SYSTEM_MCG_C6_VALUE 0x4EU /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
#define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
/* MCG_C11: PLLCS=0 */
#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x12U /* SIM_CLKDIV2 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
#elif(CLOCK_SETUP == 5)
#define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x0E */
#define SYSTEM_MCG_C6_VALUE 0x4EU /* MCG_C6 */
/* MCG_C7: OSCSEL=0 */
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
/* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
#define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
/* MCG_C11: PLLCS=0 */
#define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
#define SYSTEM_SIM_CLKDIV2_VALUE 0x12U /* SIM_CLKDIV2 */
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
/* SIM_SOPT2:
* SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
*/
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
#endif
#else
#define DEFAULT_SYSTEM_CLOCK 20971520u
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(_SYSTEM_MK65F18_H_) */

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__TARGET_CONFIG_H__)
#define __TARGET_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief Constants for clock frequencies.
enum _target_clocks
{
kDefaultClock = 20971520u,
kMcgOutWithFullSpeedUsb = 48000000u,
kMcgOutWithHighSpeedUsb = 120000000u,
kMinCoreClockWithFsUsbSupport = 20000000u,
kMaxCoreClock = 180000000u,
kMaxBusClock = 60000000u,
kMaxFlexBusClock = 60000000u,
kMaxFlashClock = 28000000u,
kDivider_Min = 1,
kDivider_Max = 16,
};
//! @brief Constants for sram partition
enum _sram_partition
{
kSram_LowerPart = 1,
kSram_UpperPart = 3,
};
//! @brief Version constants for the target.
enum _target_version_constants
{
kTarget_Version_Name = 'T',
kTarget_Version_Major = 1,
kTarget_Version_Minor = 0,
kTarget_Version_Bugfix = 0
};
#endif // __TARGET_CONFIG_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __USB_DEVICE_CONFIG_H__
#define __USB_DEVICE_CONFIG_H__ 1
#include "bootloader_common.h"
/*!
* @addtogroup usb_device_configuration
* @{
*/
#if TOWER
#define BOARD_XTAL0_CLK_HZ 16000000U
#define BOARD_XTAL32K_CLK_HZ 32768U
#elif FREEDOM
#define BOARD_XTAL0_CLK_HZ 12000000U
#define BOARD_XTAL32K_CLK_HZ 32768U
#else
#define BOARD_XTAL0_CLK_HZ 16000000U
#define BOARD_XTAL32K_CLK_HZ 32768U
#endif
/*!
* @name Hardware instance define
* @{
*/
/*! @brief KHCI instance count */
#define USB_DEVICE_CONFIG_KHCI (BL_CONFIG_USB_HID | BL_CONFIG_USB_MSC)
/*! @brief EHCI instance count */
#define USB_DEVICE_CONFIG_EHCI (BL_CONFIG_HS_USB_HID | BL_CONFIG_HS_USB_MSC)
/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/
#define USB_DEVICE_CONFIG_NUM (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI)
/* @} */
/*!
* @name class instance define
* @{
*/
/*! @brief HID instance count */
#define USB_DEVICE_CONFIG_HID (BL_CONFIG_USB_HID + BL_CONFIG_HS_USB_HID)
/*! @brief CDC ACM instance count */
#define USB_DEVICE_CONFIG_CDC_ACM (0U)
/*! @brief MSC instance count */
#define USB_DEVICE_CONFIG_MSC (BL_CONFIG_USB_MSC + BL_CONFIG_HS_USB_MSC)
/*! @brief Audio instance count */
#define USB_DEVICE_CONFIG_AUDIO (0U)
/*! @brief PHDC instance count */
#define USB_DEVICE_CONFIG_PHDC (0U)
/*! @brief Video instance count */
#define USB_DEVICE_CONFIG_VIDEO (0U)
/*! @brief CCID instance count */
#define USB_DEVICE_CONFIG_CCID (0U)
/*! @brief Printer instance count */
#define USB_DEVICE_CONFIG_PRINTER (0U)
/*! @brief DFU instance count */
#define USB_DEVICE_CONFIG_DFU (0U)
/* @} */
/*! @brief Whether device is self power. 1 supported, 0 not supported */
#define USB_DEVICE_CONFIG_SELF_POWER (1U)
/*! @brief Whether device remote wakeup supported. 1 supported, 0 not supported */
#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
/*! @brief How many endpoints are supported in the stack. */
#define USB_DEVICE_CONFIG_ENDPOINTS (8U)
/*! @brief Whether the device task is enabled. */
#define USB_DEVICE_CONFIG_USE_TASK (0U)
/*! @brief How many the notification message are supported when the device task enabled. */
#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U)
#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
/*! @brief The MAX buffer length for the KHCI DMA workaround.*/
/* clang-format off */
#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U)
/*! @brief Whether handle the USB KHCI bus error. */
#define USB_DEVICE_CONFIG_KHCI_ERROR_HANDLING (0U)
/* clang-format on */
#endif
#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
/*! @brief How many the DTD are supported. */
/* clang-format off */
#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
/*! @brief Whether handle the USB EHCI bus error. */
#define USB_DEVICE_CONFIG_EHCI_ERROR_HANDLING (0U)
/*! @brief Whether test mode enabled. */
#define USB_DEVICE_CONFIG_EHCI_TEST_MODE (0U)
/*! @brief Whether the EHCI ID pin detect feature enabled. */
#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U)
/* clang-format on */
#endif
/*! @brief Whether the keep alive feature enabled. */
/* clang-format off */
#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U)
/*! @brief Whether the transfer buffer is cache-enabled or not. */
#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
/*! @brief Whether the low power mode is enabled or not. */
#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
/*! @brief Whether the device detached feature is enabled or not. */
#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
/* clang-format on */
/* @} */
#endif /* __USB_DEVICE_CONFIG_H__ */