Add KBOOT.
This commit is contained in:
László Monda
143
targets/MK64F12/src/bootloader_config.h
Normal file
143
targets/MK64F12/src/bootloader_config.h
Normal file
@@ -0,0 +1,143 @@
|
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/*
|
||||
* Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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||||
*/
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#ifndef __BOOTLOADER_CONFIG_H__
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#define __BOOTLOADER_CONFIG_H__
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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||||
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//
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// Bootloader configuration options
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//
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//! @name Peripheral configuration macros
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//@{
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#if !defined(BL_CONFIG_SCUART)
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#define BL_CONFIG_SCUART (1)
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#endif
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#if !defined(BL_CONFIG_I2C)
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#define BL_CONFIG_I2C (1)
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#endif
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#if !defined(BL_CONFIG_DSPI)
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#define BL_CONFIG_DSPI (1)
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#endif
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#if !defined(BL_CONFIG_USB_HID)
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#define BL_CONFIG_USB_HID (1)
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#endif
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#if !defined(BL_CONFIG_USB_MSC)
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#define BL_CONFIG_USB_MSC (1)
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#endif
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//@}
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#if !defined(BL_TARGET_FLASH) && !defined(BL_TARGET_RAM)
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#define BL_TARGET_FLASH (1)
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#endif
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#define BL_FEATURE_FLASH_CHECK_CUMULATIVE_WRITE (1)
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#if defined(BL_TARGET_RAM)
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#define BL_FEATURE_FLASH_SECURITY (0)
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#else
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#define BL_FEATURE_FLASH_SECURITY (1)
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#endif
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#define BL_FEATURE_QSPI_MODULE (0)
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#define BL_FEATURE_ENCRYPTION_MMCAU (1)
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#define BL_FEATURE_ENCRYPTION (BL_FEATURE_ENCRYPTION_MMCAU)
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#define BL_FEATURE_ENCRYPTION_KEY_ADDRESS 0xb000 // NOTE: this address must be 4-byte aligned.
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#define BL_FEATURE_MIN_PROFILE (0)
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// Bootloader peripheral detection default timeout in milliseconds
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// After coming out of reset the bootloader will spin in a peripheral detection
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// loop for this amount of time. A zero value means no time out.
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#if DEBUG
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#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 0
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#else
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#define BL_DEFAULT_PERIPHERAL_DETECT_TIMEOUT 5000
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#endif // DEBUG
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#define BL_FEATURE_POWERDOWN (0)
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// Bootloader powerdown timeout in milliseconds
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// The bootloader enters a low power mode after waiting for this amount of time. A zero value means // no time out. Only
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// applicable if BL_FEATURE_POWERDOWN is enabled.
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#if DEBUG
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#define BL_DEFAULT_POWERDOWN_TIMEOUT 10000
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#else
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#define BL_DEFAULT_POWERDOWN_TIMEOUT 600000
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#endif // DEBUG
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#if !defined(BL_TARGET_RAM)
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#define BL_FEATURE_CRC_CHECK (1)
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#endif
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#define BL_FEATURE_UART_AUTOBAUD_IRQ (1)
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#define BL_FEATURE_ENABLE_FLASH_PROGRAM_SECTION (1)
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// The bootloader will check this address for the application vector table upon startup.
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#if !defined(BL_APP_VECTOR_TABLE_ADDRESS)
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#define BL_APP_VECTOR_TABLE_ADDRESS 0xa000
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#endif
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/* Serial Port Info */
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/**************************************************************************
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* Note:
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*
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* Because of the changes to the UART modules, we can no longer define
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* the TERM_PORT as a base pointer. The uart functions have been modified
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* accommodate this change. Now, TERM_PORT_NUM must be defined as the
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* number of the UART port desired to use
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*
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* TERM_PORT_NUM = 0 -- This allows you to use UART0; default pins are
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* PTA14 and PTA15
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*
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* TERM_PORT_NUM = 1 -- This allows you to use UART1; default pins are
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* PTC3 and PTC4
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*
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* TERM_PORT_NUM = 2 -- This allows you to use UART2; default pins are
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* PTD2 and PTD3
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*
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*************************************************************************/
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#define TERM_PORT_NUM 0
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#define TERMINAL_BAUD 19200
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#undef HW_FLOW_CONTROL
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#endif // __BOOTLOADER_CONFIG_H__
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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||||
////////////////////////////////////////////////////////////////////////////////
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215
targets/MK64F12/src/clock_config_MK64F12.c
Normal file
215
targets/MK64F12/src/clock_config_MK64F12.c
Normal file
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
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||||
#include "bootloader_common.h"
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#include "bootloader/bl_context.h"
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#include "property/property.h"
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#include "fsl_device_registers.h"
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||||
#include "utilities/fsl_assert.h"
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////////////////////////////////////////////////////////////////////////////////
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||||
// Definitions
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||||
////////////////////////////////////////////////////////////////////////////////
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||||
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// Clock mode types
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typedef enum _target_clock_mode
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{
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kClockMode_FEI_48MHz = 0,
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kClockMode_FEI_21MHz = 1,
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kClockMode_Default = kClockMode_FEI_21MHz,
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} target_clock_mode_t;
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////////////////////////////////////////////////////////////////////////////////
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// Prototypes
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////////////////////////////////////////////////////////////////////////////////
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||||
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// This function implements clock mode switch between FEI and PEE mode used in this bootloader
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void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode);
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||||
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||||
////////////////////////////////////////////////////////////////////////////////
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||||
// Code
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||||
////////////////////////////////////////////////////////////////////////////////
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||||
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// See bootloader_common for documentation on this function.
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void configure_clocks(bootloader_clock_option_t option)
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{
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static target_clock_mode_t s_currentClockMode = kClockMode_FEI_21MHz;
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static uint32_t s_defaultClockDivider;
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if (option == kClockOption_EnterBootloader)
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{
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s_defaultClockDivider = SIM->CLKDIV1;
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// General procedure to be implemented:
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// 1. Read clock flags and divider from bootloader config in property store
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bootloader_configuration_data_t *config = &g_bootloaderContext.propertyInterface->store->configurationData;
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uint8_t options = config->clockFlags;
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// Check if the USB HID peripheral is enabled. If it is enabled, we always
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// configure the MCGOUT to 48MHz.
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bool isUsbEnabled = config->enabledPeripherals & kPeripheralType_USB_HID;
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// 2. If NOT High Speed and USB isn't enabled, do nothing (use reset clock config)
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if ((options & kClockFlag_HighSpeed) && (!isUsbEnabled))
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{
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// Get actual Core clock.
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SystemCoreClock =
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kDefaultClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) + 1);
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// High speed flag is set (meaning disabled), so just use default clocks.
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return;
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}
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// 3. Set OUTDIV1 based on divider in config. OUTDIV4 starts out at /1.
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// The divider values are masked by the maximum bits per divider.
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uint32_t div1 = ((~config->clockDivider) & (SIM_CLKDIV1_OUTDIV1_MASK >> SIM_CLKDIV1_OUTDIV1_SHIFT)) + 1;
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// 4. Get MCGOUTCLK
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uint32_t McgOutClk = kHIRC;
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// 5. Keep core clock up kMinCoreClockWithUsbSupport if usb is supported.
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uint32_t freq = McgOutClk;
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// If USB is enabled, the CPU clock must not be allowed to go below 20 MHz
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if (isUsbEnabled)
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{
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while ((freq / div1) < kMinCoreClockWithUsbSupport)
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{
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--div1;
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||||
}
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}
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// 6. Keep core clock below kMaxCoreClock
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||||
while ((freq / div1) > kMaxCoreClock)
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{
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++div1;
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}
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||||
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assert((div1 >= kDivider_Min) && (div1 <= kDivider_Max));
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uint32_t div2 = div1;
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uint32_t div3 = div1;
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uint32_t div4 = div1;
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||||
// 7. Keep bus freq below max.
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||||
//
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// The bus clock is divided by OUTDIV2:
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// MCGOUTCLK -> OUTDIV2 -> bus_clk
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freq = McgOutClk;
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while ((freq / div2) > kMaxBusClock)
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{
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// Increase bus clock divider.
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++div2;
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}
|
||||
assert((div2 >= kDivider_Min) && (div2 <= kDivider_Max));
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||||
// 8. Keep FlexBus freq below max.
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//
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// The FlexBus clock is divided by OUTDIV3:
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// MCGOUTCLK -> OUTDIV3 -> flexbus_clk
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freq = McgOutClk;
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while ((freq / div3) > kMaxFlexBusClock)
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{
|
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// Increase flexbus clock divider.
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++div3;
|
||||
}
|
||||
assert((div3 >= kDivider_Min) && (div3 <= kDivider_Max));
|
||||
|
||||
// 9. Keep flash freq below max.
|
||||
//
|
||||
// The flash clock is diveded by OUTDIV4:
|
||||
// MCGOUTCLK -> OUTDIV4 ->flash_clk
|
||||
freq = McgOutClk;
|
||||
while ((freq / div4) > kMaxFlashClock)
|
||||
{
|
||||
// Increase bus/flash clock divider.
|
||||
++div4;
|
||||
}
|
||||
assert((div4 >= kDivider_Min) && (div4 <= kDivider_Max));
|
||||
|
||||
if ((div1 == 1) && ((div2 > 8) || (div3 > 8) || (div4 > 8)))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
// 9. Now set the dividers
|
||||
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(div1 - 1) | SIM_CLKDIV1_OUTDIV1(div1 - 1) | SIM_CLKDIV1_OUTDIV2(div3 - 1) |
|
||||
SIM_CLKDIV1_OUTDIV4(div4 - 1); /* Update system prescalers */
|
||||
|
||||
// 10. Update SystemCoreClock global.
|
||||
SystemCoreClock = McgOutClk / div1;
|
||||
|
||||
clock_mode_switch(s_currentClockMode, kClockMode_FEI_48MHz);
|
||||
|
||||
s_currentClockMode = kClockMode_FEI_48MHz;
|
||||
}
|
||||
else if (option == kClockOption_ExitBootloader)
|
||||
{
|
||||
// Restore from FEE mode to FEI mode
|
||||
clock_mode_switch(s_currentClockMode, kClockMode_FEI_21MHz);
|
||||
|
||||
// Restore clock divider
|
||||
SIM->CLKDIV1 = s_defaultClockDivider;
|
||||
}
|
||||
}
|
||||
|
||||
void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode)
|
||||
{
|
||||
// Note: here only implements clock switch between FEI and FEE,
|
||||
// The other modes are not supported.
|
||||
assert(currentMode == kClockMode_FEE || currentMode == kClockMode_FEI);
|
||||
assert(expectedMode == kClockMode_FEE || expectedMode == kClockMode_FEI);
|
||||
|
||||
if (currentMode == expectedMode)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (expectedMode == kClockMode_FEI_48MHz)
|
||||
{
|
||||
/* Switch to FEI mode */
|
||||
uint8_t tmp = MCG->C4;
|
||||
tmp &= (uint8_t) ~(MCG_C4_DRST_DRS_MASK);
|
||||
tmp |= MCG_C4_DMX32_MASK; // Multiply with 1464, MCGOUTCLK is 48Mhz
|
||||
tmp |= MCG_C4_DRST_DRS(1); // Reference range:32.768kHZ
|
||||
MCG->C4 = tmp;
|
||||
|
||||
while (!(MCG->S & MCG_S_IREFST_MASK))
|
||||
; // Wait until internal reference clock is ready.
|
||||
}
|
||||
else if (expectedMode == kClockMode_FEI_21MHz)
|
||||
{
|
||||
// Restore registers to default value out of reset.
|
||||
MCG->C4 &= (uint8_t) ~(MCG_C4_DRST_DRS_MASK | MCG_C4_DMX32_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
166
targets/MK64F12/src/hardware_init_MK64F12.c
Normal file
166
targets/MK64F12/src/hardware_init_MK64F12.c
Normal file
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "bootloader_common.h"
|
||||
#include "bootloader/bl_context.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "uart/fsl_uart.h"
|
||||
#include "smc/smc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define BOOT_PIN_NUMBER 6
|
||||
#define BOOT_PIN_PORT PORTC
|
||||
#define BOOT_PIN_GPIO GPIOC
|
||||
#define BOOT_PIN_ALT_MODE 1
|
||||
#define BOOT_PIN_DEBOUNCE_READ_COUNT 500
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Variables
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Code
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void init_hardware(void)
|
||||
{
|
||||
exit_vlpr();
|
||||
|
||||
// Disable the MPU otherwise USB cannot access the bus
|
||||
MPU->CESR = 0;
|
||||
|
||||
// Enable all the ports
|
||||
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
|
||||
SIM_SCGC5_PORTE_MASK);
|
||||
}
|
||||
|
||||
void deinit_hardware(void)
|
||||
{
|
||||
SIM->SCGC5 &= (uint32_t) ~(SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |
|
||||
SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
|
||||
|
||||
// Restore SIM_SOPTx related bits being changed
|
||||
SIM->SOPT1 &= (uint32_t)~SIM_SOPT1_USBREGEN_MASK;
|
||||
SIM->SOPT2 &= (uint32_t) ~(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
|
||||
}
|
||||
|
||||
bool usb_clock_init(void)
|
||||
{
|
||||
SIM->SCGC4 &= ~SIM_SCGC4_USBOTG_MASK;
|
||||
|
||||
SIM->CLKDIV2 = (uint32_t)0x00L;
|
||||
SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(0x03);
|
||||
|
||||
SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
|
||||
|
||||
USB0->CLK_RECOVER_IRC_EN = 0x03;
|
||||
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
|
||||
|
||||
USB0->CLK_RECOVER_CTRL |= 0x20;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
uint32_t get_bus_clock(void)
|
||||
{
|
||||
uint32_t busClockDivider = ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1;
|
||||
return (SystemCoreClock / busClockDivider);
|
||||
}
|
||||
|
||||
uint32_t get_uart_clock(uint32_t instance)
|
||||
{
|
||||
switch (instance)
|
||||
{
|
||||
case 0:
|
||||
case 1:
|
||||
// UART0 and UART1 always use the system clock
|
||||
return SystemCoreClock;
|
||||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
case 5:
|
||||
// UART2, UART3, UART4, and UART5 always use the bus clock
|
||||
return get_bus_clock();
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
bool is_boot_pin_asserted(void)
|
||||
{
|
||||
#ifdef BL_TARGET_FLASH
|
||||
// Initialize boot pin for GPIO
|
||||
BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= PORT_PCR_MUX(BOOT_PIN_ALT_MODE);
|
||||
|
||||
// Set boot pin as an input
|
||||
BOOT_PIN_GPIO->PDDR &= (uint32_t) ~(1 << BOOT_PIN_NUMBER);
|
||||
// Set boot pin pullup enabled, pullup select, filter enable
|
||||
BOOT_PIN_PORT->PCR[BOOT_PIN_NUMBER] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_PFE_MASK);
|
||||
|
||||
uint32_t readCount = 0;
|
||||
|
||||
// Sample the pin a number of times
|
||||
for (uint32_t i = 0; i < BOOT_PIN_DEBOUNCE_READ_COUNT; i++)
|
||||
{
|
||||
readCount += ((BOOT_PIN_GPIO->PDIR) >> BOOT_PIN_NUMBER) & 1;
|
||||
}
|
||||
|
||||
// boot pin is pulled high so we are measuring lows, make sure most of our measurements
|
||||
// registered as low
|
||||
return (readCount < (BOOT_PIN_DEBOUNCE_READ_COUNT / 2));
|
||||
#else
|
||||
// Boot pin for Flash only target
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
void debug_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
#if __ICCARM__
|
||||
|
||||
size_t __write(int handle, const unsigned char *buf, size_t size)
|
||||
{
|
||||
return size;
|
||||
}
|
||||
|
||||
#endif // __ICCARM__
|
||||
|
||||
void update_available_peripherals()
|
||||
{
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
53
targets/MK64F12/src/memory_map_MK64F12.c
Normal file
53
targets/MK64F12/src/memory_map_MK64F12.c
Normal file
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (c) 2013, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "bootloader/bl_context.h"
|
||||
#include "memory/memory.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Variables
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @brief Memory map for K64F12.
|
||||
//!
|
||||
//! This map is not const because it is updated at runtime with the actual sizes of
|
||||
//! flash and RAM for the chip we're running on.
|
||||
memory_map_entry_t g_memoryMap[] = {
|
||||
{ 0x00000000, 0x000fffff, kMemoryIsExecutable, &g_flashMemoryInterface }, // Flash array (1024KB)
|
||||
{ 0x1fff0000, 0x2002ffff, kMemoryIsExecutable, &g_normalMemoryInterface }, // SRAM (256KB)
|
||||
{ 0x40000000, 0x4007ffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // AIPS peripherals
|
||||
{ 0x400ff000, 0x400fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // GPIO
|
||||
{ 0xe0000000, 0xe00fffff, kMemoryNotExecutable, &g_deviceMemoryInterface }, // M4 private peripherals
|
||||
{ 0 } // Terminator
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
101
targets/MK64F12/src/peripherals_MK64F12.c
Normal file
101
targets/MK64F12/src/peripherals_MK64F12.c
Normal file
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "bootloader/bl_context.h"
|
||||
#include "bootloader/bl_peripheral_interface.h"
|
||||
#include "packet/serial_packet.h"
|
||||
|
||||
extern void uart_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
|
||||
extern void i2c_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
|
||||
extern void spi_pinmux_config(uint32_t instance, pinmux_type_t pinmux);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Variables
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#if !BL_CONFIG_SCUART && !BL_CONFIG_I2C && !BL_CONFIG_DSPI && !BL_CONFIG_USB_HID
|
||||
#error At least one peripheral must be enabled!
|
||||
#endif
|
||||
|
||||
//! @brief Peripheral array for K64F12.
|
||||
const peripheral_descriptor_t g_peripherals[] = {
|
||||
#if BL_CONFIG_SCUART
|
||||
#if !defined(TOWER)
|
||||
// UART0
|
||||
{.typeMask = kPeripheralType_UART,
|
||||
.instance = 0,
|
||||
.pinmuxConfig = uart_pinmux_config,
|
||||
.controlInterface = &g_scuartControlInterface,
|
||||
.byteInterface = &g_scuartByteInterface,
|
||||
.packetInterface = &g_framingPacketInterface },
|
||||
#else
|
||||
// UART1
|
||||
{.typeMask = kPeripheralType_UART,
|
||||
.instance = 1,
|
||||
.pinmuxConfig = uart_pinmux_config,
|
||||
.controlInterface = &g_scuartControlInterface,
|
||||
.byteInterface = &g_scuartByteInterface,
|
||||
.packetInterface = &g_framingPacketInterface },
|
||||
#endif //#if !defined(TOWER)
|
||||
#endif // BL_CONFIG_SCUART
|
||||
#if BL_CONFIG_I2C
|
||||
// I2C1
|
||||
{.typeMask = kPeripheralType_I2CSlave,
|
||||
.instance = 1,
|
||||
.pinmuxConfig = i2c_pinmux_config,
|
||||
.controlInterface = &g_i2cControlInterface,
|
||||
.byteInterface = &g_i2cByteInterface,
|
||||
.packetInterface = &g_framingPacketInterface },
|
||||
#endif // BL_CONFIG_I2C
|
||||
#if BL_CONFIG_DSPI
|
||||
// SPI0
|
||||
{.typeMask = kPeripheralType_SPISlave,
|
||||
.instance = 0,
|
||||
.pinmuxConfig = spi_pinmux_config,
|
||||
.controlInterface = &g_dspiControlInterface,
|
||||
.byteInterface = &g_dspiByteInterface,
|
||||
.packetInterface = &g_framingPacketInterface },
|
||||
#endif // BL_CONFIG_DSPI
|
||||
#if (BL_CONFIG_USB_HID || BL_CONFIG_USB_MSC)
|
||||
// USB HID
|
||||
{.typeMask = kPeripheralType_USB_HID,
|
||||
.instance = 0,
|
||||
.pinmuxConfig = NULL,
|
||||
.controlInterface = &g_usbHidControlInterface,
|
||||
.byteInterface = NULL,
|
||||
.packetInterface = &g_usbHidPacketInterface },
|
||||
#endif // BL_CONFIG_USB_HID
|
||||
|
||||
{ 0 } // Terminator
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
96
targets/MK64F12/src/peripherals_pinmux.h
Normal file
96
targets/MK64F12/src/peripherals_pinmux.h
Normal file
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! peripheral enable configurations
|
||||
#if defined(TOWER)
|
||||
#define BL_ENABLE_PINMUX_UART1 (BL_CONFIG_SCUART)
|
||||
#else
|
||||
#define BL_ENABLE_PINMUX_UART0 (BL_CONFIG_SCUART)
|
||||
#endif
|
||||
#define BL_ENABLE_PINMUX_SPI0 (BL_CONFIG_DSPI)
|
||||
#define BL_ENABLE_PINMUX_I2C1 (BL_CONFIG_I2C)
|
||||
|
||||
//! UART pinmux configurations
|
||||
#if defined(TOWER) // TWR board and tower_bootloader
|
||||
#define UART1_RX_PORT_BASE PORTC
|
||||
#define UART1_RX_GPIO_BASE PTC
|
||||
#define UART1_RX_GPIO_PIN_NUM 3 // PTC3
|
||||
#define UART1_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 RX functionality
|
||||
#define UART1_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO functionality
|
||||
#define UART1_RX_GPIO_IRQn PORTC_IRQn
|
||||
#define UART1_RX_GPIO_IRQHandler PORTC_IRQHandler
|
||||
#define UART1_TX_PORT_BASE PORTC
|
||||
#define UART1_TX_GPIO_PIN_NUM 4 // PTC4
|
||||
#define UART1_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 TX functionality
|
||||
|
||||
#else // flashloader and FRDM_bootloader
|
||||
#define UART0_RX_PORT_BASE PORTB
|
||||
#define UART0_RX_GPIO_BASE PTB
|
||||
#define UART0_RX_GPIO_PIN_NUM 16 // PTB16
|
||||
#define UART0_RX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 RX functionality
|
||||
#define UART0_RX_GPIO_ALT_MODE kPORT_MuxAsGpio // ALT mdoe for GPIO functionality
|
||||
#define UART0_RX_GPIO_IRQn PORTB_IRQn
|
||||
#define UART0_RX_GPIO_IRQHandler PORTB_IRQHandler
|
||||
#define UART0_TX_PORT_BASE PORTB
|
||||
#define UART0_TX_GPIO_PIN_NUM 17 // PTB17
|
||||
#define UART0_TX_FUNC_ALT_MODE kPORT_MuxAlt3 // ALT mode for UART1 TX functionality
|
||||
#endif // TOWER
|
||||
|
||||
//! I2C pinmux configurations
|
||||
#define I2C1_SCL_PORT_BASE PORTC
|
||||
#define I2C1_SCL_GPIO_PIN_NUM 10 // PTC10
|
||||
#define I2C1_SCL_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C1 SCL functionality
|
||||
#define I2C1_SDA_PORT_BASE PORTC
|
||||
#define I2C1_SDA_GPIO_PIN_NUM 11 // PTC11
|
||||
#define I2C1_SDA_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for I2C1 SDA functionality
|
||||
|
||||
//! SPI pinmux configurations
|
||||
#define SPI0_PCS_PORT_BASE PORTD
|
||||
#define SPI0_PCS_GPIO_PIN_NUM 0 // PTD0
|
||||
#define SPI0_PCS_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 PCS functionality
|
||||
#define SPI0_SCK_PORT_BASE PORTD
|
||||
#define SPI0_SCK_GPIO_PIN_NUM 1 // PTD1
|
||||
#define SPI0_SCK_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SCK functionality
|
||||
#define SPI0_SOUT_PORT_BASE PORTD
|
||||
#define SPI0_SOUT_GPIO_PIN_NUM 2 // PTD2
|
||||
#define SPI0_SOUT_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SOUT functionality
|
||||
#define SPI0_SIN_PORT_BASE PORTD
|
||||
#define SPI0_SIN_GPIO_PIN_NUM 3 // PTD3
|
||||
#define SPI0_SIN_FUNC_ALT_MODE kPORT_MuxAlt2 // ALT mode for SPI1 SIN functionality
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
747
targets/MK64F12/src/startup/arm/startup_MK64F12.s
Normal file
747
targets/MK64F12/src/startup/arm/startup_MK64F12.s
Normal file
File diff suppressed because it is too large
Load Diff
486
targets/MK64F12/src/startup/gcc/startup_MK64F12.S
Normal file
486
targets/MK64F12/src/startup/gcc/startup_MK64F12.S
Normal file
@@ -0,0 +1,486 @@
|
||||
/* ---------------------------------------------------------------------------------------*/
|
||||
/* @file: startup_MK64F12.s */
|
||||
/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
|
||||
/* MK64F12 */
|
||||
/* @version: 2.7 */
|
||||
/* @date: 2014-10-14 */
|
||||
/* @build: b150126 */
|
||||
/* ---------------------------------------------------------------------------------------*/
|
||||
/* */
|
||||
/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without modification, */
|
||||
/* are permitted provided that the following conditions are met: */
|
||||
/* */
|
||||
/* o Redistributions of source code must retain the above copyright notice, this list */
|
||||
/* of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* o Redistributions in binary form must reproduce the above copyright notice, this */
|
||||
/* list of conditions and the following disclaimer in the documentation and/or */
|
||||
/* other materials provided with the distribution. */
|
||||
/* */
|
||||
/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
|
||||
/* contributors may be used to endorse or promote products derived from this */
|
||||
/* software without specific prior written permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
|
||||
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
|
||||
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
|
||||
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
|
||||
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
|
||||
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
|
||||
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
|
||||
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
|
||||
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/*****************************************************************************/
|
||||
/* Version: GCC for ARM Embedded Processors */
|
||||
/*****************************************************************************/
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .isr_vector, "a"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler*/
|
||||
.long HardFault_Handler /* Hard Fault Handler*/
|
||||
.long MemManage_Handler /* MPU Fault Handler*/
|
||||
.long BusFault_Handler /* Bus Fault Handler*/
|
||||
.long UsageFault_Handler /* Usage Fault Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long SVC_Handler /* SVCall Handler*/
|
||||
.long DebugMon_Handler /* Debug Monitor Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long PendSV_Handler /* PendSV Handler*/
|
||||
.long SysTick_Handler /* SysTick Handler*/
|
||||
|
||||
/* External Interrupts*/
|
||||
.long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/
|
||||
.long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/
|
||||
.long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/
|
||||
.long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/
|
||||
.long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/
|
||||
.long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/
|
||||
.long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/
|
||||
.long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/
|
||||
.long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/
|
||||
.long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/
|
||||
.long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/
|
||||
.long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/
|
||||
.long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/
|
||||
.long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/
|
||||
.long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/
|
||||
.long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/
|
||||
.long DMA_Error_IRQHandler /* DMA Error Interrupt*/
|
||||
.long MCM_IRQHandler /* Normal Interrupt*/
|
||||
.long FTFE_IRQHandler /* FTFE Command complete interrupt*/
|
||||
.long Read_Collision_IRQHandler /* Read Collision Interrupt*/
|
||||
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
|
||||
.long LLW_IRQHandler /* Low Leakage Wakeup*/
|
||||
.long WDOG_EWM_IRQHandler /* WDOG Interrupt*/
|
||||
.long RNG_IRQHandler /* RNG Interrupt*/
|
||||
.long I2C0_IRQHandler /* I2C0 interrupt*/
|
||||
.long I2C1_IRQHandler /* I2C1 interrupt*/
|
||||
.long SPI0_IRQHandler /* SPI0 Interrupt*/
|
||||
.long SPI1_IRQHandler /* SPI1 Interrupt*/
|
||||
.long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
|
||||
.long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
|
||||
.long UART0_LON_IRQHandler /* UART0 LON interrupt*/
|
||||
.long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
|
||||
.long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
|
||||
.long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
|
||||
.long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
|
||||
.long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/
|
||||
.long UART2_ERR_IRQHandler /* UART2 Error interrupt*/
|
||||
.long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/
|
||||
.long UART3_ERR_IRQHandler /* UART3 Error interrupt*/
|
||||
.long ADC0_IRQHandler /* ADC0 interrupt*/
|
||||
.long CMP0_IRQHandler /* CMP0 interrupt*/
|
||||
.long CMP1_IRQHandler /* CMP1 interrupt*/
|
||||
.long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
|
||||
.long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
|
||||
.long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
|
||||
.long CMT_IRQHandler /* CMT interrupt*/
|
||||
.long RTC_IRQHandler /* RTC interrupt*/
|
||||
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
|
||||
.long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
|
||||
.long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
|
||||
.long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
|
||||
.long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
|
||||
.long PDB0_IRQHandler /* PDB0 Interrupt*/
|
||||
.long USB0_IRQHandler /* USB0 interrupt*/
|
||||
.long USBDCD_IRQHandler /* USBDCD Interrupt*/
|
||||
.long Reserved71_IRQHandler /* Reserved interrupt 71*/
|
||||
.long DAC0_IRQHandler /* DAC0 interrupt*/
|
||||
.long MCG_IRQHandler /* MCG Interrupt*/
|
||||
.long LPTMR0_IRQHandler /* LPTimer interrupt*/
|
||||
.long PORTA_IRQHandler /* Port A interrupt*/
|
||||
.long PORTB_IRQHandler /* Port B interrupt*/
|
||||
.long PORTC_IRQHandler /* Port C interrupt*/
|
||||
.long PORTD_IRQHandler /* Port D interrupt*/
|
||||
.long PORTE_IRQHandler /* Port E interrupt*/
|
||||
.long SWI_IRQHandler /* Software interrupt*/
|
||||
.long SPI2_IRQHandler /* SPI2 Interrupt*/
|
||||
.long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/
|
||||
.long UART4_ERR_IRQHandler /* UART4 Error interrupt*/
|
||||
.long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/
|
||||
.long UART5_ERR_IRQHandler /* UART5 Error interrupt*/
|
||||
.long CMP2_IRQHandler /* CMP2 interrupt*/
|
||||
.long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/
|
||||
.long DAC1_IRQHandler /* DAC1 interrupt*/
|
||||
.long ADC1_IRQHandler /* ADC1 interrupt*/
|
||||
.long I2C2_IRQHandler /* I2C2 interrupt*/
|
||||
.long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/
|
||||
.long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/
|
||||
.long CAN0_Error_IRQHandler /* CAN0 error interrupt*/
|
||||
.long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/
|
||||
.long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/
|
||||
.long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/
|
||||
.long SDHC_IRQHandler /* SDHC interrupt*/
|
||||
.long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt*/
|
||||
.long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt*/
|
||||
.long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt*/
|
||||
.long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt*/
|
||||
.long DefaultISR /* 102*/
|
||||
.long DefaultISR /* 103*/
|
||||
.long DefaultISR /* 104*/
|
||||
.long DefaultISR /* 105*/
|
||||
.long DefaultISR /* 106*/
|
||||
.long DefaultISR /* 107*/
|
||||
.long DefaultISR /* 108*/
|
||||
.long DefaultISR /* 109*/
|
||||
.long DefaultISR /* 110*/
|
||||
.long DefaultISR /* 111*/
|
||||
.long DefaultISR /* 112*/
|
||||
.long DefaultISR /* 113*/
|
||||
.long DefaultISR /* 114*/
|
||||
.long DefaultISR /* 115*/
|
||||
.long DefaultISR /* 116*/
|
||||
.long DefaultISR /* 117*/
|
||||
.long DefaultISR /* 118*/
|
||||
.long DefaultISR /* 119*/
|
||||
.long DefaultISR /* 120*/
|
||||
.long DefaultISR /* 121*/
|
||||
.long DefaultISR /* 122*/
|
||||
.long DefaultISR /* 123*/
|
||||
.long DefaultISR /* 124*/
|
||||
.long DefaultISR /* 125*/
|
||||
.long DefaultISR /* 126*/
|
||||
.long DefaultISR /* 127*/
|
||||
.long DefaultISR /* 128*/
|
||||
.long DefaultISR /* 129*/
|
||||
.long DefaultISR /* 130*/
|
||||
.long DefaultISR /* 131*/
|
||||
.long DefaultISR /* 132*/
|
||||
.long DefaultISR /* 133*/
|
||||
.long DefaultISR /* 134*/
|
||||
.long DefaultISR /* 135*/
|
||||
.long DefaultISR /* 136*/
|
||||
.long DefaultISR /* 137*/
|
||||
.long DefaultISR /* 138*/
|
||||
.long DefaultISR /* 139*/
|
||||
.long DefaultISR /* 140*/
|
||||
.long DefaultISR /* 141*/
|
||||
.long DefaultISR /* 142*/
|
||||
.long DefaultISR /* 143*/
|
||||
.long DefaultISR /* 144*/
|
||||
.long DefaultISR /* 145*/
|
||||
.long DefaultISR /* 146*/
|
||||
.long DefaultISR /* 147*/
|
||||
.long DefaultISR /* 148*/
|
||||
.long DefaultISR /* 149*/
|
||||
.long DefaultISR /* 150*/
|
||||
.long DefaultISR /* 151*/
|
||||
.long DefaultISR /* 152*/
|
||||
.long DefaultISR /* 153*/
|
||||
.long DefaultISR /* 154*/
|
||||
.long DefaultISR /* 155*/
|
||||
.long DefaultISR /* 156*/
|
||||
.long DefaultISR /* 157*/
|
||||
.long DefaultISR /* 158*/
|
||||
.long DefaultISR /* 159*/
|
||||
.long DefaultISR /* 160*/
|
||||
.long DefaultISR /* 161*/
|
||||
.long DefaultISR /* 162*/
|
||||
.long DefaultISR /* 163*/
|
||||
.long DefaultISR /* 164*/
|
||||
.long DefaultISR /* 165*/
|
||||
.long DefaultISR /* 166*/
|
||||
.long DefaultISR /* 167*/
|
||||
.long DefaultISR /* 168*/
|
||||
.long DefaultISR /* 169*/
|
||||
.long DefaultISR /* 170*/
|
||||
.long DefaultISR /* 171*/
|
||||
.long DefaultISR /* 172*/
|
||||
.long DefaultISR /* 173*/
|
||||
.long DefaultISR /* 174*/
|
||||
.long DefaultISR /* 175*/
|
||||
.long DefaultISR /* 176*/
|
||||
.long DefaultISR /* 177*/
|
||||
.long DefaultISR /* 178*/
|
||||
.long DefaultISR /* 179*/
|
||||
.long DefaultISR /* 180*/
|
||||
.long DefaultISR /* 181*/
|
||||
.long DefaultISR /* 182*/
|
||||
.long DefaultISR /* 183*/
|
||||
.long DefaultISR /* 184*/
|
||||
.long DefaultISR /* 185*/
|
||||
.long DefaultISR /* 186*/
|
||||
.long DefaultISR /* 187*/
|
||||
.long DefaultISR /* 188*/
|
||||
.long DefaultISR /* 189*/
|
||||
.long DefaultISR /* 190*/
|
||||
.long DefaultISR /* 191*/
|
||||
.long DefaultISR /* 192*/
|
||||
.long DefaultISR /* 193*/
|
||||
.long DefaultISR /* 194*/
|
||||
.long DefaultISR /* 195*/
|
||||
.long DefaultISR /* 196*/
|
||||
.long DefaultISR /* 197*/
|
||||
.long DefaultISR /* 198*/
|
||||
.long DefaultISR /* 199*/
|
||||
.long DefaultISR /* 200*/
|
||||
.long DefaultISR /* 201*/
|
||||
.long DefaultISR /* 202*/
|
||||
.long DefaultISR /* 203*/
|
||||
.long DefaultISR /* 204*/
|
||||
.long DefaultISR /* 205*/
|
||||
.long DefaultISR /* 206*/
|
||||
.long DefaultISR /* 207*/
|
||||
.long DefaultISR /* 208*/
|
||||
.long DefaultISR /* 209*/
|
||||
.long DefaultISR /* 210*/
|
||||
.long DefaultISR /* 211*/
|
||||
.long DefaultISR /* 212*/
|
||||
.long DefaultISR /* 213*/
|
||||
.long DefaultISR /* 214*/
|
||||
.long DefaultISR /* 215*/
|
||||
.long DefaultISR /* 216*/
|
||||
.long DefaultISR /* 217*/
|
||||
.long DefaultISR /* 218*/
|
||||
.long DefaultISR /* 219*/
|
||||
.long DefaultISR /* 220*/
|
||||
.long DefaultISR /* 221*/
|
||||
.long DefaultISR /* 222*/
|
||||
.long DefaultISR /* 223*/
|
||||
.long DefaultISR /* 224*/
|
||||
.long DefaultISR /* 225*/
|
||||
.long DefaultISR /* 226*/
|
||||
.long DefaultISR /* 227*/
|
||||
.long DefaultISR /* 228*/
|
||||
.long DefaultISR /* 229*/
|
||||
.long DefaultISR /* 230*/
|
||||
.long DefaultISR /* 231*/
|
||||
.long DefaultISR /* 232*/
|
||||
.long DefaultISR /* 233*/
|
||||
.long DefaultISR /* 234*/
|
||||
.long DefaultISR /* 235*/
|
||||
.long DefaultISR /* 236*/
|
||||
.long DefaultISR /* 237*/
|
||||
.long DefaultISR /* 238*/
|
||||
.long DefaultISR /* 239*/
|
||||
|
||||
#ifdef BL_HAS_BOOTLOADER_CONFIG
|
||||
|
||||
//__bootloaderConfigurationArea ; 0x3c0
|
||||
// .long 'kcfg' // [00:03] tag - Tag value used to validate the bootloader configuration data. Must be set to 'kcfg'
|
||||
.long 0x6766636b
|
||||
.long 0xFFFFFFFF // [04:07] crcStartAddress
|
||||
.long 0xFFFFFFFF // [08:0b] crcByteCount
|
||||
.long 0xFFFFFFFF // [0c:0f] crcExpectedValue
|
||||
.byte 0xFF // [10:10] enabledPeripherals
|
||||
.byte 0xFF // [11:11] i2cSlaveAddress
|
||||
.short 5000 // [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code
|
||||
.short 0xFFFF // [14:15] usbVid
|
||||
.short 0xFFFF // [16:17] usbPid
|
||||
.long 0xFFFFFFFF // [18:1b] usbStringsPointer
|
||||
.byte 0xFF // [1c:1c] clockFlags - High Speed and other clock options
|
||||
.byte 0xFF // [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1
|
||||
.short 0xFFFF // [1e:1f] reserved
|
||||
// Fill to align with flash configuration field.
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF // Reserved for user TRIM value
|
||||
#else
|
||||
//Fill to align with flash configuration field.
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF // Reserved for user TRIM value
|
||||
#endif // BL_HAS_BOOTLOADER_CONFIG
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Flash Configuration */
|
||||
.section .FlashConfig, "a"
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFE
|
||||
|
||||
.text
|
||||
.thumb
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
cpsid i /* Mask interrupts */
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
bl init_data_bss
|
||||
cpsie i /* Unmask interrupts */
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
#ifndef __ATOLLIC__
|
||||
bl __START
|
||||
#else
|
||||
bl __libc_init_array
|
||||
bl main
|
||||
#endif
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DefaultISR
|
||||
.type DefaultISR, %function
|
||||
DefaultISR:
|
||||
b DefaultISR
|
||||
.size DefaultISR, . - DefaultISR
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, DefaultISR
|
||||
.endm
|
||||
|
||||
/* Exception Handlers */
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DMA0_IRQHandler
|
||||
def_irq_handler DMA1_IRQHandler
|
||||
def_irq_handler DMA2_IRQHandler
|
||||
def_irq_handler DMA3_IRQHandler
|
||||
def_irq_handler DMA4_IRQHandler
|
||||
def_irq_handler DMA5_IRQHandler
|
||||
def_irq_handler DMA6_IRQHandler
|
||||
def_irq_handler DMA7_IRQHandler
|
||||
def_irq_handler DMA8_IRQHandler
|
||||
def_irq_handler DMA9_IRQHandler
|
||||
def_irq_handler DMA10_IRQHandler
|
||||
def_irq_handler DMA11_IRQHandler
|
||||
def_irq_handler DMA12_IRQHandler
|
||||
def_irq_handler DMA13_IRQHandler
|
||||
def_irq_handler DMA14_IRQHandler
|
||||
def_irq_handler DMA15_IRQHandler
|
||||
def_irq_handler DMA_Error_IRQHandler
|
||||
def_irq_handler MCM_IRQHandler
|
||||
def_irq_handler FTFE_IRQHandler
|
||||
def_irq_handler Read_Collision_IRQHandler
|
||||
def_irq_handler LVD_LVW_IRQHandler
|
||||
def_irq_handler LLW_IRQHandler
|
||||
def_irq_handler WDOG_EWM_IRQHandler
|
||||
def_irq_handler RNG_IRQHandler
|
||||
def_irq_handler I2C0_IRQHandler
|
||||
def_irq_handler I2C1_IRQHandler
|
||||
def_irq_handler SPI0_IRQHandler
|
||||
def_irq_handler SPI1_IRQHandler
|
||||
def_irq_handler I2S0_Tx_IRQHandler
|
||||
def_irq_handler I2S0_Rx_IRQHandler
|
||||
def_irq_handler UART0_LON_IRQHandler
|
||||
def_irq_handler UART0_RX_TX_IRQHandler
|
||||
def_irq_handler UART0_ERR_IRQHandler
|
||||
def_irq_handler UART1_RX_TX_IRQHandler
|
||||
def_irq_handler UART1_ERR_IRQHandler
|
||||
def_irq_handler UART2_RX_TX_IRQHandler
|
||||
def_irq_handler UART2_ERR_IRQHandler
|
||||
def_irq_handler UART3_RX_TX_IRQHandler
|
||||
def_irq_handler UART3_ERR_IRQHandler
|
||||
def_irq_handler ADC0_IRQHandler
|
||||
def_irq_handler CMP0_IRQHandler
|
||||
def_irq_handler CMP1_IRQHandler
|
||||
def_irq_handler FTM0_IRQHandler
|
||||
def_irq_handler FTM1_IRQHandler
|
||||
def_irq_handler FTM2_IRQHandler
|
||||
def_irq_handler CMT_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler RTC_Seconds_IRQHandler
|
||||
def_irq_handler PIT0_IRQHandler
|
||||
def_irq_handler PIT1_IRQHandler
|
||||
def_irq_handler PIT2_IRQHandler
|
||||
def_irq_handler PIT3_IRQHandler
|
||||
def_irq_handler PDB0_IRQHandler
|
||||
def_irq_handler USB0_IRQHandler
|
||||
def_irq_handler USBDCD_IRQHandler
|
||||
def_irq_handler Reserved71_IRQHandler
|
||||
def_irq_handler DAC0_IRQHandler
|
||||
def_irq_handler MCG_IRQHandler
|
||||
def_irq_handler LPTMR0_IRQHandler
|
||||
def_irq_handler PORTA_IRQHandler
|
||||
def_irq_handler PORTB_IRQHandler
|
||||
def_irq_handler PORTC_IRQHandler
|
||||
def_irq_handler PORTD_IRQHandler
|
||||
def_irq_handler PORTE_IRQHandler
|
||||
def_irq_handler SWI_IRQHandler
|
||||
def_irq_handler SPI2_IRQHandler
|
||||
def_irq_handler UART4_RX_TX_IRQHandler
|
||||
def_irq_handler UART4_ERR_IRQHandler
|
||||
def_irq_handler UART5_RX_TX_IRQHandler
|
||||
def_irq_handler UART5_ERR_IRQHandler
|
||||
def_irq_handler CMP2_IRQHandler
|
||||
def_irq_handler FTM3_IRQHandler
|
||||
def_irq_handler DAC1_IRQHandler
|
||||
def_irq_handler ADC1_IRQHandler
|
||||
def_irq_handler I2C2_IRQHandler
|
||||
def_irq_handler CAN0_ORed_Message_buffer_IRQHandler
|
||||
def_irq_handler CAN0_Bus_Off_IRQHandler
|
||||
def_irq_handler CAN0_Error_IRQHandler
|
||||
def_irq_handler CAN0_Tx_Warning_IRQHandler
|
||||
def_irq_handler CAN0_Rx_Warning_IRQHandler
|
||||
def_irq_handler CAN0_Wake_Up_IRQHandler
|
||||
def_irq_handler SDHC_IRQHandler
|
||||
def_irq_handler ENET_1588_Timer_IRQHandler
|
||||
def_irq_handler ENET_Transmit_IRQHandler
|
||||
def_irq_handler ENET_Receive_IRQHandler
|
||||
def_irq_handler ENET_Error_IRQHandler
|
||||
|
||||
.end
|
||||
597
targets/MK64F12/src/startup/iar/startup_MK64F12.s
Normal file
597
targets/MK64F12/src/startup/iar/startup_MK64F12.s
Normal file
File diff suppressed because it is too large
Load Diff
71
targets/MK64F12/src/startup/system_MK64F12.c
Normal file
71
targets/MK64F12/src/startup/system_MK64F12.c
Normal file
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "system_MK64F12.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "target_config.h"
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = kDefaultClock;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
|
||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||
#if (DISABLE_WDOG)
|
||||
/* Disable the WDOG module */
|
||||
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
|
||||
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
|
||||
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
|
||||
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
|
||||
/* WDOG->STCTRLH:
|
||||
* ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
|
||||
*/
|
||||
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
|
||||
WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
356
targets/MK64F12/src/startup/system_MK64F12.h
Normal file
356
targets/MK64F12/src/startup/system_MK64F12.h
Normal file
@@ -0,0 +1,356 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MK64FN1M0VDC12
|
||||
** MK64FN1M0VLL12
|
||||
** MK64FN1M0VLQ12
|
||||
** MK64FN1M0VMD12
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** GNU C Compiler - CodeSourcery Sourcery G++
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
|
||||
** Version: rev. 2.8, 2015-02-19
|
||||
** Build: b150225
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2013-08-12)
|
||||
** Initial version.
|
||||
** - rev. 2.0 (2013-10-29)
|
||||
** Register accessor macros added to the memory map.
|
||||
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||
** System initialization updated.
|
||||
** MCG - registers updated.
|
||||
** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
|
||||
** - rev. 2.1 (2013-10-30)
|
||||
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||
** - rev. 2.2 (2013-12-09)
|
||||
** DMA - EARS register removed.
|
||||
** AIPS0, AIPS1 - MPRA register updated.
|
||||
** - rev. 2.3 (2014-01-24)
|
||||
** Update according to reference manual rev. 2
|
||||
** ENET, MCG, MCM, SIM, USB - registers updated
|
||||
** - rev. 2.4 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
|
||||
** Update of SystemInit() and SystemCoreClockUpdate() functions.
|
||||
** - rev. 2.5 (2014-02-10)
|
||||
** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
|
||||
** Update of SystemInit() and SystemCoreClockUpdate() functions.
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
** - rev. 2.6 (2014-08-28)
|
||||
** Update of system files - default clock configuration changed.
|
||||
** Update of startup files - possibility to override DefaultISR added.
|
||||
** - rev. 2.7 (2014-10-14)
|
||||
** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
|
||||
** - rev. 2.8 (2015-02-19)
|
||||
** Renamed interrupt vector LLW to LLWU.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MK64F12
|
||||
* @version 2.8
|
||||
* @date 2015-02-19
|
||||
* @brief Device specific configuration file for MK64F12 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MK64F12_H_
|
||||
#define _SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* MCG mode constants */
|
||||
|
||||
#define MCG_MODE_FEI 0U
|
||||
#define MCG_MODE_FBI 1U
|
||||
#define MCG_MODE_BLPI 2U
|
||||
#define MCG_MODE_FEE 3U
|
||||
#define MCG_MODE_FBE 4U
|
||||
#define MCG_MODE_BLPE 5U
|
||||
#define MCG_MODE_PBE 6U
|
||||
#define MCG_MODE_PEE 7U
|
||||
|
||||
/* Predefined clock setups
|
||||
0 ... Default part configuration
|
||||
Multipurpose Clock Generator (MCG) in FEI mode.
|
||||
Reference clock source for MCG module: Slow internal reference clock
|
||||
Core clock = 20.97152MHz
|
||||
Bus clock = 20.97152MHz
|
||||
1 ... Maximum achievable clock frequency configuration
|
||||
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 120MHz
|
||||
Bus clock = 60MHz
|
||||
2 ... Chip internaly clocked, ready for Very Low Power Run mode.
|
||||
Multipurpose Clock Generator (MCG) in BLPI mode.
|
||||
Reference clock source for MCG module: Fast internal reference clock
|
||||
Core clock = 4MHz
|
||||
Bus clock = 4MHz
|
||||
3 ... Chip externally clocked, ready for Very Low Power Run mode.
|
||||
Multipurpose Clock Generator (MCG) in BLPE mode.
|
||||
Reference clock source for MCG module: RTC oscillator reference clock
|
||||
Core clock = 0.032768MHz
|
||||
Bus clock = 0.032768MHz
|
||||
4 ... USB clock setup
|
||||
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 120MHz
|
||||
Bus clock = 60MHz
|
||||
*/
|
||||
|
||||
/* Define clock source values */
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
|
||||
|
||||
/* RTC oscillator setting */
|
||||
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
|
||||
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
|
||||
|
||||
/* Low power mode enable */
|
||||
/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
|
||||
#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
|
||||
|
||||
/* Internal reference clock trim */
|
||||
/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
|
||||
#ifdef CLOCK_SETUP
|
||||
#if (CLOCK_SETUP == 0)
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
||||
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 1)
|
||||
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 2)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 3)
|
||||
#define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=1 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
||||
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 4)
|
||||
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
|
||||
/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
|
||||
#define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
|
||||
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2:
|
||||
* SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
|
||||
#endif
|
||||
#else
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* #if !defined(_SYSTEM_MK64F12_H_) */
|
||||
83
targets/MK64F12/src/target_config.h
Normal file
83
targets/MK64F12/src/target_config.h
Normal file
@@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#if !defined(__TARGET_CONFIG_H__)
|
||||
#define __TARGET_CONFIG_H__
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @brief Constants for clock frequencies.
|
||||
enum _target_clocks
|
||||
{
|
||||
kDefaultClock = 20971520u,
|
||||
//! Frequency of the HIRC.
|
||||
kHIRC = 48000000,
|
||||
|
||||
//! The minimum core clock cannot go below 20MHz when USB is enabled.
|
||||
kMinCoreClockWithUsbSupport = 20000000u,
|
||||
|
||||
//! The core/system clock cannot go above 120MHz.
|
||||
kMaxCoreClock = 120000000,
|
||||
|
||||
//! The bus clock cannot go above 60MHz.
|
||||
kMaxBusClock = 60000000,
|
||||
|
||||
//! The flex bus clock cannot go above 50MHz.
|
||||
kMaxFlexBusClock = 50000000,
|
||||
|
||||
//! The flash clock cannot go above 24MHz.
|
||||
kMaxFlashClock = 24000000,
|
||||
|
||||
//! Valid clock divider range
|
||||
kDivider_Min = 1,
|
||||
kDivider_Max = 16,
|
||||
};
|
||||
|
||||
//! @brief Constants for sram partition
|
||||
enum _sram_partition
|
||||
{
|
||||
kSram_LowerPart = 1,
|
||||
kSram_UpperPart = 3,
|
||||
};
|
||||
|
||||
//! @brief Version constants for the target.
|
||||
enum _target_version_constants
|
||||
{
|
||||
kTarget_Version_Name = 'T',
|
||||
kTarget_Version_Major = 1,
|
||||
kTarget_Version_Minor = 0,
|
||||
kTarget_Version_Bugfix = 0
|
||||
};
|
||||
|
||||
#endif // __TARGET_CONFIG_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
145
targets/MK64F12/src/usb_device_config.h
Normal file
145
targets/MK64F12/src/usb_device_config.h
Normal file
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __USB_DEVICE_CONFIG_H__
|
||||
#define __USB_DEVICE_CONFIG_H__ 1
|
||||
|
||||
#include "bootloader_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup usb_device_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @name Hardware instance define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief KHCI instance count */
|
||||
#define USB_DEVICE_CONFIG_KHCI (BL_CONFIG_USB_HID | BL_CONFIG_USB_MSC)
|
||||
|
||||
/*! @brief EHCI instance count */
|
||||
#define USB_DEVICE_CONFIG_EHCI (0U)
|
||||
|
||||
/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/
|
||||
#define USB_DEVICE_CONFIG_NUM (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI)
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name class instance define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief HID instance count */
|
||||
#define USB_DEVICE_CONFIG_HID (BL_CONFIG_USB_HID)
|
||||
|
||||
/*! @brief CDC ACM instance count */
|
||||
#define USB_DEVICE_CONFIG_CDC_ACM (0U)
|
||||
|
||||
/*! @brief MSC instance count */
|
||||
#define USB_DEVICE_CONFIG_MSC (BL_CONFIG_USB_MSC)
|
||||
|
||||
/*! @brief Audio instance count */
|
||||
#define USB_DEVICE_CONFIG_AUDIO (0U)
|
||||
|
||||
/*! @brief PHDC instance count */
|
||||
#define USB_DEVICE_CONFIG_PHDC (0U)
|
||||
|
||||
/*! @brief Video instance count */
|
||||
#define USB_DEVICE_CONFIG_VIDEO (0U)
|
||||
|
||||
/*! @brief CCID instance count */
|
||||
#define USB_DEVICE_CONFIG_CCID (0U)
|
||||
|
||||
/*! @brief Printer instance count */
|
||||
#define USB_DEVICE_CONFIG_PRINTER (0U)
|
||||
|
||||
/*! @brief DFU instance count */
|
||||
#define USB_DEVICE_CONFIG_DFU (0U)
|
||||
|
||||
/* @} */
|
||||
|
||||
/*! @brief Whether device is self power. 1 supported, 0 not supported */
|
||||
#define USB_DEVICE_CONFIG_SELF_POWER (1U)
|
||||
|
||||
/*! @brief Whether device remote wakeup supported. 1 supported, 0 not supported */
|
||||
#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
|
||||
|
||||
/*! @brief How many endpoints are supported in the stack. */
|
||||
#define USB_DEVICE_CONFIG_ENDPOINTS (8U)
|
||||
|
||||
/*! @brief Whether the device task is enabled. */
|
||||
#define USB_DEVICE_CONFIG_USE_TASK (0U)
|
||||
|
||||
/*! @brief How many the notification message are supported when the device task enabled. */
|
||||
#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U)
|
||||
|
||||
#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
|
||||
|
||||
/*! @brief The MAX buffer length for the KHCI DMA workaround.*/
|
||||
/* clang-format off */
|
||||
#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U)
|
||||
/*! @brief Whether handle the USB KHCI bus error. */
|
||||
#define USB_DEVICE_CONFIG_KHCI_ERROR_HANDLING (0U)
|
||||
/* clang-format on */
|
||||
#endif
|
||||
|
||||
#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
|
||||
/*! @brief How many the DTD are supported. */
|
||||
/* clang-format off */
|
||||
#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
|
||||
/*! @brief Whether handle the USB EHCI bus error. */
|
||||
#define USB_DEVICE_CONFIG_EHCI_ERROR_HANDLING (0U)
|
||||
/*! @brief Whether test mode enabled. */
|
||||
#define USB_DEVICE_CONFIG_EHCI_TEST_MODE (0U)
|
||||
/*! @brief Whether the EHCI ID pin detect feature enabled. */
|
||||
#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U)
|
||||
/* clang-format on */
|
||||
#endif
|
||||
|
||||
/*! @brief Whether the keep alive feature enabled. */
|
||||
/* clang-format off */
|
||||
#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U)
|
||||
|
||||
/*! @brief Whether the transfer buffer is cache-enabled or not. */
|
||||
#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
|
||||
|
||||
/*! @brief Whether the low power mode is enabled or not. */
|
||||
#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
|
||||
|
||||
/*! @brief Whether the device detached feature is enabled or not. */
|
||||
#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
|
||||
/* clang-format on */
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* __USB_DEVICE_CONFIG_H__ */
|
||||
Reference in New Issue
Block a user