Add KBOOT.
This commit is contained in:
László Monda
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/*
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* Copyright (c) 2014-2015, Freescale Semiconductor, Inc.
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* All rights reserved.
|
||||
*
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||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include "system_MK22F12810.h"
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#include "fsl_device_registers.h"
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#include "target_config.h"
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#ifndef DISABLE_WDOG
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#define DISABLE_WDOG 1
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#endif
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = kDefaultClock;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit(void)
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{
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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#if (DISABLE_WDOG)
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
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/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
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/* WDOG->STCTRLH:
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* ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
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*/
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WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
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WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
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#endif /* (DISABLE_WDOG) */
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}
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@@ -0,0 +1,362 @@
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/*
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** ###################################################################
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** GNU C Compiler - CodeSourcery Sourcery G++
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** IAR ANSI C/C++ Compiler for ARM
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**
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** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
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** Version: rev. 1.6, 2015-02-19
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** Build: b150225
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
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** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 1.0 (2013-11-01)
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** Initial version.
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** - rev. 1.1 (2013-12-20)
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** Update according to reference manual rev. 0.1,
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** - rev. 1.2 (2014-02-10)
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** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
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** - rev. 1.3 (2014-05-06)
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** Update according to reference manual rev. 1.0,
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** Update of system and startup files.
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** Module access macro module_BASES replaced by module_BASE_PTRS.
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** - rev. 1.4 (2014-08-28)
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** Update of system files - default clock configuration changed.
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** Update of startup files - possibility to override DefaultISR added.
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** - rev. 1.5 (2014-10-14)
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** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
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** - rev. 1.6 (2015-02-19)
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** Renamed interrupt vector LLW to LLWU.
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**
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** ###################################################################
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*/
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/*!
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* @file MK22F12810
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* @version 1.6
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* @date 2015-02-19
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* @brief Device specific configuration file for MK22F12810 (header file)
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*
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* Provides a system configuration function and a global variable that contains
|
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* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
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*/
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#ifndef _SYSTEM_MK22F12810_H_
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#define _SYSTEM_MK22F12810_H_ /**< Symbol preventing repeated inclusion */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#ifndef DISABLE_WDOG
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#define DISABLE_WDOG 1
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#endif
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/* MCG mode constants */
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#define MCG_MODE_FEI 0U
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#define MCG_MODE_FBI 1U
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#define MCG_MODE_BLPI 2U
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#define MCG_MODE_FEE 3U
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#define MCG_MODE_FBE 4U
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#define MCG_MODE_BLPE 5U
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/* Predefined clock setups
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0 ... Default part configuration
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Multipurpose Clock Generator (MCG) in FEI mode.
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Reference clock source for MCG module: Slow internal reference clock
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Core clock = 20.97152MHz
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Bus clock = 20.97152MHz
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1 ... Maximum achievable clock frequency configuration
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Multipurpose Clock Generator (MCG) in FEE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 80MHz
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Bus clock = 40MHz
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2 ... Internally clocked, ready for Very Low Power Run mode.
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Multipurpose Clock Generator (MCG) in BLPI mode.
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Reference clock source for MCG module: Fast internal reference clock
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Core clock = 4MHz
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Bus clock = 4MHz
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3 ... Externally clocked, ready for Very Low Power Run mode.
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Multipurpose Clock Generator (MCG) in BLPE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 4MHz
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Bus clock = 4MHz
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4 ... Maximum achievable clock frequency configuration, ready for USB operation.
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Multipurpose Clock Generator (MCG) in FEE mode.
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Reference clock source for MCG module: RTC oscillator reference clock
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Core clock = 95.977472MHz
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Bus clock = 47.988736MHz
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5 ... Maximum achievable clock frequency configuration in RUN mode
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Multipurpose Clock Generator (MCG) in FEE mode.
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Reference clock source for MCG module: RTC oscillator reference clock
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Core clock = 71.991296MHz
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Bus clock = 35.995648MHz
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*/
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/* Define clock source values */
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#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
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/* RTC oscillator setting */
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/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
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#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
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/* Low power mode enable */
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/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
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#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
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/* Internal reference clock trim */
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/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
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#ifdef CLOCK_SETUP
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#if (CLOCK_SETUP == 0)
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#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
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#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
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/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
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/* MCG_C5: */
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#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
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/* MCG_C6: CME=0 */
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#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
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/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
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/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 1)
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#define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
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#define MCG_MODE MCG_MODE_FEE /* Clock generator mode */
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/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=3,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x60U /* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
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/* MCG_C5: */
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#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
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/* MCG_C6: CME=0 */
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#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
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/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
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#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
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/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 */
|
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x01030000U /* SIM_CLKDIV1 */
|
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/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
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/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 2)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=4 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 3)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV4=7 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x11070000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 4)
|
||||
#define DEFAULT_SYSTEM_CLOCK 95977472u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_FEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x02U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=1,DRST_DRS=3,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0xE0U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=1 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01030000U /* SIM_CLKDIV1 */
|
||||
/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
|
||||
#define SYSTEM_SIM_CLKDIV2_VALUE 0x02U /* SIM_CLKDIV2 */
|
||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 5)
|
||||
#define DEFAULT_SYSTEM_CLOCK 71991296u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_FEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x02U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=1,DRST_DRS=2,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0xC0U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=1 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=2 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01020000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
||||
#endif
|
||||
#else
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* #if !defined(_SYSTEM_MK22F12810_H_) */
|
||||
Reference in New Issue
Block a user