Add KBOOT.
This commit is contained in:
László Monda
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,475 @@
|
||||
/* ---------------------------------------------------------------------------------------*/
|
||||
/* @file: startup_MK02F12810.s */
|
||||
/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
|
||||
/* MK02F12810 */
|
||||
/* @version: 0.3 */
|
||||
/* @date: 2015-2-19 */
|
||||
/* @build: b151111 */
|
||||
/* ---------------------------------------------------------------------------------------*/
|
||||
/* */
|
||||
/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without modification, */
|
||||
/* are permitted provided that the following conditions are met: */
|
||||
/* */
|
||||
/* o Redistributions of source code must retain the above copyright notice, this list */
|
||||
/* of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* o Redistributions in binary form must reproduce the above copyright notice, this */
|
||||
/* list of conditions and the following disclaimer in the documentation and/or */
|
||||
/* other materials provided with the distribution. */
|
||||
/* */
|
||||
/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
|
||||
/* contributors may be used to endorse or promote products derived from this */
|
||||
/* software without specific prior written permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
|
||||
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
|
||||
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
|
||||
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
|
||||
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
|
||||
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
|
||||
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
|
||||
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
|
||||
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/*****************************************************************************/
|
||||
/* Version: GCC for ARM Embedded Processors */
|
||||
/*****************************************************************************/
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .isr_vector, "a"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler*/
|
||||
.long HardFault_Handler /* Hard Fault Handler*/
|
||||
.long MemManage_Handler /* MPU Fault Handler*/
|
||||
.long BusFault_Handler /* Bus Fault Handler*/
|
||||
.long UsageFault_Handler /* Usage Fault Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long SVC_Handler /* SVCall Handler*/
|
||||
.long DebugMon_Handler /* Debug Monitor Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long PendSV_Handler /* PendSV Handler*/
|
||||
.long SysTick_Handler /* SysTick Handler*/
|
||||
|
||||
/* External Interrupts*/
|
||||
.long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/
|
||||
.long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/
|
||||
.long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/
|
||||
.long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/
|
||||
.long Reserved20_IRQHandler /* Reserved interrupt 20*/
|
||||
.long Reserved21_IRQHandler /* Reserved interrupt 21*/
|
||||
.long Reserved22_IRQHandler /* Reserved interrupt 22*/
|
||||
.long Reserved23_IRQHandler /* Reserved interrupt 23*/
|
||||
.long Reserved24_IRQHandler /* Reserved interrupt 24*/
|
||||
.long Reserved25_IRQHandler /* Reserved interrupt 25*/
|
||||
.long Reserved26_IRQHandler /* Reserved interrupt 26*/
|
||||
.long Reserved27_IRQHandler /* Reserved interrupt 27*/
|
||||
.long Reserved28_IRQHandler /* Reserved interrupt 28*/
|
||||
.long Reserved29_IRQHandler /* Reserved interrupt 29*/
|
||||
.long Reserved30_IRQHandler /* Reserved interrupt 30*/
|
||||
.long Reserved31_IRQHandler /* Reserved interrupt 31*/
|
||||
.long DMA_Error_IRQHandler /* DMA Error Interrupt*/
|
||||
.long MCM_IRQHandler /* Normal Interrupt*/
|
||||
.long FTF_IRQHandler /* FTFA Command complete interrupt*/
|
||||
.long Read_Collision_IRQHandler /* Read Collision Interrupt*/
|
||||
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
|
||||
.long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/
|
||||
.long WDOG_EWM_IRQHandler /* WDOG Interrupt*/
|
||||
.long Reserved39_IRQHandler /* Reserved Interrupt 39*/
|
||||
.long I2C0_IRQHandler /* I2C0 interrupt*/
|
||||
.long Reserved41_IRQHandler /* Reserved Interrupt 41*/
|
||||
.long SPI0_IRQHandler /* SPI0 Interrupt*/
|
||||
.long Reserved43_IRQHandler /* Reserved Interrupt 43*/
|
||||
.long Reserved44_IRQHandler /* Reserved Interrupt 44*/
|
||||
.long Reserved45_IRQHandler /* Reserved interrupt 45*/
|
||||
.long Reserved46_IRQHandler /* Reserved interrupt 46*/
|
||||
.long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
|
||||
.long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
|
||||
.long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
|
||||
.long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
|
||||
.long Reserved51_IRQHandler /* Reserved interrupt 51*/
|
||||
.long Reserved52_IRQHandler /* Reserved interrupt 52*/
|
||||
.long Reserved53_IRQHandler /* Reserved interrupt 53*/
|
||||
.long Reserved54_IRQHandler /* Reserved interrupt 54*/
|
||||
.long ADC0_IRQHandler /* ADC0 interrupt*/
|
||||
.long CMP0_IRQHandler /* CMP0 interrupt*/
|
||||
.long CMP1_IRQHandler /* CMP1 interrupt*/
|
||||
.long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
|
||||
.long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
|
||||
.long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
|
||||
.long Reserved61_IRQHandler /* Reserved interrupt 61*/
|
||||
.long Reserved62_IRQHandler /* Reserved interrupt 62*/
|
||||
.long Reserved63_IRQHandler /* Reserved interrupt 63*/
|
||||
.long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
|
||||
.long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
|
||||
.long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
|
||||
.long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
|
||||
.long PDB0_IRQHandler /* PDB0 Interrupt*/
|
||||
.long Reserved69_IRQHandler /* Reserved interrupt 69*/
|
||||
.long Reserved70_IRQHandler /* Reserved interrupt 70*/
|
||||
.long Reserved71_IRQHandler /* Reserved interrupt 71*/
|
||||
.long DAC0_IRQHandler /* DAC0 interrupt*/
|
||||
.long MCG_IRQHandler /* MCG Interrupt*/
|
||||
.long LPTMR0_IRQHandler /* LPTimer interrupt*/
|
||||
.long PORTA_IRQHandler /* Port A interrupt*/
|
||||
.long PORTB_IRQHandler /* Port B interrupt*/
|
||||
.long PORTC_IRQHandler /* Port C interrupt*/
|
||||
.long PORTD_IRQHandler /* Port D interrupt*/
|
||||
.long PORTE_IRQHandler /* Port E interrupt*/
|
||||
.long SWI_IRQHandler /* Software interrupt*/
|
||||
.long Reserved81_IRQHandler /* Reserved interrupt 81*/
|
||||
.long Reserved82_IRQHandler /* Reserved interrupt 82*/
|
||||
.long Reserved83_IRQHandler /* Reserved interrupt 83*/
|
||||
.long Reserved84_IRQHandler /* Reserved interrupt 84*/
|
||||
.long Reserved85_IRQHandler /* Reserved interrupt 85*/
|
||||
.long Reserved86_IRQHandler /* Reserved interrupt 86*/
|
||||
.long Reserved87_IRQHandler /* Reserved interrupt 87*/
|
||||
.long Reserved88_IRQHandler /* Reserved interrupt 88*/
|
||||
.long ADC1_IRQHandler /* ADC1 interrupt*/
|
||||
.long DefaultISR /* 90*/
|
||||
.long DefaultISR /* 91*/
|
||||
.long DefaultISR /* 92*/
|
||||
.long DefaultISR /* 93*/
|
||||
.long DefaultISR /* 94*/
|
||||
.long DefaultISR /* 95*/
|
||||
.long DefaultISR /* 96*/
|
||||
.long DefaultISR /* 97*/
|
||||
.long DefaultISR /* 98*/
|
||||
.long DefaultISR /* 99*/
|
||||
.long DefaultISR /* 100*/
|
||||
.long DefaultISR /* 101*/
|
||||
.long DefaultISR /* 102*/
|
||||
.long DefaultISR /* 103*/
|
||||
.long DefaultISR /* 104*/
|
||||
.long DefaultISR /* 105*/
|
||||
.long DefaultISR /* 106*/
|
||||
.long DefaultISR /* 107*/
|
||||
.long DefaultISR /* 108*/
|
||||
.long DefaultISR /* 109*/
|
||||
.long DefaultISR /* 110*/
|
||||
.long DefaultISR /* 111*/
|
||||
.long DefaultISR /* 112*/
|
||||
.long DefaultISR /* 113*/
|
||||
.long DefaultISR /* 114*/
|
||||
.long DefaultISR /* 115*/
|
||||
.long DefaultISR /* 116*/
|
||||
.long DefaultISR /* 117*/
|
||||
.long DefaultISR /* 118*/
|
||||
.long DefaultISR /* 119*/
|
||||
.long DefaultISR /* 120*/
|
||||
.long DefaultISR /* 121*/
|
||||
.long DefaultISR /* 122*/
|
||||
.long DefaultISR /* 123*/
|
||||
.long DefaultISR /* 124*/
|
||||
.long DefaultISR /* 125*/
|
||||
.long DefaultISR /* 126*/
|
||||
.long DefaultISR /* 127*/
|
||||
.long DefaultISR /* 128*/
|
||||
.long DefaultISR /* 129*/
|
||||
.long DefaultISR /* 130*/
|
||||
.long DefaultISR /* 131*/
|
||||
.long DefaultISR /* 132*/
|
||||
.long DefaultISR /* 133*/
|
||||
.long DefaultISR /* 134*/
|
||||
.long DefaultISR /* 135*/
|
||||
.long DefaultISR /* 136*/
|
||||
.long DefaultISR /* 137*/
|
||||
.long DefaultISR /* 138*/
|
||||
.long DefaultISR /* 139*/
|
||||
.long DefaultISR /* 140*/
|
||||
.long DefaultISR /* 141*/
|
||||
.long DefaultISR /* 142*/
|
||||
.long DefaultISR /* 143*/
|
||||
.long DefaultISR /* 144*/
|
||||
.long DefaultISR /* 145*/
|
||||
.long DefaultISR /* 146*/
|
||||
.long DefaultISR /* 147*/
|
||||
.long DefaultISR /* 148*/
|
||||
.long DefaultISR /* 149*/
|
||||
.long DefaultISR /* 150*/
|
||||
.long DefaultISR /* 151*/
|
||||
.long DefaultISR /* 152*/
|
||||
.long DefaultISR /* 153*/
|
||||
.long DefaultISR /* 154*/
|
||||
.long DefaultISR /* 155*/
|
||||
.long DefaultISR /* 156*/
|
||||
.long DefaultISR /* 157*/
|
||||
.long DefaultISR /* 158*/
|
||||
.long DefaultISR /* 159*/
|
||||
.long DefaultISR /* 160*/
|
||||
.long DefaultISR /* 161*/
|
||||
.long DefaultISR /* 162*/
|
||||
.long DefaultISR /* 163*/
|
||||
.long DefaultISR /* 164*/
|
||||
.long DefaultISR /* 165*/
|
||||
.long DefaultISR /* 166*/
|
||||
.long DefaultISR /* 167*/
|
||||
.long DefaultISR /* 168*/
|
||||
.long DefaultISR /* 169*/
|
||||
.long DefaultISR /* 170*/
|
||||
.long DefaultISR /* 171*/
|
||||
.long DefaultISR /* 172*/
|
||||
.long DefaultISR /* 173*/
|
||||
.long DefaultISR /* 174*/
|
||||
.long DefaultISR /* 175*/
|
||||
.long DefaultISR /* 176*/
|
||||
.long DefaultISR /* 177*/
|
||||
.long DefaultISR /* 178*/
|
||||
.long DefaultISR /* 179*/
|
||||
.long DefaultISR /* 180*/
|
||||
.long DefaultISR /* 181*/
|
||||
.long DefaultISR /* 182*/
|
||||
.long DefaultISR /* 183*/
|
||||
.long DefaultISR /* 184*/
|
||||
.long DefaultISR /* 185*/
|
||||
.long DefaultISR /* 186*/
|
||||
.long DefaultISR /* 187*/
|
||||
.long DefaultISR /* 188*/
|
||||
.long DefaultISR /* 189*/
|
||||
.long DefaultISR /* 190*/
|
||||
.long DefaultISR /* 191*/
|
||||
.long DefaultISR /* 192*/
|
||||
.long DefaultISR /* 193*/
|
||||
.long DefaultISR /* 194*/
|
||||
.long DefaultISR /* 195*/
|
||||
.long DefaultISR /* 196*/
|
||||
.long DefaultISR /* 197*/
|
||||
.long DefaultISR /* 198*/
|
||||
.long DefaultISR /* 199*/
|
||||
.long DefaultISR /* 200*/
|
||||
.long DefaultISR /* 201*/
|
||||
.long DefaultISR /* 202*/
|
||||
.long DefaultISR /* 203*/
|
||||
.long DefaultISR /* 204*/
|
||||
.long DefaultISR /* 205*/
|
||||
.long DefaultISR /* 206*/
|
||||
.long DefaultISR /* 207*/
|
||||
.long DefaultISR /* 208*/
|
||||
.long DefaultISR /* 209*/
|
||||
.long DefaultISR /* 210*/
|
||||
.long DefaultISR /* 211*/
|
||||
.long DefaultISR /* 212*/
|
||||
.long DefaultISR /* 213*/
|
||||
.long DefaultISR /* 214*/
|
||||
.long DefaultISR /* 215*/
|
||||
.long DefaultISR /* 216*/
|
||||
.long DefaultISR /* 217*/
|
||||
.long DefaultISR /* 218*/
|
||||
.long DefaultISR /* 219*/
|
||||
.long DefaultISR /* 220*/
|
||||
.long DefaultISR /* 221*/
|
||||
.long DefaultISR /* 222*/
|
||||
.long DefaultISR /* 223*/
|
||||
.long DefaultISR /* 224*/
|
||||
.long DefaultISR /* 225*/
|
||||
.long DefaultISR /* 226*/
|
||||
.long DefaultISR /* 227*/
|
||||
.long DefaultISR /* 228*/
|
||||
.long DefaultISR /* 229*/
|
||||
.long DefaultISR /* 230*/
|
||||
.long DefaultISR /* 231*/
|
||||
.long DefaultISR /* 232*/
|
||||
.long DefaultISR /* 233*/
|
||||
.long DefaultISR /* 234*/
|
||||
.long DefaultISR /* 235*/
|
||||
.long DefaultISR /* 236*/
|
||||
.long DefaultISR /* 237*/
|
||||
.long DefaultISR /* 238*/
|
||||
.long DefaultISR /* 239*/
|
||||
|
||||
#ifdef BL_HAS_BOOTLOADER_CONFIG
|
||||
|
||||
//__bootloaderConfigurationArea ; 0x3c0
|
||||
// .long 'kcfg' // [00:03] tag - Tag value used to validate the bootloader configuration data. Must be set to 'kcfg'
|
||||
.long 0x6766636b
|
||||
.long 0xFFFFFFFF // [04:07] crcStartAddress
|
||||
.long 0xFFFFFFFF // [08:0b] crcByteCount
|
||||
.long 0xFFFFFFFF // [0c:0f] crcExpectedValue
|
||||
.byte 0xFF // [10:10] enabledPeripherals
|
||||
.byte 0xFF // [11:11] i2cSlaveAddress
|
||||
.short 5000 // [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code
|
||||
.short 0xFFFF // [14:15] usbVid
|
||||
.short 0xFFFF // [16:17] usbPid
|
||||
.long 0xFFFFFFFF // [18:1b] usbStringsPointer
|
||||
.byte 0xFF // [1c:1c] clockFlags - High Speed and other clock options
|
||||
.byte 0xFF // [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1
|
||||
.short 0xFFFF // [1e:1f] reserved
|
||||
// Fill to align with flash configuration field.
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF // Reserved for user TRIM value
|
||||
#else
|
||||
//Fill to align with flash configuration field.
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF // Reserved for user TRIM value
|
||||
#endif // BL_HAS_BOOTLOADER_CONFIG
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Flash Configuration */
|
||||
.section .FlashConfig, "a"
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFE
|
||||
|
||||
.text
|
||||
.thumb
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
cpsid i /* Mask interrupts */
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
bl init_data_bss
|
||||
cpsie i /* Unmask interrupts */
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
#ifndef __ATOLLIC__
|
||||
bl __START
|
||||
#else
|
||||
bl __libc_init_array
|
||||
bl main
|
||||
#endif
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DefaultISR
|
||||
.type DefaultISR, %function
|
||||
DefaultISR:
|
||||
b DefaultISR
|
||||
.size DefaultISR, . - DefaultISR
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, DefaultISR
|
||||
.endm
|
||||
|
||||
/* Exception Handlers */
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DMA0_IRQHandler
|
||||
def_irq_handler DMA1_IRQHandler
|
||||
def_irq_handler DMA2_IRQHandler
|
||||
def_irq_handler DMA3_IRQHandler
|
||||
def_irq_handler Reserved20_IRQHandler
|
||||
def_irq_handler Reserved21_IRQHandler
|
||||
def_irq_handler Reserved22_IRQHandler
|
||||
def_irq_handler Reserved23_IRQHandler
|
||||
def_irq_handler Reserved24_IRQHandler
|
||||
def_irq_handler Reserved25_IRQHandler
|
||||
def_irq_handler Reserved26_IRQHandler
|
||||
def_irq_handler Reserved27_IRQHandler
|
||||
def_irq_handler Reserved28_IRQHandler
|
||||
def_irq_handler Reserved29_IRQHandler
|
||||
def_irq_handler Reserved30_IRQHandler
|
||||
def_irq_handler Reserved31_IRQHandler
|
||||
def_irq_handler DMA_Error_IRQHandler
|
||||
def_irq_handler MCM_IRQHandler
|
||||
def_irq_handler FTF_IRQHandler
|
||||
def_irq_handler Read_Collision_IRQHandler
|
||||
def_irq_handler LVD_LVW_IRQHandler
|
||||
def_irq_handler LLWU_IRQHandler
|
||||
def_irq_handler WDOG_EWM_IRQHandler
|
||||
def_irq_handler Reserved39_IRQHandler
|
||||
def_irq_handler I2C0_IRQHandler
|
||||
def_irq_handler Reserved41_IRQHandler
|
||||
def_irq_handler SPI0_IRQHandler
|
||||
def_irq_handler Reserved43_IRQHandler
|
||||
def_irq_handler Reserved44_IRQHandler
|
||||
def_irq_handler Reserved45_IRQHandler
|
||||
def_irq_handler Reserved46_IRQHandler
|
||||
def_irq_handler UART0_RX_TX_IRQHandler
|
||||
def_irq_handler UART0_ERR_IRQHandler
|
||||
def_irq_handler UART1_RX_TX_IRQHandler
|
||||
def_irq_handler UART1_ERR_IRQHandler
|
||||
def_irq_handler Reserved51_IRQHandler
|
||||
def_irq_handler Reserved52_IRQHandler
|
||||
def_irq_handler Reserved53_IRQHandler
|
||||
def_irq_handler Reserved54_IRQHandler
|
||||
def_irq_handler ADC0_IRQHandler
|
||||
def_irq_handler CMP0_IRQHandler
|
||||
def_irq_handler CMP1_IRQHandler
|
||||
def_irq_handler FTM0_IRQHandler
|
||||
def_irq_handler FTM1_IRQHandler
|
||||
def_irq_handler FTM2_IRQHandler
|
||||
def_irq_handler Reserved61_IRQHandler
|
||||
def_irq_handler Reserved62_IRQHandler
|
||||
def_irq_handler Reserved63_IRQHandler
|
||||
def_irq_handler PIT0_IRQHandler
|
||||
def_irq_handler PIT1_IRQHandler
|
||||
def_irq_handler PIT2_IRQHandler
|
||||
def_irq_handler PIT3_IRQHandler
|
||||
def_irq_handler PDB0_IRQHandler
|
||||
def_irq_handler Reserved69_IRQHandler
|
||||
def_irq_handler Reserved70_IRQHandler
|
||||
def_irq_handler Reserved71_IRQHandler
|
||||
def_irq_handler DAC0_IRQHandler
|
||||
def_irq_handler MCG_IRQHandler
|
||||
def_irq_handler LPTMR0_IRQHandler
|
||||
def_irq_handler PORTA_IRQHandler
|
||||
def_irq_handler PORTB_IRQHandler
|
||||
def_irq_handler PORTC_IRQHandler
|
||||
def_irq_handler PORTD_IRQHandler
|
||||
def_irq_handler PORTE_IRQHandler
|
||||
def_irq_handler SWI_IRQHandler
|
||||
def_irq_handler Reserved81_IRQHandler
|
||||
def_irq_handler Reserved82_IRQHandler
|
||||
def_irq_handler Reserved83_IRQHandler
|
||||
def_irq_handler Reserved84_IRQHandler
|
||||
def_irq_handler Reserved85_IRQHandler
|
||||
def_irq_handler Reserved86_IRQHandler
|
||||
def_irq_handler Reserved87_IRQHandler
|
||||
def_irq_handler Reserved88_IRQHandler
|
||||
def_irq_handler ADC1_IRQHandler
|
||||
|
||||
.end
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,119 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MK02FN128VFM10
|
||||
** MK02FN64VFM10
|
||||
** MK02FN128VLF10
|
||||
** MK02FN64VLF10
|
||||
** MK02FN128VLH10
|
||||
** MK02FN64VLH10
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K02P64M100SFARM, Rev. 0, February 14, 2014
|
||||
** Version: rev. 0.5, 2015-02-19
|
||||
** Build: b151215
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2014-02-24)
|
||||
** Initial version
|
||||
** - rev. 0.2 (2014-07-15)
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
** Update of system and startup files.
|
||||
** - rev. 0.3 (2014-08-28)
|
||||
** Update of system files - default clock configuration changed.
|
||||
** Update of startup files - possibility to override DefaultISR added.
|
||||
** - rev. 0.4 (2014-10-14)
|
||||
** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
|
||||
** - rev. 0.5 (2015-02-19)
|
||||
** Renamed interrupt vector LLW to LLWU.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MK02F12810
|
||||
* @version 0.5
|
||||
* @date 2015-02-19
|
||||
* @brief Device specific configuration file for MK02F12810 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "system_MK02F12810.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "target_config.h"
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = kDefaultClock;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
|
||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||
|
||||
#if (DISABLE_WDOG)
|
||||
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
|
||||
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
|
||||
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
|
||||
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
|
||||
/* WDOG->STCTRLH:
|
||||
* ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
|
||||
*/
|
||||
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
|
||||
WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
}
|
||||
@@ -0,0 +1,329 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MK02FN128VFM10
|
||||
** MK02FN64VFM10
|
||||
** MK02FN128VLF10
|
||||
** MK02FN64VLF10
|
||||
** MK02FN128VLH10
|
||||
** MK02FN64VLH10
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K02P64M100SFARM, Rev. 0, February 14, 2014
|
||||
** Version: rev. 0.5, 2015-02-19
|
||||
** Build: b151215
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2014-02-24)
|
||||
** Initial version
|
||||
** - rev. 0.2 (2014-07-15)
|
||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||
** Update of system and startup files.
|
||||
** - rev. 0.3 (2014-08-28)
|
||||
** Update of system files - default clock configuration changed.
|
||||
** Update of startup files - possibility to override DefaultISR added.
|
||||
** - rev. 0.4 (2014-10-14)
|
||||
** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
|
||||
** - rev. 0.5 (2015-02-19)
|
||||
** Renamed interrupt vector LLW to LLWU.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MK02F12810
|
||||
* @version 0.5
|
||||
* @date 2015-02-19
|
||||
* @brief Device specific configuration file for MK02F12810 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MK02F12810_H_
|
||||
#define _SYSTEM_MK02F12810_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* MCG mode constants */
|
||||
|
||||
#define MCG_MODE_FEI 0U
|
||||
#define MCG_MODE_FBI 1U
|
||||
#define MCG_MODE_BLPI 2U
|
||||
#define MCG_MODE_FEE 3U
|
||||
#define MCG_MODE_FBE 4U
|
||||
#define MCG_MODE_BLPE 5U
|
||||
|
||||
/* Predefined clock setups
|
||||
0 ... Default part configuration
|
||||
Multipurpose Clock Generator (MCG) in FEI mode.
|
||||
Reference clock source for MCG module: Slow internal reference clock
|
||||
Core clock = 20.97152MHz
|
||||
Bus clock = 20.97152MHz
|
||||
1 ... Maximum achievable clock frequency configuration
|
||||
Multipurpose Clock Generator (MCG) in FEE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 80MHz
|
||||
Bus clock = 40MHz
|
||||
2 ... Internally clocked, ready for Very Low Power Run mode.
|
||||
Multipurpose Clock Generator (MCG) in BLPI mode.
|
||||
Reference clock source for MCG module: Fast internal reference clock
|
||||
Core clock = 4MHz
|
||||
Bus clock = 4MHz
|
||||
3 ... Externally clocked, ready for Very Low Power Run mode.
|
||||
Multipurpose Clock Generator (MCG) in BLPE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 4MHz
|
||||
Bus clock = 4MHz
|
||||
4 ... Maximum achievable clock frequency configuration in RUN mode
|
||||
Multipurpose Clock Generator (MCG) in FEE mode.
|
||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||
Core clock = 60MHz
|
||||
Bus clock = 30MHz
|
||||
*/
|
||||
|
||||
/* Define clock source values */
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_XTAL32k_CLK_HZ 0u /* No RTC clock available */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
|
||||
|
||||
/* RTC oscillator setting */
|
||||
|
||||
/* Low power mode enable */
|
||||
/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
|
||||
#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
|
||||
|
||||
/* Internal reference clock trim */
|
||||
/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
|
||||
|
||||
#ifdef CLOCK_SETUP
|
||||
#if (CLOCK_SETUP == 0)
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 1)
|
||||
#define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_FEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=3,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x60U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01030000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 2)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=4 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 3)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV4=7 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x11070000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
||||
#elif(CLOCK_SETUP == 4)
|
||||
#define DEFAULT_SYSTEM_CLOCK 60000000u /* Default System clock value */
|
||||
#define MCG_MODE MCG_MODE_FEE /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
|
||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=2,FCTRIM=0,SCFTRIM=0 */
|
||||
#define SYSTEM_MCG_C4_VALUE 0x40U /* MCG_C4 */
|
||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||
/* MCG_C5: */
|
||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||
/* MCG_C6: CME=0 */
|
||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=2 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01020000U /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
||||
#else
|
||||
#error The selected clock setup is not supported.
|
||||
#endif
|
||||
#else
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MK02F12810_H_ */
|
||||
Reference in New Issue
Block a user