Add KBOOT.
This commit is contained in:
László Monda
49
apps/demo_qspi/rom_qspi_patch/src/hw_def.h
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49
apps/demo_qspi/rom_qspi_patch/src/hw_def.h
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __HW_DEF_H__
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#define __HW_DEF_H__
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// Note: the FAMILYID for K8x is 0x08 while it is 0x09 for KL8x.
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// So use the least-significant bit to distiguish K8x from KL8x.
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#define SIM_SDID_BASE (0x40048024ul)
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#define SIM_SDID_KL81_MASK (0x10000000ul)
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#define K8x_QuadSPI0_FLSHCR_BASE (0x400da00cul)
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#define KL8x_QuadSPI0_FLSHCR_BASE (0x4005a00cul)
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#define QuadSPI0_FLSHCR_TDH_MASK (0x00030000ul)
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#define QuadSPI0_FLSHCR_TDH_SHIFT (16)
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#define K8x_QuadSPI0_SOCCR_BASE (0x400DA024ul)
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#define KL8x_QuadSPI0_SOCCR_BASE (0x4005A024ul)
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#define QuadSPI0_SOCCR_DLYTAPSELA_SHIFT (16)
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#define QuadSPI0_SOCCR_DLYTAPSELA_MASK (0x003F0000ul)
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#define QuadSPI0_SOCCR_DLYTAPSELB_SHIFT (24)
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#define QuadSPI0_SOCCR_DLYTAPSELB_MASK (0x3F000000ul)
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#endif // #ifndef __HW_DEF_H__
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109
apps/demo_qspi/rom_qspi_patch/src/qspi.h
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apps/demo_qspi/rom_qspi_patch/src/qspi.h
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __QSPI_H__
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#define __QSPI_H__
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#include <stdint.h>
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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#define QSPI_LUT_MAX_ENTRIES 64
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#define QSPI_PRE_CMD_CNT 4 //!< the max number of pre commands
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#define QSPI_FEATURE_ENABLE 1
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typedef struct __sflash_configuration_parameter
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{
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uint32_t tag; //!< Set to magic number of 'kqcf'
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uint32_t version; //!< version of config struct
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//!< the version number i organized as following:
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uint32_t lengthInBytes; //!< Total length of strcut in bytes
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uint32_t dqs_loopback; //!< Sets DQS LoopBack Mode to enable Dummy Pad MCR[24]
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uint32_t data_hold_time; //!< Serial Flash Data In Hold time
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uint32_t reserved0[2]; //!< Reserved for K80
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uint32_t device_mode_config_en; //!< Determine if it is required to config working mode of external spi flash.
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uint32_t device_cmd; //!< Command to be tranferred to device
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uint32_t write_cmd_ipcr; //!< IPCR value of Write command
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uint32_t word_addressable; //!< Determine if the serial flash is word addressable
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uint32_t cs_hold_time; //!< CS hold time in terms of serial clock.(for example 1 serial clock cyle)
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uint32_t cs_setup_time; //!< CS setup time in terms of serial clock.(for example 1 serial clock cyle)
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uint32_t sflash_A1_size; //!< Size of flash connected on QSPI0A Ports and QSPI0A_SS0, in terms of Bytes
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uint32_t sflash_A2_size; //!< Size of flash connected on QSPI0A Ports and QSPI0A_SS1, in terms of Bytes
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uint32_t sflash_B1_size; //!< Size of flash connected on QSPI0B Ports and QSPI0B_SS0, in terms of Bytes
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uint32_t sflash_B2_size; //!< Size of flash connected on QSPI0B Ports and QSPI0B_SS1, in terms of Bytes
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uint32_t sclk_freq; //!< In 00 - 24MHz, 01 - 48MHz, 10 - 96MHz,(only for SDR Mode)
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uint32_t busy_bit_offset; //!< Flash device busy bit offset in status register
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uint32_t sflash_type; //!< SPI flash type: 0-Single,1--Dual 2--Quad, 3-- Octal
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uint32_t sflash_port; //!< 0--Only Port-A, 1--Both PortA and PortB
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uint32_t ddr_mode_enable; //!< Enable DDR mode if set to TRUE
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uint32_t dqs_enable; //!< Enable DQS mode if set to TRUE.
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uint32_t parallel_mode_enable; //!< Enable Individual or parrallel mode.
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uint32_t portA_cs1; //!< Enable PORTA CS1
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uint32_t portB_cs1; //!< Enable PORTB CS1
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uint32_t fsphs; //!< Full speed delay selection for SDR instructions
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uint32_t fsdly; //!< Full speed phase selection for SDR instructions
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uint32_t ddrsmp; //!< Select the sampling point for incomming data when serial flash is in DDR mdoe
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uint32_t
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look_up_table[QSPI_LUT_MAX_ENTRIES]; //!< Set of seq to perform optimum read on SFLASH as as per vendor SFLASH
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uint32_t column_address_space; //!< The width of the column address
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uint32_t config_cmd_en; //!< Enable config commands
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uint32_t config_cmds[QSPI_PRE_CMD_CNT]; //!< Config comands, used to configure nor flash
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uint32_t config_cmds_args[QSPI_PRE_CMD_CNT]; //!< Config commands arguments
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uint32_t differential_clock_pin_enable; //!< Differential flash clock pins enable
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uint32_t flash_CK2_clock_pin_enable; //!< Flash CK2 clock pin enable
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uint32_t dqs_inverse_sel; //!< Select clock source for internal DQS generation
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uint32_t dqs_latency_enable; //!< DQS Latency Enable
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uint32_t dqs_loopback_internal; //!< 0: dqs loopback from pad, 1: dqs loopback internally
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uint32_t dqs_phase_sel; //!< dqs phase sel
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uint32_t dqs_fa_delay_chain_sel; //!< dqs fa delay chain selection
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uint32_t dqs_fb_delay_chain_sel; //!< dqs fb delay chain selection
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uint32_t reserved1[2]; //!< reserved
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uint32_t pagesize; //!< page Size of Serial Flash
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uint32_t sectorsize; //!< sector Size of Serial Flash
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uint32_t timeout_milliseconds; //!< timeout in terms of millisecond in case of infinite loop in qspi driver
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//!< 0 represents disabling timeout check. This value is valid since version 1.1.0
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uint32_t ips_command_second_divider; //!< second devider for all IPS commands.
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uint32_t need_multi_phases; //!< Determine if multiple hases command are needed.
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uint32_t is_spansion_hyperflash; //!< Determine if connected spi flash device belongs to Hyperflash family
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uint32_t pre_read_status_cmd_address_offset; //!< Address for PreReadStatus command
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uint32_t pre_unlock_cmd_address_offset; //!< Address for PreWriteEnable command
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uint32_t unlock_cmd_address_offset; //!< Address for WriteEnable command
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uint32_t pre_program_cmd_address_offset; //!< Address for PreProgram command
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uint32_t pre_erase_cmd_address_offset; //!< Address for PreErase command
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uint32_t erase_all_cmd_address_offset; //!< Address for EraseAll command
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uint32_t reserved2[3]; //!< Reserved words to make sure qspi config block is page-aligend.
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} qspi_config_t, *SFLASH_CONFIGURATION_PARAM_PTR;
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#endif // #define __QSPI_H__
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66
apps/demo_qspi/rom_qspi_patch/src/rom_qspi_patch.c
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66
apps/demo_qspi/rom_qspi_patch/src/rom_qspi_patch.c
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@@ -0,0 +1,66 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qspi.h"
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#include "hw_def.h"
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enum
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{
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kStatus_Success = 0,
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};
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uint32_t rom_patch(qspi_config_t *base)
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{
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volatile uint32_t *qspi_flshcr_reg = (volatile uint32_t *)K8x_QuadSPI0_FLSHCR_BASE;
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volatile uint32_t *qspi_soccr_reg = (volatile uint32_t *)K8x_QuadSPI0_SOCCR_BASE;
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// This means the device belongs to KL series, namely, KL8x
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uint32_t sim_sdid = *(volatile uint32_t *)SIM_SDID_BASE;
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if (sim_sdid & SIM_SDID_KL81_MASK)
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{
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qspi_flshcr_reg = (volatile uint32_t *)KL8x_QuadSPI0_FLSHCR_BASE;
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qspi_soccr_reg = (volatile uint32_t *)KL8x_QuadSPI0_SOCCR_BASE;
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}
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// Set QuadSPI_FLSHCR[TDH] to given value.
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*qspi_flshcr_reg &= (uint32_t)~QuadSPI0_FLSHCR_TDH_MASK;
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*qspi_flshcr_reg |= (base->data_hold_time) << QuadSPI0_FLSHCR_TDH_SHIFT;
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// Set QuadSPI_SOCCR[DLYTAPSELA] to given value
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*qspi_soccr_reg &= (uint32_t)~QuadSPI0_SOCCR_DLYTAPSELA_MASK;
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*qspi_soccr_reg |=
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(base->dqs_fa_delay_chain_sel << QuadSPI0_SOCCR_DLYTAPSELA_SHIFT) & QuadSPI0_SOCCR_DLYTAPSELA_MASK;
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// Set QuadSPI_SOCCR[DLYTAPSELB] to given value
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*qspi_soccr_reg &= (uint32_t)~QuadSPI0_SOCCR_DLYTAPSELB_MASK;
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*qspi_soccr_reg |=
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(base->dqs_fb_delay_chain_sel << QuadSPI0_SOCCR_DLYTAPSELB_SHIFT) & QuadSPI0_SOCCR_DLYTAPSELB_MASK;
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return kStatus_Success;
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}
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