Add KBOOT.

apps/demo_qspi/bdfile/key.txt

@@ -0,0 +1 @@
+00112233445566778899aabbccddeeff

apps/demo_qspi/bdfile/program_keys.bd

@@ -0,0 +1,28 @@
+# No source file needed, keep this block empty
+sources {
+}
+
+# The section block specifies the sequence of boot commands to be written to the SB file.
+section (0) {
+
+    # Use the 'load ifr' statement to program the SB key to IFR memory.
+    # The SB key occupies IFR index 0x30-0x33.
+    # The SB key is 128-bit specifies as 4 little-endian long-word values.
+    # SB Key = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff}
+    load ifr 0x33221100 > 0x30;
+    load ifr 0x77665544 > 0x31;
+    load ifr 0xbbaa9988 > 0x32;
+    load ifr 0xffeeddcc > 0x33;
+    
+    # Use the 'load ifr' statement to program the OTFAD KEK to IFR memory.
+    # The KEK is used to unwrap(decrypt) the keyblob at boot time in order to correctly set up the OTFAD engine.
+    # The key is specified as 4 little-endian values, with the "least significant" key word going into the lowest IFR index
+    # KEK = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f}
+    load ifr 0x0f0e0d0c > 0x20;
+    load ifr 0x0b0a0908 > 0x21;
+    load ifr 0x07060504 > 0x22;
+    load ifr 0x03020100 > 0x23;
+    
+    # Reset target in order to let these keys take effect.
+    reset;
+}

apps/demo_qspi/bdfile/qspi_image_0000.bd

@@ -0,0 +1,35 @@
+# The sources block assigns file names to identifiers
+sources {
+    # SREC File path
+    mySrecFile = "led_demo_qspi_0000.srec";
+    # QCB file path 
+    qspiConfigBlock = "qspi_config_block.bin";
+}
+
+# The section block specifies the sequence of boot commands to be written to
+# the SB file
+section (0) {
+
+    #1. Erase the vector table and flash config field.
+    erase 0..0x800;
+    
+    # Step 2 and Step 3 are optional if the QuadSPI is configured at startup.
+    #2. Load the QCB to RAM
+    load qspiConfigBlock > 0x20000000;
+    
+    #3. Configure QuadSPI with the QCB above
+    enable qspi 0x20000000;
+    
+    #4. Erase the QuadSPI memory region before programming.
+    erase 0x68000000..0x68004000;
+    
+    #5.Load the QCB above to the start address of QuadSPI memory
+    load qspiConfigBlock > 0x68000000;
+    
+    #6,7. Load all the RO data from srec file, including vector table, flash config field and codes.
+    load mySrecFile;
+    
+    #8. Reset target.
+    reset;
+
+}

apps/demo_qspi/bdfile/qspi_image_a000.bd

@@ -0,0 +1,35 @@
+# The sources block assigns file names to identifiers
+sources {
+    # SREC File path
+    mySrecFile = "led_demo_qspi_a000.srec";
+    # QCB file path 
+    qspiConfigBlock = "qspi_config_block.bin";
+}
+
+# The section block specifies the sequence of boot commands to be written to
+# the SB file
+section (0) {
+
+    #1. Erase the vector table and flash config field.
+    erase 0xa000..0xa800;
+    
+    # Step 2 and Step 3 are optional if the QuadSPI is configured at startup.
+    #2. Load the QCB to RAM
+    load qspiConfigBlock > 0x20000000;
+    
+    #3. Configure QuadSPI with the QCB above
+    enable qspi 0x20000000;
+    
+    #4. Erase the QuadSPI memory region before programming.
+    erase 0x68000000..0x68004000;
+    
+    #5.Load the QCB above to the start address of QuadSPI memory
+    load qspiConfigBlock > 0x68000000;
+    
+    #6,7. Load all the RO data from srec file, including vector table, flash config field and codes.
+    load mySrecFile;
+    
+    #8. Reset target.
+    reset;
+
+}

apps/demo_qspi/bdfile/qspi_image_alias_a000.bd

@@ -0,0 +1,35 @@
+# The sources block assigns file names to identifiers
+sources {
+    # SREC File path
+    mySrecFile = "led_demo_qspi_alias_a000.srec";
+    # QCB file path 
+    qspiConfigBlock = "qspi_config_block.bin";
+}
+
+# The section block specifies the sequence of boot commands to be written to
+# the SB file
+section (0) {
+
+    #1. Erase the vector table and flash config field.
+    erase 0xa000..0xa800;
+    
+    # Step 2 and Step 3 are optional if the QuadSPI is configured at startup.
+    #2. Load the QCB to RAM
+    load qspiConfigBlock > 0x20000000;
+    
+    #3. Configure QuadSPI with the QCB above
+    enable qspi 0x20000000;
+    
+    #4. Erase the QuadSPI memory region before programming.
+    erase 0x04000000..0x04004000;
+    
+    #5.Load the QCB above to the start address of QuadSPI memory
+    load qspiConfigBlock > 0x68000000;
+    
+    #6. Load all boot_to_qspi_alias_memory applcation
+    load mySrecFile;
+    
+    #7. Reset target.
+    reset;
+
+}

apps/demo_qspi/bdfile/qspi_image_alias_encrypt_rom.bd

@@ -0,0 +1,70 @@
+# The sources block assigns file names to identifiers
+sources {
+    # SREC File path
+    mySrecFile = "boot_to_qspi_alias_memory_rom.srec";
+    # QCB file path 
+    qspiConfigBlock = "qspi_config_block.bin";
+    # Alias QSPI image file path
+    myBinFile = "led_demo_qspi_alias_rom.bin";
+}
+
+# The keyblob creates a structure with up to 4 keyblob entries.
+# The empty parentheses syntax specifies an entry of all zeros (no encryption)
+# Each entry consists of 4 parameters:
+# start     - start address of encrypted block.
+# end       - end address of encrypted block.
+# key       - AES-CTR mode encryption key for this range.
+# counter   - initial counter value for AES-CTR encryption for this range.
+keyblob (0) {
+    (
+        start=0x68001000,
+        end = 0x68001fff,
+        key="000102030405060708090a0b0c0d0e0f",
+        counter="0123456789abcdef"
+    )
+    ()
+    ()
+    ()
+}
+
+# The section block specifies the sequence of boot commands to be written to
+# the SB file
+section (0) {
+
+    #1. Erase the vector table and flash config field.
+    erase 0..0x800;
+    
+    # Step 2 and Step 3 are optional if the QuadSPI is configured at startup.
+    #2. Load the QCB to RAM
+    load qspiConfigBlock > 0x20000000;
+    
+    #3. Configure QuadSPI with the QCB above
+    enable qspi 0x20000000;
+    
+    #4. Erase the QuadSPI memory region before programming.
+    erase 0x68000000..0x68004000;
+    
+    #5.Load the QCB above to the start address of QuadSPI memory
+    load qspiConfigBlock > 0x68000000;
+    
+    #6. Load all boot_to_qspi_alias_memory applcation
+    load mySrecFile;
+    
+    #7. The encrypt argument (0) specifies the keyblob parameters range of one of the keyblob entries are left unencrypted.
+    encrypt(0) {
+        # Load alias QSPI image
+        load myBinFile > 0x68001000;
+    }
+    
+    #8. Load the encrypted keyblob block to specified location.
+    # The keywrap statement wraps (encrypts) the keyblob specified in the argument (0) using the specified Key Encryption Key (KEK) and loads the keyblob to internal flas.
+    # The load destination (0x1000, which is defined via keyBlobPointer in BCA) must match the defualt location (0x410) or the keyblob pointer in the Bootloader Configuraion Area(BCA) contained in the SREC image.
+    # Make sure the sector at 0x1000 has not been written by the srec file load above, otherwise it will need to be erased again.
+    keywrap (0) {
+        load {{000102030405060708090a0b0c0d0e0f}} > 0x1000;
+    }
+    
+    #9. Reset target.
+    reset;
+
+}

apps/demo_qspi/bdfile/qspi_image_alias_rom.bd

@@ -0,0 +1,40 @@
+# The sources block assigns file names to identifiers
+sources {
+    # SREC File path
+    mySrecFile = "boot_to_qspi_alias_memory_rom.srec";
+    # QCB file path 
+    qspiConfigBlock = "qspi_config_block.bin";
+    # Alias QSPI image file path
+    myBinFile = "led_demo_qspi_alias_rom.bin";
+}
+
+# The section block specifies the sequence of boot commands to be written to
+# the SB file
+section (0) {
+
+    #1. Erase the vector table and flash config field.
+    erase 0..0x800;
+    
+    # Step 2 and Step 3 are optional if the QuadSPI is configured at startup.
+    #2. Load the QCB to RAM
+    load qspiConfigBlock > 0x20000000;
+    
+    #3. Configure QuadSPI with the QCB above
+    enable qspi 0x20000000;
+    
+    #4. Erase the QuadSPI memory region before programming.
+    erase 0x68000000..0x68004000;
+    
+    #5.Load the QCB above to the start address of QuadSPI memory
+    load qspiConfigBlock > 0x68000000;
+    
+    #. Load all boot_to_qspi_alias_memory applcation
+    load mySrecFile;
+    
+    #7. Load Alias QSPI image
+    load myBinFile > 0x68001000;
+    
+    #8. Reset target.
+    reset;
+
+}

apps/demo_qspi/bdfile/qspi_image_encrypt_0000.bd

@@ -0,0 +1,67 @@
+# The sources block assigns file names to identifiers
+sources {
+    # SREC File path
+    mySrecFile = "led_demo_QSPI.srec";
+    # QCB file path 
+    qspiConfigBlock = "qspi_config_block.bin";
+}
+
+# The keyblob creates a structure with up to 4 keyblob entries.
+# The empty parentheses syntax specifies an entry of all zeros (no encryption)
+# Each entry consists of 4 parameters:
+# start     - start address of encrypted block.
+# end       - end address of encrypted block.
+# key       - AES-CTR mode encryption key for this range.
+# counter   - initial counter value for AES-CTR encryption for this range.
+keyblob (0) {
+    (
+        start=0x68001000,
+        end = 0x68001fff,
+        key="000102030405060708090a0b0c0d0e0f",
+        counter="0123456789abcdef"
+    )
+    ()
+    ()
+    ()
+}
+
+
+# The section block specifies the sequence of boot commands to be written to
+# the SB file
+section (0) {
+
+    #1. Erase the vector table and flash config field.
+    erase 0..0x800;
+    
+    # Step 2 and Step 3 are optional if the QuadSPI is configured at startup.
+    #2. Load the QCB to RAM
+    load qspiConfigBlock > 0x20000000;
+    
+    #3. Configure QuadSPI with the QCB above
+    enable qspi 0x20000000;
+    
+    #4. Erase the QuadSPI memory region before programming.
+    erase 0x68000000..0x68004000;
+    
+    #5.Load the QCB above to the start address of QuadSPI memory
+    load qspiConfigBlock > 0x68000000;
+    
+    #6,7. The encrypt statement indicates that load commands should encrypt load from the srec file using AES-CTR mode encrypteion.
+    # The encrypt argument (0) specifies the keyblob parameters range of one of the keyblob entries are left unencrypted.
+    encrypt(0) {
+        # Load all the RO data from SREC fiel.
+        load mySrecFile;
+    }
+    
+    #8. Load the encrypted keyblob block to specified location.
+    # The keywrap statement wraps (encrypts) the keyblob specified in the argument (0) using the specified Key Encryption Key (KEK) and loads the keyblob to internal flas.
+    # The load destination (0x1000, which is defined via keyBlobPointer in BCA) must match the defualt location (0x410) or the keyblob pointer in the Bootloader Configuraion Area(BCA) contained in the SREC image.
+    # Make sure the sector at 0x1000 has not been written by the srec file load above, otherwise it will need to be erased again.
+    keywrap (0) {
+        load {{000102030405060708090a0b0c0d0e0f}} > 0x1000;
+    }
+    
+    #9. Reset target.
+    reset;
+
+}

apps/demo_qspi/bdfile/qspi_image_encrypt_a000.bd

@@ -0,0 +1,70 @@
+# The sources block assigns file names to identifiers
+sources {
+    # SREC File path
+    mySrecFile = "led_demo_qspi_a000.srec";
+    # QCB file path 
+    qspiConfigBlock = "qspi_config_block.bin";
+}
+
+# The keyblob creates a structure with up to 4 keyblob entries.
+# The empty parentheses syntax specifies an entry of all zeros (no encryption)
+# Each entry consists of 4 parameters:
+# start     - start address of encrypted block.
+# end       - end address of encrypted block.
+# key       - AES-CTR mode encryption key for this range.
+# counter   - initial counter value for AES-CTR encryption for this range.
+keyblob (0) {
+    (
+        start=0x68001000,
+        end = 0x68001fff,
+        key="000102030405060708090a0b0c0d0e0f",
+        counter="0123456789abcdef"
+    )
+    ()
+    ()
+    ()
+}
+
+
+# The section block specifies the sequence of boot commands to be written to
+# the SB file
+section (0) {
+
+    #1. Erase the vector table and flash config field.
+    erase 0xa000..0xc000;
+    
+    # Step 2 and Step 3 are optional if the QuadSPI is configured at startup.
+    #2. Load the QCB to RAM
+    load qspiConfigBlock > 0x20000000;
+    
+    #3. Configure QuadSPI with the QCB above
+    enable qspi 0x20000000;
+    
+    #4. Erase the QuadSPI memory region before programming.
+    erase 0x68000000..0x68004000;
+    
+    #5.Load the QCB above to the start address of QuadSPI memory
+    load qspiConfigBlock > 0x68000000;
+    
+    #6,7. The encrypt statement indicates that load commands should encrypt load from the srec file using AES-CTR mode encrypteion.
+    # The encrypt argument (0) specifies the keyblob parameters range of one of the keyblob entries are left unencrypted.
+    encrypt(0) {
+        # Load all the RO data from SREC field.
+        load mySrecFile;
+    }
+    
+    #8. Load kek to 0xb000
+    load {{000102030405060708090a0b0c0d0e0f}} > 0xb000;
+    
+    #9. Load the encrypted keyblob block to specified location.
+    # The keywrap statement wraps (encrypts) the keyblob specified in the argument (0) using the specified Key Encryption Key (KEK) and loads the keyblob to internal flash.
+    # The load destination (0xc000, which is defined via keyBlobPointer in BCA) must match the keyblob pointer in the Bootloader Configuraion Area(BCA) contained in the SREC image.
+    # Make sure the sector at 0xc000 has not been written by the srec file load above, otherwise it will need to be erased again.
+    keywrap (0) {
+        load {{000102030405060708090a0b0c0d0e0f}} > 0xc000;
+    }
+    
+    #10. Reset target.
+    reset;
+
+}

apps/demo_qspi/bdfile/qspi_image_patch_rom.bd

@@ -0,0 +1,43 @@
+# The sources block assigns file names to identifiers
+sources {
+    # SREC File path
+    mySrecFile = "led_demo_qspi_patch_rom.srec";
+    # QCB file path 
+    qspiConfigBlock = "qspi_config_block.bin";
+    # ROM patch
+    rom_patch = "ROM_QSPI_patch.bin";
+}
+
+# The section block specifies the sequence of boot commands to be written to
+# the SB file
+section (0) {
+
+    #1. Erase the internal flash
+    erase 0..0x3000;
+    
+    # Step 2 and Step 3 are optional if the QuadSPI is configured at startup.
+    #2. Load the QCB to RAM
+    load qspiConfigBlock > 0x20000000;
+    
+    #3. Configure QuadSPI with the QCB above
+    enable qspi 0x20000000;
+    
+    #4. Load patch to RAM
+    load rom_patch > 0x20000200;
+    
+    #5. Call patch to invoke ROM workaround
+    call 0x20000201 (0x20000000);
+    
+    #6. Erase the QuadSPI memory region before programming.
+    erase 0x68000000..0x68090000;
+    
+    #7.Load the QCB above to the address specified by qspiConfigBlockPointer in BCA
+    load qspiConfigBlock > 0x2000;
+    
+    #8. Load all the RO data from srec file, including vector table, flash config field and codes.
+    load mySrecFile;
+    
+    #9. Reset target.
+    reset;
+
+}

apps/demo_qspi/led_demo/devices/MK80F25615/startup/gcc/startup_MK80F25615.S

@@ -0,0 +1,462 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3DFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK80F25615/startup/gcc/startup_MK80F25615_qspi.S

@@ -0,0 +1,462 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK80F25615/startup/gcc/startup_MK80F25615_qspi_patch.S

@@ -0,0 +1,470 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .section BootloaderPatchHandler, "a"
+    .thumb
+/* Reset Handler */
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    ldr r0, = ROM_PatchHandler
+    blx r0
+#ifndef __NO_SYSTEM_INIT
+    ldr r0, = SystemInit
+    blx r0
+#endif
+    ldr r0, = init_data_bss
+    blx r0
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr r0, = __START
+    blx r0
+#else
+    ldr r0,=    __libc_init_array
+    blx r0
+    ldr r0, = main,
+    bx r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .text
+    .thumb
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK80F25615/startup/system_MK80F25615.c

@@ -0,0 +1,316 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+#ifdef BOOTLOADER_CONFIG
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0x01F4U, /* Timeout :500ms */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,       /* No MMCAU configuration */
+      .keyBlobPointer = 0x00001000U,           /* keyblob data is at 0x1000 */
+      .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 20971520u;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if (DISABLE_WDOG)
+    /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+    /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+                                                   /* WDOG->STCTRLH:
+                                                    * ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
+                                                    */
+    WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
+                    WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
+#endif /* (DISABLE_WDOG) */
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+    uint16_t Divider;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
+    {
+        /* Output of FLL or PLL is selected */
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
+        {
+            /* FLL is selected */
+            if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
+            {
+                /* External reference clock is selected */
+                switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+                {
+                    case 0x00U:
+                        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                        break;
+                    case 0x01U:
+                        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                        break;
+                    case 0x02U:
+                    default:
+                        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                        break;
+                }
+                if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
+                {
+                    switch (MCG->C1 & MCG_C1_FRDIV_MASK)
+                    {
+                        case 0x38U:
+                            Divider = 1536U;
+                            break;
+                        case 0x30U:
+                            Divider = 1280U;
+                            break;
+                        default:
+                            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                            break;
+                    }
+                }
+                else
+                { /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+                    Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                }
+                MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+            }
+            else
+            {                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+                MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+            }                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+            /* Select correct multiplier to calculate the MCG output clock  */
+            switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
+            {
+                case 0x00U:
+                    MCGOUTClock *= 640U;
+                    break;
+                case 0x20U:
+                    MCGOUTClock *= 1280U;
+                    break;
+                case 0x40U:
+                    MCGOUTClock *= 1920U;
+                    break;
+                case 0x60U:
+                    MCGOUTClock *= 2560U;
+                    break;
+                case 0x80U:
+                    MCGOUTClock *= 732U;
+                    break;
+                case 0xA0U:
+                    MCGOUTClock *= 1464U;
+                    break;
+                case 0xC0U:
+                    MCGOUTClock *= 2197U;
+                    break;
+                case 0xE0U:
+                    MCGOUTClock *= 2929U;
+                    break;
+                default:
+                    break;
+            }
+        }
+        else
+        { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+            /* PLL is selected */
+            Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+            MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+            Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+            MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+            MCGOUTClock /= 2;       /* Calculate the MCG output clock */
+        }                           /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
+    {
+        /* Internal reference clock is selected */
+        if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
+        {
+            MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+        }
+        else
+        { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+            Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+            MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+        }                                                            /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
+    {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+        {
+            case 0x00U:
+                MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                break;
+            case 0x01U:
+                MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                break;
+            case 0x02U:
+            default:
+                MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                break;
+        }
+    }
+    else
+    { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+        /* Reserved value */
+        return;
+    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    SystemCoreClock =
+        (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

apps/demo_qspi/led_demo/devices/MK80F25615/startup/system_MK80F25615.h

@@ -0,0 +1,383 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK82F25615_H_
+#define SYSTEM_MK82F25615_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef DISABLE_WDOG
+#define DISABLE_WDOG 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximal speed configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 150MHz
+         Bus clock  = 75MHz
+   2 ... Chip internally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   4 ... USB clock setup.
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 144MHz
+         Bus clock  = 72MHz
+   5 ... Maximum achievable clock frequency configuration in RUN mode.
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ \
+    12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ                                                                       \
+    32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
+              */
+#define CPU_INT_SLOW_CLK_HZ 32768U   /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */      /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */      /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
+#define MCG_MODE MCG_MODE_FEI          /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+                                           /* SIM_SOPT2:
+                                            * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+                                            */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 1)
+#define DEFAULT_SYSTEM_CLOCK 150000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=9 */
+#define SYSTEM_MCG_C6_VALUE 0x49U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=5 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01150000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 2)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPI    /* Clock generator mode */
+/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 3)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPE    /* Clock generator mode */
+/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=2,OUTDIV2=2,OUTDIV3=2,OUTDIV4=0x0B */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x222B0000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 4)
+#define DEFAULT_SYSTEM_CLOCK 144000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=8 */
+#define SYSTEM_MCG_C6_VALUE 0x48U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=5 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01150000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=2,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x04U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 5)
+#define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=4 */
+#define SYSTEM_MCG_C6_VALUE 0x44U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#endif
+#else
+#define DEFAULT_SYSTEM_CLOCK 20971520u
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK82F25615_H_) */

apps/demo_qspi/led_demo/devices/MK80F25615/startup/system_MK80F25615_qspi.c

@@ -0,0 +1,304 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+#ifdef BOOTLOADER_CONFIG
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0x01F4U, /* timeout: 500ms */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,       /* No MMCAU configuration */
+      .keyBlobPointer = 0x000001000,           /* keyblob data is at 0x1000 */
+      .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 96000000ul;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+    uint16_t Divider;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
+    {
+        /* Output of FLL or PLL is selected */
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
+        {
+            /* FLL is selected */
+            if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
+            {
+                /* External reference clock is selected */
+                switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+                {
+                    case 0x00U:
+                        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                        break;
+                    case 0x01U:
+                        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                        break;
+                    case 0x02U:
+                    default:
+                        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                        break;
+                }
+                if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
+                {
+                    switch (MCG->C1 & MCG_C1_FRDIV_MASK)
+                    {
+                        case 0x38U:
+                            Divider = 1536U;
+                            break;
+                        case 0x30U:
+                            Divider = 1280U;
+                            break;
+                        default:
+                            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                            break;
+                    }
+                }
+                else
+                { /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+                    Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                }
+                MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+            }
+            else
+            {                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+                MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+            }                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+            /* Select correct multiplier to calculate the MCG output clock  */
+            switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
+            {
+                case 0x00U:
+                    MCGOUTClock *= 640U;
+                    break;
+                case 0x20U:
+                    MCGOUTClock *= 1280U;
+                    break;
+                case 0x40U:
+                    MCGOUTClock *= 1920U;
+                    break;
+                case 0x60U:
+                    MCGOUTClock *= 2560U;
+                    break;
+                case 0x80U:
+                    MCGOUTClock *= 732U;
+                    break;
+                case 0xA0U:
+                    MCGOUTClock *= 1464U;
+                    break;
+                case 0xC0U:
+                    MCGOUTClock *= 2197U;
+                    break;
+                case 0xE0U:
+                    MCGOUTClock *= 2929U;
+                    break;
+                default:
+                    break;
+            }
+        }
+        else
+        { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+            /* PLL is selected */
+            Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+            MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+            Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+            MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+            MCGOUTClock /= 2;       /* Calculate the MCG output clock */
+        }                           /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
+    {
+        /* Internal reference clock is selected */
+        if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
+        {
+            MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+        }
+        else
+        { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+            Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+            MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+        }                                                            /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
+    {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+        {
+            case 0x00U:
+                MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                break;
+            case 0x01U:
+                MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                break;
+            case 0x02U:
+            default:
+                MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                break;
+        }
+    }
+    else
+    { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+        /* Reserved value */
+        return;
+    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    SystemCoreClock =
+        (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

apps/demo_qspi/led_demo/devices/MK80F25615/startup/system_MK80F25615_qspi_patch.c

@@ -0,0 +1,235 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                   /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,       /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,      /* Disable CRC check */
+      .enabledPeripherals = 0x17,           /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,              /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 3000, /* timeout: 3000ms */
+      .usbVid = 0xFFFFU,                    /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                    /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,     /* Use default USB Strings */
+      .clockFlags = 0x01,                   /* Enable High speed mode */
+      .clockDivider = 0xFF,                 /* Use clock divider 1 */
+      .bootFlags = 0x01,                    /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,    /* No MMCAU configuration */
+      .keyBlobPointer = 0x000001000,        /* keyblob data is at 0x1000 */
+      .qspiConfigBlockPtr = 0x2000,         /* QCB is placed at 0x2000 */
+    };
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 96000000ul;
+
+/**
+ *  A section located at 0x410 used for storing ROM patch code
+ *
+ * pseudo-code:
+ *    int rom_patch(qspi_config_t *base)
+ *    {
+ *        volatile uint32_t *qspi_flshcr_reg = (volatile uint32_t*)QuadSPI0_FLSHCR_BASE;
+ *
+ *        // Set QuadSPI_FLSHCR[TDH] to given parameters.
+ *        *qspi_flshcr_reg &= (uint32_t)~QuadSPI_FLSHCR_TDH_MASK;
+ *        *qspi_flshcr_reg |= (base->data_hold_time)<<QuadSPI0_FLSHCR_TDH_SHIFT;
+ *
+ *        return kStatus_Success;
+    }
+ */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the rom patch code on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "rom_patch_code"
+const uint8_t s_rom_patch[124] @"rom_patch_code" =
+#elif defined(__GNUC__)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+
+#elif defined(__CC_ARM)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    { 0x10, 0xB5, 0x01, 0x00, 0x17, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x17, 0x4B, 0x1B, 0x68, 0xDB, 0x00, 0x02, 0xD5,
+      0x16, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x13, 0x68, 0x15, 0x4C, 0x1C, 0x40, 0x14, 0x60, 0x13, 0x68, 0x0C, 0x69,
+      0x24, 0x04, 0x1C, 0x43, 0x14, 0x60, 0x02, 0x68, 0x11, 0x4B, 0x13, 0x40, 0x03, 0x60, 0xDA, 0x22, 0x52, 0x00,
+      0x89, 0x18, 0x02, 0x68, 0x0B, 0x68, 0x1B, 0x04, 0xFC, 0x24, 0xA4, 0x03, 0x1C, 0x40, 0x14, 0x43, 0x04, 0x60,
+      0x02, 0x68, 0x0B, 0x4B, 0x13, 0x40, 0x03, 0x60, 0x02, 0x68, 0x49, 0x68, 0x09, 0x06, 0xFC, 0x23, 0x9B, 0x05,
+      0x0B, 0x40, 0x13, 0x43, 0x03, 0x60, 0x00, 0x20, 0x10, 0xBD, 0x0C, 0xA0, 0x0D, 0x40, 0x24, 0x80, 0x04, 0x40,
+      0x0C, 0xA0, 0x05, 0x40, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0 };
+
+/*
+ *   ROM patch handler for ROM patch code execution.
+ */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the ROM_PatchHandler on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "BootloaderPatchHandler"
+void ROM_PatchHandler(void) @"BootloaderPatchHandler"
+#elif defined(__GNUC__)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#else
+#error Unsupported compiler!
+#endif
+{
+    typedef int (*patch_handler_t)(uint32_t);
+
+#if defined(__IAR_SYSTEMS_ICC__)
+    uint32_t s_rom_patch_start = (uint32_t)__section_begin("rom_patch_code");
+#elif defined(__CC_ARM)
+    extern uint32_t Load$$EXEC_m_rom_patch_code$$Base[];
+    uint32_t s_rom_patch_start = (uint32_t)&Load$$EXEC_m_rom_patch_code$$Base;
+#elif defined(__GNUC__)
+    extern uint32_t rom_patch_code_start[];
+    uint32_t s_rom_patch_start = (uint32_t)&rom_patch_code_start;
+#endif
+
+    uint32_t patch_start = s_rom_patch_start + 1;
+    patch_handler_t patch_run = (patch_handler_t)patch_start;
+    patch_run(BootloaderConfig.qspiConfigBlockPtr);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+}

apps/demo_qspi/led_demo/devices/MK81F25615/startup/gcc/startup_MK82F25615.S

@@ -0,0 +1,462 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3DFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK81F25615/startup/gcc/startup_MK82F25615_qspi.S

@@ -0,0 +1,462 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK81F25615/startup/gcc/startup_MK82F25615_qspi_patch.S

@@ -0,0 +1,470 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .section BootloaderPatchHandler, "a"
+    .thumb
+/* Reset Handler */
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    ldr r0, = ROM_PatchHandler
+    blx r0
+#ifndef __NO_SYSTEM_INIT
+    ldr r0, = SystemInit
+    blx r0
+#endif
+    ldr r0, = init_data_bss
+    blx r0
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr r0, = __START
+    blx r0
+#else
+    ldr r0,=    __libc_init_array
+    blx r0
+    ldr r0, = main,
+    bx r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .text
+    .thumb
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK81F25615/startup/system_MK82F25615.c

@@ -0,0 +1,316 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+#ifdef BOOTLOADER_CONFIG
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0x01F4U, /* Timeout :500ms */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,       /* No MMCAU configuration */
+      .keyBlobPointer = 0x00001000U,           /* keyblob data is at 0x1000 */
+      .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 20971520u;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if (DISABLE_WDOG)
+    /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+    /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+                                                   /* WDOG->STCTRLH:
+                                                    * ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
+                                                    */
+    WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
+                    WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
+#endif /* (DISABLE_WDOG) */
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+    uint16_t Divider;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
+    {
+        /* Output of FLL or PLL is selected */
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
+        {
+            /* FLL is selected */
+            if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
+            {
+                /* External reference clock is selected */
+                switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+                {
+                    case 0x00U:
+                        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                        break;
+                    case 0x01U:
+                        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                        break;
+                    case 0x02U:
+                    default:
+                        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                        break;
+                }
+                if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
+                {
+                    switch (MCG->C1 & MCG_C1_FRDIV_MASK)
+                    {
+                        case 0x38U:
+                            Divider = 1536U;
+                            break;
+                        case 0x30U:
+                            Divider = 1280U;
+                            break;
+                        default:
+                            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                            break;
+                    }
+                }
+                else
+                { /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+                    Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                }
+                MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+            }
+            else
+            {                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+                MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+            }                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+            /* Select correct multiplier to calculate the MCG output clock  */
+            switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
+            {
+                case 0x00U:
+                    MCGOUTClock *= 640U;
+                    break;
+                case 0x20U:
+                    MCGOUTClock *= 1280U;
+                    break;
+                case 0x40U:
+                    MCGOUTClock *= 1920U;
+                    break;
+                case 0x60U:
+                    MCGOUTClock *= 2560U;
+                    break;
+                case 0x80U:
+                    MCGOUTClock *= 732U;
+                    break;
+                case 0xA0U:
+                    MCGOUTClock *= 1464U;
+                    break;
+                case 0xC0U:
+                    MCGOUTClock *= 2197U;
+                    break;
+                case 0xE0U:
+                    MCGOUTClock *= 2929U;
+                    break;
+                default:
+                    break;
+            }
+        }
+        else
+        { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+            /* PLL is selected */
+            Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+            MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+            Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+            MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+            MCGOUTClock /= 2;       /* Calculate the MCG output clock */
+        }                           /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
+    {
+        /* Internal reference clock is selected */
+        if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
+        {
+            MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+        }
+        else
+        { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+            Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+            MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+        }                                                            /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
+    {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+        {
+            case 0x00U:
+                MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                break;
+            case 0x01U:
+                MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                break;
+            case 0x02U:
+            default:
+                MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                break;
+        }
+    }
+    else
+    { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+        /* Reserved value */
+        return;
+    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    SystemCoreClock =
+        (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

apps/demo_qspi/led_demo/devices/MK81F25615/startup/system_MK82F25615.h

@@ -0,0 +1,383 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK82F25615_H_
+#define SYSTEM_MK82F25615_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef DISABLE_WDOG
+#define DISABLE_WDOG 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximal speed configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 150MHz
+         Bus clock  = 75MHz
+   2 ... Chip internally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   4 ... USB clock setup.
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 144MHz
+         Bus clock  = 72MHz
+   5 ... Maximum achievable clock frequency configuration in RUN mode.
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ \
+    12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ                                                                       \
+    32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
+              */
+#define CPU_INT_SLOW_CLK_HZ 32768U   /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */      /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */      /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
+#define MCG_MODE MCG_MODE_FEI          /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+                                           /* SIM_SOPT2:
+                                            * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+                                            */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 1)
+#define DEFAULT_SYSTEM_CLOCK 150000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=9 */
+#define SYSTEM_MCG_C6_VALUE 0x49U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=5 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01150000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 2)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPI    /* Clock generator mode */
+/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 3)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPE    /* Clock generator mode */
+/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=2,OUTDIV2=2,OUTDIV3=2,OUTDIV4=0x0B */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x222B0000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 4)
+#define DEFAULT_SYSTEM_CLOCK 144000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=8 */
+#define SYSTEM_MCG_C6_VALUE 0x48U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=5 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01150000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=2,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x04U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 5)
+#define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=4 */
+#define SYSTEM_MCG_C6_VALUE 0x44U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#endif
+#else
+#define DEFAULT_SYSTEM_CLOCK 20971520u
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK82F25615_H_) */

apps/demo_qspi/led_demo/devices/MK81F25615/startup/system_MK82F25615_qspi.c

@@ -0,0 +1,308 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+#ifdef BOOTLOADER_CONFIG
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0x01F4U, /* timeout: 500ms */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,       /* No MMCAU configuration */
+#ifdef BL_TARGET_FLASH
+      .keyBlobPointer = 0x0000c000,            /* keyblob data is ata 0xc000 */
+#else
+      .keyBlobPointer = 0x000001000,           /* keyblob data is at 0x1000 */
+#endif // BL_TARGET_FLASH
+      .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 96000000ul;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+    uint16_t Divider;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
+    {
+        /* Output of FLL or PLL is selected */
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
+        {
+            /* FLL is selected */
+            if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
+            {
+                /* External reference clock is selected */
+                switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+                {
+                    case 0x00U:
+                        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                        break;
+                    case 0x01U:
+                        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                        break;
+                    case 0x02U:
+                    default:
+                        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                        break;
+                }
+                if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
+                {
+                    switch (MCG->C1 & MCG_C1_FRDIV_MASK)
+                    {
+                        case 0x38U:
+                            Divider = 1536U;
+                            break;
+                        case 0x30U:
+                            Divider = 1280U;
+                            break;
+                        default:
+                            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                            break;
+                    }
+                }
+                else
+                { /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+                    Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                }
+                MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+            }
+            else
+            {                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+                MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+            }                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+            /* Select correct multiplier to calculate the MCG output clock  */
+            switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
+            {
+                case 0x00U:
+                    MCGOUTClock *= 640U;
+                    break;
+                case 0x20U:
+                    MCGOUTClock *= 1280U;
+                    break;
+                case 0x40U:
+                    MCGOUTClock *= 1920U;
+                    break;
+                case 0x60U:
+                    MCGOUTClock *= 2560U;
+                    break;
+                case 0x80U:
+                    MCGOUTClock *= 732U;
+                    break;
+                case 0xA0U:
+                    MCGOUTClock *= 1464U;
+                    break;
+                case 0xC0U:
+                    MCGOUTClock *= 2197U;
+                    break;
+                case 0xE0U:
+                    MCGOUTClock *= 2929U;
+                    break;
+                default:
+                    break;
+            }
+        }
+        else
+        { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+            /* PLL is selected */
+            Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+            MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+            Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+            MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+            MCGOUTClock /= 2;       /* Calculate the MCG output clock */
+        }                           /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
+    {
+        /* Internal reference clock is selected */
+        if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
+        {
+            MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+        }
+        else
+        { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+            Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+            MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+        }                                                            /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
+    {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+        {
+            case 0x00U:
+                MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                break;
+            case 0x01U:
+                MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                break;
+            case 0x02U:
+            default:
+                MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                break;
+        }
+    }
+    else
+    { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+        /* Reserved value */
+        return;
+    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    SystemCoreClock =
+        (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

apps/demo_qspi/led_demo/devices/MK81F25615/startup/system_MK82F25615_qspi_patch.c

@@ -0,0 +1,235 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                   /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,       /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,      /* Disable CRC check */
+      .enabledPeripherals = 0x17,           /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,              /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 3000, /* timeout: 3000ms */
+      .usbVid = 0xFFFFU,                    /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                    /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,     /* Use default USB Strings */
+      .clockFlags = 0x01,                   /* Enable High speed mode */
+      .clockDivider = 0xFF,                 /* Use clock divider 1 */
+      .bootFlags = 0x01,                    /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,    /* No MMCAU configuration */
+      .keyBlobPointer = 0x000001000,        /* keyblob data is at 0x1000 */
+      .qspiConfigBlockPtr = 0x2000,         /* QCB is placed at 0x2000 */
+    };
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 96000000ul;
+
+/**
+ *  A section located at 0x410 used for storing ROM patch code
+ *
+ * pseudo-code:
+ *    int rom_patch(qspi_config_t *base)
+ *    {
+ *        volatile uint32_t *qspi_flshcr_reg = (volatile uint32_t*)QuadSPI0_FLSHCR_BASE;
+ *
+ *        // Set QuadSPI_FLSHCR[TDH] to given parameters.
+ *        *qspi_flshcr_reg &= (uint32_t)~QuadSPI_FLSHCR_TDH_MASK;
+ *        *qspi_flshcr_reg |= (base->data_hold_time)<<QuadSPI0_FLSHCR_TDH_SHIFT;
+ *
+ *        return kStatus_Success;
+    }
+ */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the rom patch code on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "rom_patch_code"
+const uint8_t s_rom_patch[124] @"rom_patch_code" =
+#elif defined(__GNUC__)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+
+#elif defined(__CC_ARM)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    { 0x10, 0xB5, 0x01, 0x00, 0x17, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x17, 0x4B, 0x1B, 0x68, 0xDB, 0x00, 0x02, 0xD5,
+      0x16, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x13, 0x68, 0x15, 0x4C, 0x1C, 0x40, 0x14, 0x60, 0x13, 0x68, 0x0C, 0x69,
+      0x24, 0x04, 0x1C, 0x43, 0x14, 0x60, 0x02, 0x68, 0x11, 0x4B, 0x13, 0x40, 0x03, 0x60, 0xDA, 0x22, 0x52, 0x00,
+      0x89, 0x18, 0x02, 0x68, 0x0B, 0x68, 0x1B, 0x04, 0xFC, 0x24, 0xA4, 0x03, 0x1C, 0x40, 0x14, 0x43, 0x04, 0x60,
+      0x02, 0x68, 0x0B, 0x4B, 0x13, 0x40, 0x03, 0x60, 0x02, 0x68, 0x49, 0x68, 0x09, 0x06, 0xFC, 0x23, 0x9B, 0x05,
+      0x0B, 0x40, 0x13, 0x43, 0x03, 0x60, 0x00, 0x20, 0x10, 0xBD, 0x0C, 0xA0, 0x0D, 0x40, 0x24, 0x80, 0x04, 0x40,
+      0x0C, 0xA0, 0x05, 0x40, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0 };
+
+/*
+ *   ROM patch handler for ROM patch code execution.
+ */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the ROM_PatchHandler on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "BootloaderPatchHandler"
+void ROM_PatchHandler(void) @"BootloaderPatchHandler"
+#elif defined(__GNUC__)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#else
+#error Unsupported compiler!
+#endif
+{
+    typedef int (*patch_handler_t)(uint32_t);
+
+#if defined(__IAR_SYSTEMS_ICC__)
+    uint32_t s_rom_patch_start = (uint32_t)__section_begin("rom_patch_code");
+#elif defined(__CC_ARM)
+    extern uint32_t Load$$EXEC_m_rom_patch_code$$Base[];
+    uint32_t s_rom_patch_start = (uint32_t)&Load$$EXEC_m_rom_patch_code$$Base;
+#elif defined(__GNUC__)
+    extern uint32_t rom_patch_code_start[];
+    uint32_t s_rom_patch_start = (uint32_t)&rom_patch_code_start;
+#endif
+
+    uint32_t patch_start = s_rom_patch_start + 1;
+    patch_handler_t patch_run = (patch_handler_t)patch_start;
+    patch_run(BootloaderConfig.qspiConfigBlockPtr);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+}

apps/demo_qspi/led_demo/devices/MK82F25615/startup/gcc/startup_MK82F25615.S

@@ -0,0 +1,462 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3DFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK82F25615/startup/gcc/startup_MK82F25615_qspi.S

@@ -0,0 +1,462 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK82F25615/startup/gcc/startup_MK82F25615_qspi_patch.S

@@ -0,0 +1,470 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK82F25615.s                                                        */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK82F25615                                                                  */
+/*  @version: 1.1                                                                         */
+/*  @date:    2015-5-28                                                                   */
+/*  @build:   b150626                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA16_IRQHandler                           /* DMA channel 0,16 transfer complete*/
+    .long   DMA1_DMA17_IRQHandler                           /* DMA channel 1,17 transfer complete*/
+    .long   DMA2_DMA18_IRQHandler                           /* DMA channel 2,18 transfer complete*/
+    .long   DMA3_DMA19_IRQHandler                           /* DMA channel 3,19 transfer complete*/
+    .long   DMA4_DMA20_IRQHandler                           /* DMA channel 4,20 transfer complete*/
+    .long   DMA5_DMA21_IRQHandler                           /* DMA channel 5,21 transfer complete*/
+    .long   DMA6_DMA22_IRQHandler                           /* DMA channel 6,22 transfer complete*/
+    .long   DMA7_DMA23_IRQHandler                           /* DMA channel 7,23 transfer complete*/
+    .long   DMA8_DMA24_IRQHandler                           /* DMA channel 8,24 transfer complete*/
+    .long   DMA9_DMA25_IRQHandler                           /* DMA channel 9,25 transfer complete*/
+    .long   DMA10_DMA26_IRQHandler                          /* DMA channel 10,26 transfer complete*/
+    .long   DMA11_DMA27_IRQHandler                          /* DMA channel 11,27 transfer complete*/
+    .long   DMA12_DMA28_IRQHandler                          /* DMA channel 12,28 transfer complete*/
+    .long   DMA13_DMA29_IRQHandler                          /* DMA channel 13,29 transfer complete*/
+    .long   DMA14_DMA30_IRQHandler                          /* DMA channel 14,30 transfer complete*/
+    .long   DMA15_DMA31_IRQHandler                          /* DMA channel 15,31 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 31 error*/
+    .long   MCM_IRQHandler                                  /* MCM normal interrupt*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete*/
+    .long   Read_Collision_IRQHandler                       /* FTFA read collision*/
+    .long   LVD_LVW_IRQHandler                              /* PMC controller low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup unit*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator*/
+    .long   I2C0_IRQHandler                                 /* Inter-integrated circuit 0*/
+    .long   I2C1_IRQHandler                                 /* Inter-integrated circuit 1*/
+    .long   SPI0_IRQHandler                                 /* Serial peripheral Interface 0*/
+    .long   SPI1_IRQHandler                                 /* Serial peripheral Interface 1*/
+    .long   I2S0_Tx_IRQHandler                              /* Integrated interchip sound 0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* Integrated interchip sound 0 receive interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 receive/transmit/error interrupt*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 receive/transmit/error interrupt*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 receive/transmit/error interrupt*/
+    .long   LPUART3_IRQHandler                              /* LPUART3 receive/transmit/error interrupt*/
+    .long   LPUART4_IRQHandler                              /* LPUART4 receive/transmit/error interrupt*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved52_IRQHandler                           /* Reserved interrupt*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-digital converter 0*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0*/
+    .long   CMP1_IRQHandler                                 /* Comparator 1*/
+    .long   FTM0_IRQHandler                                 /* FlexTimer module 0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FlexTimer module 1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FlexTimer module 2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* Carrier modulator transmitter*/
+    .long   RTC_IRQHandler                                  /* Real time clock*/
+    .long   RTC_Seconds_IRQHandler                          /* Real time clock seconds*/
+    .long   PIT0CH0_IRQHandler                              /* Periodic interrupt timer 0 channel 0*/
+    .long   PIT0CH1_IRQHandler                              /* Periodic interrupt timer 0 channel 1*/
+    .long   PIT0CH2_IRQHandler                              /* Periodic interrupt timer 0 channel 2*/
+    .long   PIT0CH3_IRQHandler                              /* Periodic interrupt timer 0 channel 3*/
+    .long   PDB0_IRQHandler                                 /* Programmable delay block*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   USBDCD_IRQHandler                               /* USB charger detect*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator*/
+    .long   LPTMR0_LPTMR1_IRQHandler                        /* Single interrupt vector for  Low Power Timer 0 and 1*/
+    .long   PORTA_IRQHandler                                /* Port A pin detect interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B pin detect interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C pin detect interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D pin detect interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E pin detect interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* Serial peripheral Interface 2*/
+    .long   Reserved82_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved83_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved84_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved85_IRQHandler                           /* Reserved interrupt*/
+    .long   FLEXIO0_IRQHandler                              /* FLEXIO0*/
+    .long   FTM3_IRQHandler                                 /* FlexTimer module 3 fault, overflow and channels interrupt*/
+    .long   Reserved88_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved89_IRQHandler                           /* Reserved interrupt*/
+    .long   I2C2_IRQHandler                                 /* Inter-integrated circuit 2*/
+    .long   Reserved91_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved92_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved93_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved94_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved95_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved96_IRQHandler                           /* Reserved interrupt*/
+    .long   SDHC_IRQHandler                                 /* Secured digital host controller*/
+    .long   Reserved98_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved99_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved100_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved101_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved102_IRQHandler                          /* Reserved interrupt*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   Reserved106_IRQHandler                          /* Reserved interrupt*/
+    .long   I2C3_IRQHandler                                 /* Inter-integrated circuit 3*/
+    .long   Reserved108_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved109_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved110_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved111_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved112_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved113_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved114_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved115_IRQHandler                          /* Reserved interrupt*/
+    .long   QuadSPI0_IRQHandler                             /* qspi*/
+    .long   Reserved117_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved118_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved119_IRQHandler                          /* Reserved interrupt*/
+    .long   LTC0_IRQHandler                                 /* LP Trusted Cryptography*/
+    .long   Reserved121_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved122_IRQHandler                          /* Reserved interrupt*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .section BootloaderPatchHandler, "a"
+    .thumb
+/* Reset Handler */
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    ldr r0, = ROM_PatchHandler
+    blx r0
+#ifndef __NO_SYSTEM_INIT
+    ldr r0, = SystemInit
+    blx r0
+#endif
+    ldr r0, = init_data_bss
+    blx r0
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr r0, = __START
+    blx r0
+#else
+    ldr r0,=    __libc_init_array
+    blx r0
+    ldr r0, = main,
+    bx r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .text
+    .thumb
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA16_IRQHandler
+    def_irq_handler    DMA1_DMA17_IRQHandler
+    def_irq_handler    DMA2_DMA18_IRQHandler
+    def_irq_handler    DMA3_DMA19_IRQHandler
+    def_irq_handler    DMA4_DMA20_IRQHandler
+    def_irq_handler    DMA5_DMA21_IRQHandler
+    def_irq_handler    DMA6_DMA22_IRQHandler
+    def_irq_handler    DMA7_DMA23_IRQHandler
+    def_irq_handler    DMA8_DMA24_IRQHandler
+    def_irq_handler    DMA9_DMA25_IRQHandler
+    def_irq_handler    DMA10_DMA26_IRQHandler
+    def_irq_handler    DMA11_DMA27_IRQHandler
+    def_irq_handler    DMA12_DMA28_IRQHandler
+    def_irq_handler    DMA13_DMA29_IRQHandler
+    def_irq_handler    DMA14_DMA30_IRQHandler
+    def_irq_handler    DMA15_DMA31_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    LPUART3_IRQHandler
+    def_irq_handler    LPUART4_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    Reserved52_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0CH0_IRQHandler
+    def_irq_handler    PIT0CH1_IRQHandler
+    def_irq_handler    PIT0CH2_IRQHandler
+    def_irq_handler    PIT0CH3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_LPTMR1_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    Reserved82_IRQHandler
+    def_irq_handler    Reserved83_IRQHandler
+    def_irq_handler    Reserved84_IRQHandler
+    def_irq_handler    Reserved85_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    Reserved88_IRQHandler
+    def_irq_handler    Reserved89_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    Reserved91_IRQHandler
+    def_irq_handler    Reserved92_IRQHandler
+    def_irq_handler    Reserved93_IRQHandler
+    def_irq_handler    Reserved94_IRQHandler
+    def_irq_handler    Reserved95_IRQHandler
+    def_irq_handler    Reserved96_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    Reserved98_IRQHandler
+    def_irq_handler    Reserved99_IRQHandler
+    def_irq_handler    Reserved100_IRQHandler
+    def_irq_handler    Reserved101_IRQHandler
+    def_irq_handler    Reserved102_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    Reserved106_IRQHandler
+    def_irq_handler    I2C3_IRQHandler
+    def_irq_handler    Reserved108_IRQHandler
+    def_irq_handler    Reserved109_IRQHandler
+    def_irq_handler    Reserved110_IRQHandler
+    def_irq_handler    Reserved111_IRQHandler
+    def_irq_handler    Reserved112_IRQHandler
+    def_irq_handler    Reserved113_IRQHandler
+    def_irq_handler    Reserved114_IRQHandler
+    def_irq_handler    Reserved115_IRQHandler
+    def_irq_handler    QuadSPI0_IRQHandler
+    def_irq_handler    Reserved117_IRQHandler
+    def_irq_handler    Reserved118_IRQHandler
+    def_irq_handler    Reserved119_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    Reserved121_IRQHandler
+    def_irq_handler    Reserved122_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MK82F25615/startup/system_MK82F25615.c

@@ -0,0 +1,316 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+#ifdef BOOTLOADER_CONFIG
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0x01F4U, /* Timeout :500ms */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,       /* No MMCAU configuration */
+      .keyBlobPointer = 0x00001000U,           /* keyblob data is at 0x1000 */
+      .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 20971520u;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if (DISABLE_WDOG)
+    /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+    /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+                                                   /* WDOG->STCTRLH:
+                                                    * ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0
+                                                    */
+    WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK |
+                    WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U;
+#endif /* (DISABLE_WDOG) */
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+    uint16_t Divider;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
+    {
+        /* Output of FLL or PLL is selected */
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
+        {
+            /* FLL is selected */
+            if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
+            {
+                /* External reference clock is selected */
+                switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+                {
+                    case 0x00U:
+                        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                        break;
+                    case 0x01U:
+                        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                        break;
+                    case 0x02U:
+                    default:
+                        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                        break;
+                }
+                if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
+                {
+                    switch (MCG->C1 & MCG_C1_FRDIV_MASK)
+                    {
+                        case 0x38U:
+                            Divider = 1536U;
+                            break;
+                        case 0x30U:
+                            Divider = 1280U;
+                            break;
+                        default:
+                            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                            break;
+                    }
+                }
+                else
+                { /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+                    Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                }
+                MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+            }
+            else
+            {                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+                MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+            }                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+            /* Select correct multiplier to calculate the MCG output clock  */
+            switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
+            {
+                case 0x00U:
+                    MCGOUTClock *= 640U;
+                    break;
+                case 0x20U:
+                    MCGOUTClock *= 1280U;
+                    break;
+                case 0x40U:
+                    MCGOUTClock *= 1920U;
+                    break;
+                case 0x60U:
+                    MCGOUTClock *= 2560U;
+                    break;
+                case 0x80U:
+                    MCGOUTClock *= 732U;
+                    break;
+                case 0xA0U:
+                    MCGOUTClock *= 1464U;
+                    break;
+                case 0xC0U:
+                    MCGOUTClock *= 2197U;
+                    break;
+                case 0xE0U:
+                    MCGOUTClock *= 2929U;
+                    break;
+                default:
+                    break;
+            }
+        }
+        else
+        { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+            /* PLL is selected */
+            Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+            MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+            Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+            MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+            MCGOUTClock /= 2;       /* Calculate the MCG output clock */
+        }                           /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
+    {
+        /* Internal reference clock is selected */
+        if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
+        {
+            MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+        }
+        else
+        { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+            Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+            MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+        }                                                            /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
+    {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+        {
+            case 0x00U:
+                MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                break;
+            case 0x01U:
+                MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                break;
+            case 0x02U:
+            default:
+                MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                break;
+        }
+    }
+    else
+    { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+        /* Reserved value */
+        return;
+    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    SystemCoreClock =
+        (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

apps/demo_qspi/led_demo/devices/MK82F25615/startup/system_MK82F25615.h

@@ -0,0 +1,383 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK82F25615_H_
+#define SYSTEM_MK82F25615_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef DISABLE_WDOG
+#define DISABLE_WDOG 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximal speed configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 150MHz
+         Bus clock  = 75MHz
+   2 ... Chip internally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   4 ... USB clock setup.
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 144MHz
+         Bus clock  = 72MHz
+   5 ... Maximum achievable clock frequency configuration in RUN mode.
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ \
+    12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ                                                                       \
+    32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
+              */
+#define CPU_INT_SLOW_CLK_HZ 32768U   /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */      /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */      /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
+#define MCG_MODE MCG_MODE_FEI          /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+                                           /* SIM_SOPT2:
+                                            * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+                                            */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 1)
+#define DEFAULT_SYSTEM_CLOCK 150000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=9 */
+#define SYSTEM_MCG_C6_VALUE 0x49U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=5 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01150000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 2)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPI    /* Clock generator mode */
+/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 3)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPE    /* Clock generator mode */
+/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=2,OUTDIV2=2,OUTDIV3=2,OUTDIV4=0x0B */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x222B0000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 4)
+#define DEFAULT_SYSTEM_CLOCK 144000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=8 */
+#define SYSTEM_MCG_C6_VALUE 0x48U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=5 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01150000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=2,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x04U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 5)
+#define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=4 */
+#define SYSTEM_MCG_C6_VALUE 0x44U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#endif
+#else
+#define DEFAULT_SYSTEM_CLOCK 20971520u
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK82F25615_H_) */

apps/demo_qspi/led_demo/devices/MK82F25615/startup/system_MK82F25615_qspi.c

@@ -0,0 +1,308 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+#ifdef BOOTLOADER_CONFIG
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0x01F4U, /* timeout: 500ms */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,       /* No MMCAU configuration */
+#ifdef BL_TARGET_FLASH
+      .keyBlobPointer = 0x0000c000,            /* keyblob data is ata 0xc000 */
+#else
+      .keyBlobPointer = 0x000001000,           /* keyblob data is at 0x1000 */
+#endif // BL_TARGET_FLASH
+      .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 96000000ul;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+    uint16_t Divider;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
+    {
+        /* Output of FLL or PLL is selected */
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
+        {
+            /* FLL is selected */
+            if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
+            {
+                /* External reference clock is selected */
+                switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+                {
+                    case 0x00U:
+                        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                        break;
+                    case 0x01U:
+                        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                        break;
+                    case 0x02U:
+                    default:
+                        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                        break;
+                }
+                if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
+                {
+                    switch (MCG->C1 & MCG_C1_FRDIV_MASK)
+                    {
+                        case 0x38U:
+                            Divider = 1536U;
+                            break;
+                        case 0x30U:
+                            Divider = 1280U;
+                            break;
+                        default:
+                            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                            break;
+                    }
+                }
+                else
+                { /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+                    Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                }
+                MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+            }
+            else
+            {                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+                MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+            }                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+            /* Select correct multiplier to calculate the MCG output clock  */
+            switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
+            {
+                case 0x00U:
+                    MCGOUTClock *= 640U;
+                    break;
+                case 0x20U:
+                    MCGOUTClock *= 1280U;
+                    break;
+                case 0x40U:
+                    MCGOUTClock *= 1920U;
+                    break;
+                case 0x60U:
+                    MCGOUTClock *= 2560U;
+                    break;
+                case 0x80U:
+                    MCGOUTClock *= 732U;
+                    break;
+                case 0xA0U:
+                    MCGOUTClock *= 1464U;
+                    break;
+                case 0xC0U:
+                    MCGOUTClock *= 2197U;
+                    break;
+                case 0xE0U:
+                    MCGOUTClock *= 2929U;
+                    break;
+                default:
+                    break;
+            }
+        }
+        else
+        { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+            /* PLL is selected */
+            Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+            MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+            Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+            MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+            MCGOUTClock /= 2;       /* Calculate the MCG output clock */
+        }                           /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
+    {
+        /* Internal reference clock is selected */
+        if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
+        {
+            MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+        }
+        else
+        { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+            Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+            MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+        }                                                            /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
+    {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+        {
+            case 0x00U:
+                MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                break;
+            case 0x01U:
+                MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                break;
+            case 0x02U:
+            default:
+                MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                break;
+        }
+    }
+    else
+    { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+        /* Reserved value */
+        return;
+    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    SystemCoreClock =
+        (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

apps/demo_qspi/led_demo/devices/MK82F25615/startup/system_MK82F25615_qspi_patch.c

@@ -0,0 +1,235 @@
+/*
+** ###################################################################
+**     Processors:          MK82FN256CAx15
+**                          MK82FN256VDC15
+**                          MK82FN256VLL15
+**                          MK82FN256VLQ15
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K82P121M150SF5RM, Rev. 0, May 2015
+**     Version:             rev. 1.1, 2015-05-28
+**     Build:               b150626
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-09)
+**         Initial version
+**     - rev. 1.1 (2015-05-28)
+**         Update according to the reference manual Rev. 0.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK82F25615
+ * @version 1.1
+ * @date 2015-05-28
+ * @brief Device specific configuration file for MK82F25615 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t mmcauConfigPointer; /*!< A pointer to the MMCAU configuration structure in memory. */
+    uint32_t keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+    uint8_t RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED3[12];
+} system_bootloader_config_t;
+
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                   /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,       /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,      /* Disable CRC check */
+      .enabledPeripherals = 0x17,           /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,              /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 3000, /* timeout: 3000ms */
+      .usbVid = 0xFFFFU,                    /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                    /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,     /* Use default USB Strings */
+      .clockFlags = 0x01,                   /* Enable High speed mode */
+      .clockDivider = 0xFF,                 /* Use clock divider 1 */
+      .bootFlags = 0x01,                    /* Enable communication with host */
+      .mmcauConfigPointer = 0xFFFFFFFFU,    /* No MMCAU configuration */
+      .keyBlobPointer = 0x000001000,        /* keyblob data is at 0x1000 */
+      .qspiConfigBlockPtr = 0x2000,         /* QCB is placed at 0x2000 */
+    };
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 96000000ul;
+
+/**
+ *  A section located at 0x410 used for storing ROM patch code
+ *
+ * pseudo-code:
+ *    int rom_patch(qspi_config_t *base)
+ *    {
+ *        volatile uint32_t *qspi_flshcr_reg = (volatile uint32_t*)QuadSPI0_FLSHCR_BASE;
+ *
+ *        // Set QuadSPI_FLSHCR[TDH] to given parameters.
+ *        *qspi_flshcr_reg &= (uint32_t)~QuadSPI_FLSHCR_TDH_MASK;
+ *        *qspi_flshcr_reg |= (base->data_hold_time)<<QuadSPI0_FLSHCR_TDH_SHIFT;
+ *
+ *        return kStatus_Success;
+    }
+ */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the rom patch code on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "rom_patch_code"
+const uint8_t s_rom_patch[124] @"rom_patch_code" =
+#elif defined(__GNUC__)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+
+#elif defined(__CC_ARM)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    { 0x10, 0xB5, 0x01, 0x00, 0x17, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x17, 0x4B, 0x1B, 0x68, 0xDB, 0x00, 0x02, 0xD5,
+      0x16, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x13, 0x68, 0x15, 0x4C, 0x1C, 0x40, 0x14, 0x60, 0x13, 0x68, 0x0C, 0x69,
+      0x24, 0x04, 0x1C, 0x43, 0x14, 0x60, 0x02, 0x68, 0x11, 0x4B, 0x13, 0x40, 0x03, 0x60, 0xDA, 0x22, 0x52, 0x00,
+      0x89, 0x18, 0x02, 0x68, 0x0B, 0x68, 0x1B, 0x04, 0xFC, 0x24, 0xA4, 0x03, 0x1C, 0x40, 0x14, 0x43, 0x04, 0x60,
+      0x02, 0x68, 0x0B, 0x4B, 0x13, 0x40, 0x03, 0x60, 0x02, 0x68, 0x49, 0x68, 0x09, 0x06, 0xFC, 0x23, 0x9B, 0x05,
+      0x0B, 0x40, 0x13, 0x43, 0x03, 0x60, 0x00, 0x20, 0x10, 0xBD, 0x0C, 0xA0, 0x0D, 0x40, 0x24, 0x80, 0x04, 0x40,
+      0x0C, 0xA0, 0x05, 0x40, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0 };
+
+/*
+ *   ROM patch handler for ROM patch code execution.
+ */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the ROM_PatchHandler on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "BootloaderPatchHandler"
+void ROM_PatchHandler(void) @"BootloaderPatchHandler"
+#elif defined(__GNUC__)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#else
+#error Unsupported compiler!
+#endif
+{
+    typedef int (*patch_handler_t)(uint32_t);
+
+#if defined(__IAR_SYSTEMS_ICC__)
+    uint32_t s_rom_patch_start = (uint32_t)__section_begin("rom_patch_code");
+#elif defined(__CC_ARM)
+    extern uint32_t Load$$EXEC_m_rom_patch_code$$Base[];
+    uint32_t s_rom_patch_start = (uint32_t)&Load$$EXEC_m_rom_patch_code$$Base;
+#elif defined(__GNUC__)
+    extern uint32_t rom_patch_code_start[];
+    uint32_t s_rom_patch_start = (uint32_t)&rom_patch_code_start;
+#endif
+
+    uint32_t patch_start = s_rom_patch_start + 1;
+    patch_handler_t patch_run = (patch_handler_t)patch_start;
+    patch_run(BootloaderConfig.qspiConfigBlockPtr);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+}

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/arm/startup_MKL81Z7.s

@@ -0,0 +1,463 @@
+; * ---------------------------------------------------------------------------------------
+; *  @file:    startup_MKL82Z7.s
+; *  @purpose: CMSIS Cortex-M0P Core Device Startup File
+; *            MKL82Z7
+; *  @version: 1.4
+; *  @date:    2015-8-28
+; *  @build:   b150910
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler                         ;NMI Handler
+                DCD     HardFault_Handler                   ;Hard Fault Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     SVC_Handler                         ;SVCall Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     PendSV_Handler                      ;PendSV Handler
+                DCD     SysTick_Handler                     ;SysTick Handler
+
+                                                            ;External Interrupts
+                DCD     DMA0_DMA4_IRQHandler                ;DMA channel 0, 4 transfer complete
+                DCD     DMA1_DMA5_IRQHandler                ;DMA channel 1, 5 transfer complete
+                DCD     DMA2_DMA6_IRQHandler                ;DMA channel 2, 6 transfer complete
+                DCD     DMA3_DMA7_IRQHandler                ;DMA channel 3, 7 transfer complete
+                DCD     DMA_Error_IRQHandler                ;DMA channel 0 - 7 error
+                DCD     FLEXIO0_IRQHandler                  ;Flexible IO
+                DCD     TPM0_IRQHandler                     ;Timer/PWM module 0
+                DCD     TPM1_IRQHandler                     ;Timer/PWM module 1
+                DCD     TPM2_IRQHandler                     ;Timer/PWM module 2
+                DCD     PIT0_IRQHandler                     ;Periodic Interrupt Timer 0
+                DCD     SPI0_IRQHandler                     ;Serial Peripheral Interface 0
+                DCD     EMVSIM0_IRQHandler                  ;EMVSIM0 common interrupt
+                DCD     LPUART0_IRQHandler                  ;LPUART0 status and error
+                DCD     LPUART1_IRQHandler                  ;LPUART1 status and error
+                DCD     I2C0_IRQHandler                     ;Inter-Integrated Circuit 0
+                DCD     QSPI0_IRQHandler                    ;QuadSPI0 interrupt
+                DCD     Reserved32_IRQHandler               ;DryIce tamper detect
+                DCD     PORTA_IRQHandler                    ;Pin detect Port A
+                DCD     PORTB_IRQHandler                    ;Pin detect Port B
+                DCD     PORTC_IRQHandler                    ;Pin detect Port C
+                DCD     PORTD_IRQHandler                    ;Pin detect Port D
+                DCD     PORTE_IRQHandler                    ;Pin detect Port E
+                DCD     LLWU_IRQHandler                     ;Low Leakage Wakeup
+                DCD     LTC0_IRQHandler                     ;Low power trusted cryptographic
+                DCD     USB0_IRQHandler                     ;USB OTG interrupt
+                DCD     ADC0_IRQHandler                     ;Analog-to-Digital Converter 0
+                DCD     LPTMR0_IRQHandler                   ;Low-Power Timer 0
+                DCD     RTC_Seconds_IRQHandler              ;RTC seconds
+                DCD     INTMUX0_0_IRQHandler                ;Selectable peripheral interrupt INTMUX0-0
+                DCD     INTMUX0_1_IRQHandler                ;Selectable peripheral interrupt INTMUX0-1
+                DCD     INTMUX0_2_IRQHandler                ;Selectable peripheral interrupt INTMUX0-2
+                DCD     INTMUX0_3_IRQHandler                ;Selectable peripheral interrupt INTMUX0-3
+                DCD     LPTMR1_IRQHandler                   ;Low-Power Timer 1 (INTMUX source IRQ0)
+                DCD     Reserved49_IRQHandler               ;Reserved interrupt (INTMUX source IRQ1)
+                DCD     Reserved50_IRQHandler               ;Reserved interrupt (INTMUX source IRQ2)
+                DCD     Reserved51_IRQHandler               ;Reserved interrupt (INTMUX source IRQ3)
+                DCD     SPI1_IRQHandler                     ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+                DCD     LPUART2_IRQHandler                  ;LPUART2 status and error (INTMUX source IRQ5)
+                DCD     EMVSIM1_IRQHandler                  ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+                DCD     I2C1_IRQHandler                     ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+                DCD     TSI0_IRQHandler                     ;Touch Sensing Input 0 (INTMUX source IRQ8)
+                DCD     PMC_IRQHandler                      ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+                DCD     FTFA_IRQHandler                     ;FTFA command complete/read collision (INTMUX source IRQ10)
+                DCD     MCG_IRQHandler                      ;Multipurpose clock generator (INTMUX source IRQ11)
+                DCD     WDOG_EWM_IRQHandler                 ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+                DCD     DAC0_IRQHandler                     ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+                DCD     TRNG0_IRQHandler                    ;True randon number generator (INTMUX source IRQ14)
+                DCD     Reserved63_IRQHandler               ;Reserved interrupt (INTMUX source IRQ15)
+                DCD     CMP0_IRQHandler                     ;Comparator 0 (INTMUX source IRQ16)
+                DCD     Reserved65_IRQHandler               ;Reserved interrupt (INTMUX source IRQ17)
+                DCD     RTC_Alarm_IRQHandler                ;Real time clock (INTMUX source IRQ18)
+                DCD     Reserved67_IRQHandler               ;Reserved interrupt (INTMUX source IRQ19)
+                DCD     Reserved68_IRQHandler               ;Reserved interrupt (INTMUX source IRQ20)
+                DCD     Reserved69_IRQHandler               ;Reserved interrupt (INTMUX source IRQ21)
+                DCD     Reserved70_IRQHandler               ;Reserved interrupt (INTMUX source IRQ22)
+                DCD     Reserved71_IRQHandler               ;Reserved interrupt (INTMUX source IRQ23)
+                DCD     DMA4_IRQHandler                     ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+                DCD     DMA5_IRQHandler                     ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+                DCD     DMA6_IRQHandler                     ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+                DCD     DMA7_IRQHandler                     ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+                DCD     Reserved76_IRQHandler               ;Reserved interrupt (INTMUX source IRQ28)
+                DCD     Reserved77_IRQHandler               ;Reserved interrupt (INTMUX source IRQ29)
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt (INTMUX source IRQ30)
+                DCD     Reserved79_IRQHandler               ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict access to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>
+;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>
+;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>
+;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>
+;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>
+;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>
+;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>
+;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program Flash Region Protect Register 0
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0> LPBOOT
+;       <0=> Low-power boot
+;       <1=> Normal boot
+;     <o.1> BOOTPIN_OPT
+;       <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+;       <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+;     <o.2> NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI_b pin/interrupts reset default to enabled
+;     <o.5> FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+;     <o.6..7> BOOTSRC_SEL
+;       <0=> Boot from Flash
+;       <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
+;       <3=> Boot from ROM and enter boot loader mode.
+;         <i> Boot source selection
+FOPT          EQU     0x3D
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor Key Security Enable
+FSEC          EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    FlashConfig, DATA, READONLY
+__FlashConfig
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3
+                DCB     FSEC      , FOPT      , 0xFF      , 0xFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  init_data_bss
+                IMPORT  __main
+
+                IF      :LNOT::DEF:RAM_TARGET
+                REQUIRE FlashConfig
+                ENDIF
+
+                CPSID   I               ; Mask interrupts
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =init_data_bss
+                BLX     R0
+                CPSIE   i               ; Unmask interrupts
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler         [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler         [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler         [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+Default_Handler\
+                PROC
+                EXPORT  DMA0_DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA1_DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA2_DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA3_DMA7_IRQHandler         [WEAK]
+                EXPORT  DMA_Error_IRQHandler         [WEAK]
+                EXPORT  FLEXIO0_IRQHandler         [WEAK]
+                EXPORT  TPM0_IRQHandler         [WEAK]
+                EXPORT  TPM1_IRQHandler         [WEAK]
+                EXPORT  TPM2_IRQHandler         [WEAK]
+                EXPORT  PIT0_IRQHandler         [WEAK]
+                EXPORT  SPI0_IRQHandler         [WEAK]
+                EXPORT  EMVSIM0_IRQHandler         [WEAK]
+                EXPORT  LPUART0_IRQHandler         [WEAK]
+                EXPORT  LPUART1_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  QSPI0_IRQHandler         [WEAK]
+                EXPORT  Reserved32_IRQHandler         [WEAK]
+                EXPORT  PORTA_IRQHandler         [WEAK]
+                EXPORT  PORTB_IRQHandler         [WEAK]
+                EXPORT  PORTC_IRQHandler         [WEAK]
+                EXPORT  PORTD_IRQHandler         [WEAK]
+                EXPORT  PORTE_IRQHandler         [WEAK]
+                EXPORT  LLWU_IRQHandler         [WEAK]
+                EXPORT  LTC0_IRQHandler         [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  LPTMR0_IRQHandler         [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_0_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_1_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_2_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_3_IRQHandler         [WEAK]
+                EXPORT  LPTMR1_IRQHandler         [WEAK]
+                EXPORT  Reserved49_IRQHandler         [WEAK]
+                EXPORT  Reserved50_IRQHandler         [WEAK]
+                EXPORT  Reserved51_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler         [WEAK]
+                EXPORT  LPUART2_IRQHandler         [WEAK]
+                EXPORT  EMVSIM1_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  TSI0_IRQHandler         [WEAK]
+                EXPORT  PMC_IRQHandler         [WEAK]
+                EXPORT  FTFA_IRQHandler         [WEAK]
+                EXPORT  MCG_IRQHandler         [WEAK]
+                EXPORT  WDOG_EWM_IRQHandler         [WEAK]
+                EXPORT  DAC0_IRQHandler         [WEAK]
+                EXPORT  TRNG0_IRQHandler         [WEAK]
+                EXPORT  Reserved63_IRQHandler         [WEAK]
+                EXPORT  CMP0_IRQHandler         [WEAK]
+                EXPORT  Reserved65_IRQHandler         [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler         [WEAK]
+                EXPORT  Reserved67_IRQHandler         [WEAK]
+                EXPORT  Reserved68_IRQHandler         [WEAK]
+                EXPORT  Reserved69_IRQHandler         [WEAK]
+                EXPORT  Reserved70_IRQHandler         [WEAK]
+                EXPORT  Reserved71_IRQHandler         [WEAK]
+                EXPORT  DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA7_IRQHandler         [WEAK]
+                EXPORT  Reserved76_IRQHandler         [WEAK]
+                EXPORT  Reserved77_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  Reserved79_IRQHandler         [WEAK]
+                EXPORT  DefaultISR         [WEAK]
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+                LDR    R0, =DefaultISR
+                BX     R0
+                ENDP
+                  ALIGN
+
+
+                END

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/arm/startup_MKL81Z7_qspi.s

@@ -0,0 +1,463 @@
+; * ---------------------------------------------------------------------------------------
+; *  @file:    startup_MKL82Z7.s
+; *  @purpose: CMSIS Cortex-M0P Core Device Startup File
+; *            MKL82Z7
+; *  @version: 1.4
+; *  @date:    2015-8-28
+; *  @build:   b150910
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler                         ;NMI Handler
+                DCD     HardFault_Handler                   ;Hard Fault Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     SVC_Handler                         ;SVCall Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     PendSV_Handler                      ;PendSV Handler
+                DCD     SysTick_Handler                     ;SysTick Handler
+
+                                                            ;External Interrupts
+                DCD     DMA0_DMA4_IRQHandler                ;DMA channel 0, 4 transfer complete
+                DCD     DMA1_DMA5_IRQHandler                ;DMA channel 1, 5 transfer complete
+                DCD     DMA2_DMA6_IRQHandler                ;DMA channel 2, 6 transfer complete
+                DCD     DMA3_DMA7_IRQHandler                ;DMA channel 3, 7 transfer complete
+                DCD     DMA_Error_IRQHandler                ;DMA channel 0 - 7 error
+                DCD     FLEXIO0_IRQHandler                  ;Flexible IO
+                DCD     TPM0_IRQHandler                     ;Timer/PWM module 0
+                DCD     TPM1_IRQHandler                     ;Timer/PWM module 1
+                DCD     TPM2_IRQHandler                     ;Timer/PWM module 2
+                DCD     PIT0_IRQHandler                     ;Periodic Interrupt Timer 0
+                DCD     SPI0_IRQHandler                     ;Serial Peripheral Interface 0
+                DCD     EMVSIM0_IRQHandler                  ;EMVSIM0 common interrupt
+                DCD     LPUART0_IRQHandler                  ;LPUART0 status and error
+                DCD     LPUART1_IRQHandler                  ;LPUART1 status and error
+                DCD     I2C0_IRQHandler                     ;Inter-Integrated Circuit 0
+                DCD     QSPI0_IRQHandler                    ;QuadSPI0 interrupt
+                DCD     Reserved32_IRQHandler               ;DryIce tamper detect
+                DCD     PORTA_IRQHandler                    ;Pin detect Port A
+                DCD     PORTB_IRQHandler                    ;Pin detect Port B
+                DCD     PORTC_IRQHandler                    ;Pin detect Port C
+                DCD     PORTD_IRQHandler                    ;Pin detect Port D
+                DCD     PORTE_IRQHandler                    ;Pin detect Port E
+                DCD     LLWU_IRQHandler                     ;Low Leakage Wakeup
+                DCD     LTC0_IRQHandler                     ;Low power trusted cryptographic
+                DCD     USB0_IRQHandler                     ;USB OTG interrupt
+                DCD     ADC0_IRQHandler                     ;Analog-to-Digital Converter 0
+                DCD     LPTMR0_IRQHandler                   ;Low-Power Timer 0
+                DCD     RTC_Seconds_IRQHandler              ;RTC seconds
+                DCD     INTMUX0_0_IRQHandler                ;Selectable peripheral interrupt INTMUX0-0
+                DCD     INTMUX0_1_IRQHandler                ;Selectable peripheral interrupt INTMUX0-1
+                DCD     INTMUX0_2_IRQHandler                ;Selectable peripheral interrupt INTMUX0-2
+                DCD     INTMUX0_3_IRQHandler                ;Selectable peripheral interrupt INTMUX0-3
+                DCD     LPTMR1_IRQHandler                   ;Low-Power Timer 1 (INTMUX source IRQ0)
+                DCD     Reserved49_IRQHandler               ;Reserved interrupt (INTMUX source IRQ1)
+                DCD     Reserved50_IRQHandler               ;Reserved interrupt (INTMUX source IRQ2)
+                DCD     Reserved51_IRQHandler               ;Reserved interrupt (INTMUX source IRQ3)
+                DCD     SPI1_IRQHandler                     ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+                DCD     LPUART2_IRQHandler                  ;LPUART2 status and error (INTMUX source IRQ5)
+                DCD     EMVSIM1_IRQHandler                  ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+                DCD     I2C1_IRQHandler                     ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+                DCD     TSI0_IRQHandler                     ;Touch Sensing Input 0 (INTMUX source IRQ8)
+                DCD     PMC_IRQHandler                      ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+                DCD     FTFA_IRQHandler                     ;FTFA command complete/read collision (INTMUX source IRQ10)
+                DCD     MCG_IRQHandler                      ;Multipurpose clock generator (INTMUX source IRQ11)
+                DCD     WDOG_EWM_IRQHandler                 ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+                DCD     DAC0_IRQHandler                     ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+                DCD     TRNG0_IRQHandler                    ;True randon number generator (INTMUX source IRQ14)
+                DCD     Reserved63_IRQHandler               ;Reserved interrupt (INTMUX source IRQ15)
+                DCD     CMP0_IRQHandler                     ;Comparator 0 (INTMUX source IRQ16)
+                DCD     Reserved65_IRQHandler               ;Reserved interrupt (INTMUX source IRQ17)
+                DCD     RTC_Alarm_IRQHandler                ;Real time clock (INTMUX source IRQ18)
+                DCD     Reserved67_IRQHandler               ;Reserved interrupt (INTMUX source IRQ19)
+                DCD     Reserved68_IRQHandler               ;Reserved interrupt (INTMUX source IRQ20)
+                DCD     Reserved69_IRQHandler               ;Reserved interrupt (INTMUX source IRQ21)
+                DCD     Reserved70_IRQHandler               ;Reserved interrupt (INTMUX source IRQ22)
+                DCD     Reserved71_IRQHandler               ;Reserved interrupt (INTMUX source IRQ23)
+                DCD     DMA4_IRQHandler                     ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+                DCD     DMA5_IRQHandler                     ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+                DCD     DMA6_IRQHandler                     ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+                DCD     DMA7_IRQHandler                     ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+                DCD     Reserved76_IRQHandler               ;Reserved interrupt (INTMUX source IRQ28)
+                DCD     Reserved77_IRQHandler               ;Reserved interrupt (INTMUX source IRQ29)
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt (INTMUX source IRQ30)
+                DCD     Reserved79_IRQHandler               ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict access to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>
+;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>
+;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>
+;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>
+;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>
+;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>
+;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>
+;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program Flash Region Protect Register 0
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0> LPBOOT
+;       <0=> Low-power boot
+;       <1=> Normal boot
+;     <o.1> BOOTPIN_OPT
+;       <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+;       <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+;     <o.2> NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI_b pin/interrupts reset default to enabled
+;     <o.5> FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+;     <o.6..7> BOOTSRC_SEL
+;       <0=> Boot from Flash
+;       <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
+;       <3=> Boot from ROM and enter boot loader mode.
+;         <i> Boot source selection
+FOPT          EQU     0xBD
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor Key Security Enable
+FSEC          EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    FlashConfig, DATA, READONLY
+__FlashConfig
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3
+                DCB     FSEC      , FOPT      , 0xFF      , 0xFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  init_data_bss
+                IMPORT  __main
+
+                IF      :LNOT::DEF:RAM_TARGET
+                REQUIRE FlashConfig
+                ENDIF
+
+                CPSID   I               ; Mask interrupts
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =init_data_bss
+                BLX     R0
+                CPSIE   i               ; Unmask interrupts
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler         [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler         [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler         [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+Default_Handler\
+                PROC
+                EXPORT  DMA0_DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA1_DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA2_DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA3_DMA7_IRQHandler         [WEAK]
+                EXPORT  DMA_Error_IRQHandler         [WEAK]
+                EXPORT  FLEXIO0_IRQHandler         [WEAK]
+                EXPORT  TPM0_IRQHandler         [WEAK]
+                EXPORT  TPM1_IRQHandler         [WEAK]
+                EXPORT  TPM2_IRQHandler         [WEAK]
+                EXPORT  PIT0_IRQHandler         [WEAK]
+                EXPORT  SPI0_IRQHandler         [WEAK]
+                EXPORT  EMVSIM0_IRQHandler         [WEAK]
+                EXPORT  LPUART0_IRQHandler         [WEAK]
+                EXPORT  LPUART1_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  QSPI0_IRQHandler         [WEAK]
+                EXPORT  Reserved32_IRQHandler         [WEAK]
+                EXPORT  PORTA_IRQHandler         [WEAK]
+                EXPORT  PORTB_IRQHandler         [WEAK]
+                EXPORT  PORTC_IRQHandler         [WEAK]
+                EXPORT  PORTD_IRQHandler         [WEAK]
+                EXPORT  PORTE_IRQHandler         [WEAK]
+                EXPORT  LLWU_IRQHandler         [WEAK]
+                EXPORT  LTC0_IRQHandler         [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  LPTMR0_IRQHandler         [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_0_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_1_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_2_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_3_IRQHandler         [WEAK]
+                EXPORT  LPTMR1_IRQHandler         [WEAK]
+                EXPORT  Reserved49_IRQHandler         [WEAK]
+                EXPORT  Reserved50_IRQHandler         [WEAK]
+                EXPORT  Reserved51_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler         [WEAK]
+                EXPORT  LPUART2_IRQHandler         [WEAK]
+                EXPORT  EMVSIM1_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  TSI0_IRQHandler         [WEAK]
+                EXPORT  PMC_IRQHandler         [WEAK]
+                EXPORT  FTFA_IRQHandler         [WEAK]
+                EXPORT  MCG_IRQHandler         [WEAK]
+                EXPORT  WDOG_EWM_IRQHandler         [WEAK]
+                EXPORT  DAC0_IRQHandler         [WEAK]
+                EXPORT  TRNG0_IRQHandler         [WEAK]
+                EXPORT  Reserved63_IRQHandler         [WEAK]
+                EXPORT  CMP0_IRQHandler         [WEAK]
+                EXPORT  Reserved65_IRQHandler         [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler         [WEAK]
+                EXPORT  Reserved67_IRQHandler         [WEAK]
+                EXPORT  Reserved68_IRQHandler         [WEAK]
+                EXPORT  Reserved69_IRQHandler         [WEAK]
+                EXPORT  Reserved70_IRQHandler         [WEAK]
+                EXPORT  Reserved71_IRQHandler         [WEAK]
+                EXPORT  DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA7_IRQHandler         [WEAK]
+                EXPORT  Reserved76_IRQHandler         [WEAK]
+                EXPORT  Reserved77_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  Reserved79_IRQHandler         [WEAK]
+                EXPORT  DefaultISR         [WEAK]
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+                LDR    R0, =DefaultISR
+                BX     R0
+                ENDP
+                  ALIGN
+
+
+                END

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/arm/startup_MKL81Z7_qspi_patch.s

@@ -0,0 +1,467 @@
+; * ---------------------------------------------------------------------------------------
+; *  @file:    startup_MKL82Z7.s
+; *  @purpose: CMSIS Cortex-M0P Core Device Startup File
+; *            MKL82Z7
+; *  @version: 1.4
+; *  @date:    2015-8-28
+; *  @build:   b150910
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler                         ;NMI Handler
+                DCD     HardFault_Handler                   ;Hard Fault Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     SVC_Handler                         ;SVCall Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     PendSV_Handler                      ;PendSV Handler
+                DCD     SysTick_Handler                     ;SysTick Handler
+
+                                                            ;External Interrupts
+                DCD     DMA0_DMA4_IRQHandler                ;DMA channel 0, 4 transfer complete
+                DCD     DMA1_DMA5_IRQHandler                ;DMA channel 1, 5 transfer complete
+                DCD     DMA2_DMA6_IRQHandler                ;DMA channel 2, 6 transfer complete
+                DCD     DMA3_DMA7_IRQHandler                ;DMA channel 3, 7 transfer complete
+                DCD     DMA_Error_IRQHandler                ;DMA channel 0 - 7 error
+                DCD     FLEXIO0_IRQHandler                  ;Flexible IO
+                DCD     TPM0_IRQHandler                     ;Timer/PWM module 0
+                DCD     TPM1_IRQHandler                     ;Timer/PWM module 1
+                DCD     TPM2_IRQHandler                     ;Timer/PWM module 2
+                DCD     PIT0_IRQHandler                     ;Periodic Interrupt Timer 0
+                DCD     SPI0_IRQHandler                     ;Serial Peripheral Interface 0
+                DCD     EMVSIM0_IRQHandler                  ;EMVSIM0 common interrupt
+                DCD     LPUART0_IRQHandler                  ;LPUART0 status and error
+                DCD     LPUART1_IRQHandler                  ;LPUART1 status and error
+                DCD     I2C0_IRQHandler                     ;Inter-Integrated Circuit 0
+                DCD     QSPI0_IRQHandler                    ;QuadSPI0 interrupt
+                DCD     Reserved32_IRQHandler               ;DryIce tamper detect
+                DCD     PORTA_IRQHandler                    ;Pin detect Port A
+                DCD     PORTB_IRQHandler                    ;Pin detect Port B
+                DCD     PORTC_IRQHandler                    ;Pin detect Port C
+                DCD     PORTD_IRQHandler                    ;Pin detect Port D
+                DCD     PORTE_IRQHandler                    ;Pin detect Port E
+                DCD     LLWU_IRQHandler                     ;Low Leakage Wakeup
+                DCD     LTC0_IRQHandler                     ;Low power trusted cryptographic
+                DCD     USB0_IRQHandler                     ;USB OTG interrupt
+                DCD     ADC0_IRQHandler                     ;Analog-to-Digital Converter 0
+                DCD     LPTMR0_IRQHandler                   ;Low-Power Timer 0
+                DCD     RTC_Seconds_IRQHandler              ;RTC seconds
+                DCD     INTMUX0_0_IRQHandler                ;Selectable peripheral interrupt INTMUX0-0
+                DCD     INTMUX0_1_IRQHandler                ;Selectable peripheral interrupt INTMUX0-1
+                DCD     INTMUX0_2_IRQHandler                ;Selectable peripheral interrupt INTMUX0-2
+                DCD     INTMUX0_3_IRQHandler                ;Selectable peripheral interrupt INTMUX0-3
+                DCD     LPTMR1_IRQHandler                   ;Low-Power Timer 1 (INTMUX source IRQ0)
+                DCD     Reserved49_IRQHandler               ;Reserved interrupt (INTMUX source IRQ1)
+                DCD     Reserved50_IRQHandler               ;Reserved interrupt (INTMUX source IRQ2)
+                DCD     Reserved51_IRQHandler               ;Reserved interrupt (INTMUX source IRQ3)
+                DCD     SPI1_IRQHandler                     ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+                DCD     LPUART2_IRQHandler                  ;LPUART2 status and error (INTMUX source IRQ5)
+                DCD     EMVSIM1_IRQHandler                  ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+                DCD     I2C1_IRQHandler                     ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+                DCD     TSI0_IRQHandler                     ;Touch Sensing Input 0 (INTMUX source IRQ8)
+                DCD     PMC_IRQHandler                      ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+                DCD     FTFA_IRQHandler                     ;FTFA command complete/read collision (INTMUX source IRQ10)
+                DCD     MCG_IRQHandler                      ;Multipurpose clock generator (INTMUX source IRQ11)
+                DCD     WDOG_EWM_IRQHandler                 ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+                DCD     DAC0_IRQHandler                     ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+                DCD     TRNG0_IRQHandler                    ;True randon number generator (INTMUX source IRQ14)
+                DCD     Reserved63_IRQHandler               ;Reserved interrupt (INTMUX source IRQ15)
+                DCD     CMP0_IRQHandler                     ;Comparator 0 (INTMUX source IRQ16)
+                DCD     Reserved65_IRQHandler               ;Reserved interrupt (INTMUX source IRQ17)
+                DCD     RTC_Alarm_IRQHandler                ;Real time clock (INTMUX source IRQ18)
+                DCD     Reserved67_IRQHandler               ;Reserved interrupt (INTMUX source IRQ19)
+                DCD     Reserved68_IRQHandler               ;Reserved interrupt (INTMUX source IRQ20)
+                DCD     Reserved69_IRQHandler               ;Reserved interrupt (INTMUX source IRQ21)
+                DCD     Reserved70_IRQHandler               ;Reserved interrupt (INTMUX source IRQ22)
+                DCD     Reserved71_IRQHandler               ;Reserved interrupt (INTMUX source IRQ23)
+                DCD     DMA4_IRQHandler                     ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+                DCD     DMA5_IRQHandler                     ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+                DCD     DMA6_IRQHandler                     ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+                DCD     DMA7_IRQHandler                     ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+                DCD     Reserved76_IRQHandler               ;Reserved interrupt (INTMUX source IRQ28)
+                DCD     Reserved77_IRQHandler               ;Reserved interrupt (INTMUX source IRQ29)
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt (INTMUX source IRQ30)
+                DCD     Reserved79_IRQHandler               ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict access to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>
+;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>
+;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>
+;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>
+;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>
+;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>
+;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>
+;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program Flash Region Protect Register 0
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0> LPBOOT
+;       <0=> Low-power boot
+;       <1=> Normal boot
+;     <o.1> BOOTPIN_OPT
+;       <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+;       <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+;     <o.2> NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI_b pin/interrupts reset default to enabled
+;     <o.5> FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+;     <o.6..7> BOOTSRC_SEL
+;       <0=> Boot from Flash
+;       <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
+;       <3=> Boot from ROM and enter boot loader mode.
+;         <i> Boot source selection
+FOPT          EQU     0xBD
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor Key Security Enable
+FSEC          EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    FlashConfig, DATA, READONLY
+__FlashConfig
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3
+                DCB     FSEC      , FOPT      , 0xFF      , 0xFF
+                ENDIF
+
+
+                
+; Reset Handler
+        AREA    BootloaderPatchHandler, CODE, READONLY
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  init_data_bss
+                IMPORT  ROM_PatchHandler
+                IMPORT  __main
+
+                IF      :LNOT::DEF:RAM_TARGET
+                LDR R0, =FlashConfig    ; dummy read, workaround for flashConfig
+                ENDIF
+
+                CPSID   I               ; Mask interrupts
+                LDR     R0, =ROM_PatchHandler
+                BLX     R0
+                NOP
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =init_data_bss
+                BLX     R0
+                CPSIE   i               ; Unmask interrupts
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+        AREA    |.text|, CODE, READONLY
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler         [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler         [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler         [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+Default_Handler\
+                PROC
+                EXPORT  DMA0_DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA1_DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA2_DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA3_DMA7_IRQHandler         [WEAK]
+                EXPORT  DMA_Error_IRQHandler         [WEAK]
+                EXPORT  FLEXIO0_IRQHandler         [WEAK]
+                EXPORT  TPM0_IRQHandler         [WEAK]
+                EXPORT  TPM1_IRQHandler         [WEAK]
+                EXPORT  TPM2_IRQHandler         [WEAK]
+                EXPORT  PIT0_IRQHandler         [WEAK]
+                EXPORT  SPI0_IRQHandler         [WEAK]
+                EXPORT  EMVSIM0_IRQHandler         [WEAK]
+                EXPORT  LPUART0_IRQHandler         [WEAK]
+                EXPORT  LPUART1_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  QSPI0_IRQHandler         [WEAK]
+                EXPORT  Reserved32_IRQHandler         [WEAK]
+                EXPORT  PORTA_IRQHandler         [WEAK]
+                EXPORT  PORTB_IRQHandler         [WEAK]
+                EXPORT  PORTC_IRQHandler         [WEAK]
+                EXPORT  PORTD_IRQHandler         [WEAK]
+                EXPORT  PORTE_IRQHandler         [WEAK]
+                EXPORT  LLWU_IRQHandler         [WEAK]
+                EXPORT  LTC0_IRQHandler         [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  LPTMR0_IRQHandler         [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_0_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_1_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_2_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_3_IRQHandler         [WEAK]
+                EXPORT  LPTMR1_IRQHandler         [WEAK]
+                EXPORT  Reserved49_IRQHandler         [WEAK]
+                EXPORT  Reserved50_IRQHandler         [WEAK]
+                EXPORT  Reserved51_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler         [WEAK]
+                EXPORT  LPUART2_IRQHandler         [WEAK]
+                EXPORT  EMVSIM1_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  TSI0_IRQHandler         [WEAK]
+                EXPORT  PMC_IRQHandler         [WEAK]
+                EXPORT  FTFA_IRQHandler         [WEAK]
+                EXPORT  MCG_IRQHandler         [WEAK]
+                EXPORT  WDOG_EWM_IRQHandler         [WEAK]
+                EXPORT  DAC0_IRQHandler         [WEAK]
+                EXPORT  TRNG0_IRQHandler         [WEAK]
+                EXPORT  Reserved63_IRQHandler         [WEAK]
+                EXPORT  CMP0_IRQHandler         [WEAK]
+                EXPORT  Reserved65_IRQHandler         [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler         [WEAK]
+                EXPORT  Reserved67_IRQHandler         [WEAK]
+                EXPORT  Reserved68_IRQHandler         [WEAK]
+                EXPORT  Reserved69_IRQHandler         [WEAK]
+                EXPORT  Reserved70_IRQHandler         [WEAK]
+                EXPORT  Reserved71_IRQHandler         [WEAK]
+                EXPORT  DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA7_IRQHandler         [WEAK]
+                EXPORT  Reserved76_IRQHandler         [WEAK]
+                EXPORT  Reserved77_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  Reserved79_IRQHandler         [WEAK]
+                EXPORT  DefaultISR         [WEAK]
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+                LDR    R0, =DefaultISR
+                BX     R0
+                ENDP
+                  ALIGN
+
+
+                END

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/gcc/startup_MKL81Z7.S

@@ -0,0 +1,256 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL82Z7.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL82Z7                                                                     */
+/*  @version: 1.4                                                                         */
+/*  @date:    2015-8-28                                                                   */
+/*  @build:   b150910                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA4_IRQHandler                            /* DMA channel 0, 4 transfer complete*/
+    .long   DMA1_DMA5_IRQHandler                            /* DMA channel 1, 5 transfer complete*/
+    .long   DMA2_DMA6_IRQHandler                            /* DMA channel 2, 6 transfer complete*/
+    .long   DMA3_DMA7_IRQHandler                            /* DMA channel 3, 7 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 7 error*/
+    .long   FLEXIO0_IRQHandler                              /* Flexible IO*/
+    .long   TPM0_IRQHandler                                 /* Timer/PWM module 0*/
+    .long   TPM1_IRQHandler                                 /* Timer/PWM module 1*/
+    .long   TPM2_IRQHandler                                 /* Timer/PWM module 2*/
+    .long   PIT0_IRQHandler                                 /* Periodic Interrupt Timer 0*/
+    .long   SPI0_IRQHandler                                 /* Serial Peripheral Interface 0*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   I2C0_IRQHandler                                 /* Inter-Integrated Circuit 0*/
+    .long   QSPI0_IRQHandler                                /* QuadSPI0 interrupt*/
+    .long   Reserved32_IRQHandler                           /* DryIce tamper detect*/
+    .long   PORTA_IRQHandler                                /* Pin detect Port A*/
+    .long   PORTB_IRQHandler                                /* Pin detect Port B*/
+    .long   PORTC_IRQHandler                                /* Pin detect Port C*/
+    .long   PORTD_IRQHandler                                /* Pin detect Port D*/
+    .long   PORTE_IRQHandler                                /* Pin detect Port E*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup*/
+    .long   LTC0_IRQHandler                                 /* Low power trusted cryptographic*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-Digital Converter 0*/
+    .long   LPTMR0_IRQHandler                               /* Low-Power Timer 0*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   INTMUX0_0_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-0*/
+    .long   INTMUX0_1_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-1*/
+    .long   INTMUX0_2_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-2*/
+    .long   INTMUX0_3_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-3*/
+    .long   LPTMR1_IRQHandler                               /* Low-Power Timer 1 (INTMUX source IRQ0)*/
+    .long   Reserved49_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ1)*/
+    .long   Reserved50_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ2)*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ3)*/
+    .long   SPI1_IRQHandler                                 /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 status and error (INTMUX source IRQ5)*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
+    .long   I2C1_IRQHandler                                 /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
+    .long   PMC_IRQHandler                                  /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete/read collision (INTMUX source IRQ10)*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator (INTMUX source IRQ11)*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator (INTMUX source IRQ14)*/
+    .long   Reserved63_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ15)*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0 (INTMUX source IRQ16)*/
+    .long   Reserved65_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ17)*/
+    .long   RTC_Alarm_IRQHandler                            /* Real time clock (INTMUX source IRQ18)*/
+    .long   Reserved67_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ19)*/
+    .long   Reserved68_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ20)*/
+    .long   Reserved69_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ21)*/
+    .long   Reserved70_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ22)*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ23)*/
+    .long   DMA4_IRQHandler                                 /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
+    .long   DMA5_IRQHandler                                 /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
+    .long   DMA6_IRQHandler                                 /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
+    .long   DMA7_IRQHandler                                 /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
+    .long   Reserved76_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ28)*/
+    .long   Reserved77_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ29)*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ30)*/
+    .long   Reserved79_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ31)*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3DFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr	r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA4_IRQHandler
+    def_irq_handler    DMA1_DMA5_IRQHandler
+    def_irq_handler    DMA2_DMA6_IRQHandler
+    def_irq_handler    DMA3_DMA7_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    QSPI0_IRQHandler
+    def_irq_handler    Reserved32_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    INTMUX0_0_IRQHandler
+    def_irq_handler    INTMUX0_1_IRQHandler
+    def_irq_handler    INTMUX0_2_IRQHandler
+    def_irq_handler    INTMUX0_3_IRQHandler
+    def_irq_handler    LPTMR1_IRQHandler
+    def_irq_handler    Reserved49_IRQHandler
+    def_irq_handler    Reserved50_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    Reserved63_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    Reserved65_IRQHandler
+    def_irq_handler    RTC_Alarm_IRQHandler
+    def_irq_handler    Reserved67_IRQHandler
+    def_irq_handler    Reserved68_IRQHandler
+    def_irq_handler    Reserved69_IRQHandler
+    def_irq_handler    Reserved70_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    Reserved76_IRQHandler
+    def_irq_handler    Reserved77_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    Reserved79_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/gcc/startup_MKL81Z7_qspi.S

@@ -0,0 +1,256 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL82Z7.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL82Z7                                                                     */
+/*  @version: 1.4                                                                         */
+/*  @date:    2015-8-28                                                                   */
+/*  @build:   b150910                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA4_IRQHandler                            /* DMA channel 0, 4 transfer complete*/
+    .long   DMA1_DMA5_IRQHandler                            /* DMA channel 1, 5 transfer complete*/
+    .long   DMA2_DMA6_IRQHandler                            /* DMA channel 2, 6 transfer complete*/
+    .long   DMA3_DMA7_IRQHandler                            /* DMA channel 3, 7 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 7 error*/
+    .long   FLEXIO0_IRQHandler                              /* Flexible IO*/
+    .long   TPM0_IRQHandler                                 /* Timer/PWM module 0*/
+    .long   TPM1_IRQHandler                                 /* Timer/PWM module 1*/
+    .long   TPM2_IRQHandler                                 /* Timer/PWM module 2*/
+    .long   PIT0_IRQHandler                                 /* Periodic Interrupt Timer 0*/
+    .long   SPI0_IRQHandler                                 /* Serial Peripheral Interface 0*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   I2C0_IRQHandler                                 /* Inter-Integrated Circuit 0*/
+    .long   QSPI0_IRQHandler                                /* QuadSPI0 interrupt*/
+    .long   Reserved32_IRQHandler                           /* DryIce tamper detect*/
+    .long   PORTA_IRQHandler                                /* Pin detect Port A*/
+    .long   PORTB_IRQHandler                                /* Pin detect Port B*/
+    .long   PORTC_IRQHandler                                /* Pin detect Port C*/
+    .long   PORTD_IRQHandler                                /* Pin detect Port D*/
+    .long   PORTE_IRQHandler                                /* Pin detect Port E*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup*/
+    .long   LTC0_IRQHandler                                 /* Low power trusted cryptographic*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-Digital Converter 0*/
+    .long   LPTMR0_IRQHandler                               /* Low-Power Timer 0*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   INTMUX0_0_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-0*/
+    .long   INTMUX0_1_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-1*/
+    .long   INTMUX0_2_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-2*/
+    .long   INTMUX0_3_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-3*/
+    .long   LPTMR1_IRQHandler                               /* Low-Power Timer 1 (INTMUX source IRQ0)*/
+    .long   Reserved49_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ1)*/
+    .long   Reserved50_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ2)*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ3)*/
+    .long   SPI1_IRQHandler                                 /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 status and error (INTMUX source IRQ5)*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
+    .long   I2C1_IRQHandler                                 /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
+    .long   PMC_IRQHandler                                  /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete/read collision (INTMUX source IRQ10)*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator (INTMUX source IRQ11)*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator (INTMUX source IRQ14)*/
+    .long   Reserved63_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ15)*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0 (INTMUX source IRQ16)*/
+    .long   Reserved65_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ17)*/
+    .long   RTC_Alarm_IRQHandler                            /* Real time clock (INTMUX source IRQ18)*/
+    .long   Reserved67_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ19)*/
+    .long   Reserved68_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ20)*/
+    .long   Reserved69_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ21)*/
+    .long   Reserved70_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ22)*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ23)*/
+    .long   DMA4_IRQHandler                                 /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
+    .long   DMA5_IRQHandler                                 /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
+    .long   DMA6_IRQHandler                                 /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
+    .long   DMA7_IRQHandler                                 /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
+    .long   Reserved76_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ28)*/
+    .long   Reserved77_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ29)*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ30)*/
+    .long   Reserved79_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ31)*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr	r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA4_IRQHandler
+    def_irq_handler    DMA1_DMA5_IRQHandler
+    def_irq_handler    DMA2_DMA6_IRQHandler
+    def_irq_handler    DMA3_DMA7_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    QSPI0_IRQHandler
+    def_irq_handler    Reserved32_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    INTMUX0_0_IRQHandler
+    def_irq_handler    INTMUX0_1_IRQHandler
+    def_irq_handler    INTMUX0_2_IRQHandler
+    def_irq_handler    INTMUX0_3_IRQHandler
+    def_irq_handler    LPTMR1_IRQHandler
+    def_irq_handler    Reserved49_IRQHandler
+    def_irq_handler    Reserved50_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    Reserved63_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    Reserved65_IRQHandler
+    def_irq_handler    RTC_Alarm_IRQHandler
+    def_irq_handler    Reserved67_IRQHandler
+    def_irq_handler    Reserved68_IRQHandler
+    def_irq_handler    Reserved69_IRQHandler
+    def_irq_handler    Reserved70_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    Reserved76_IRQHandler
+    def_irq_handler    Reserved77_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    Reserved79_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/gcc/startup_MKL81Z7_qspi_patch.S

@@ -0,0 +1,266 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL82Z7.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL82Z7                                                                     */
+/*  @version: 1.4                                                                         */
+/*  @date:    2015-8-28                                                                   */
+/*  @build:   b150910                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA4_IRQHandler                            /* DMA channel 0, 4 transfer complete*/
+    .long   DMA1_DMA5_IRQHandler                            /* DMA channel 1, 5 transfer complete*/
+    .long   DMA2_DMA6_IRQHandler                            /* DMA channel 2, 6 transfer complete*/
+    .long   DMA3_DMA7_IRQHandler                            /* DMA channel 3, 7 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 7 error*/
+    .long   FLEXIO0_IRQHandler                              /* Flexible IO*/
+    .long   TPM0_IRQHandler                                 /* Timer/PWM module 0*/
+    .long   TPM1_IRQHandler                                 /* Timer/PWM module 1*/
+    .long   TPM2_IRQHandler                                 /* Timer/PWM module 2*/
+    .long   PIT0_IRQHandler                                 /* Periodic Interrupt Timer 0*/
+    .long   SPI0_IRQHandler                                 /* Serial Peripheral Interface 0*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   I2C0_IRQHandler                                 /* Inter-Integrated Circuit 0*/
+    .long   QSPI0_IRQHandler                                /* QuadSPI0 interrupt*/
+    .long   Reserved32_IRQHandler                           /* DryIce tamper detect*/
+    .long   PORTA_IRQHandler                                /* Pin detect Port A*/
+    .long   PORTB_IRQHandler                                /* Pin detect Port B*/
+    .long   PORTC_IRQHandler                                /* Pin detect Port C*/
+    .long   PORTD_IRQHandler                                /* Pin detect Port D*/
+    .long   PORTE_IRQHandler                                /* Pin detect Port E*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup*/
+    .long   LTC0_IRQHandler                                 /* Low power trusted cryptographic*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-Digital Converter 0*/
+    .long   LPTMR0_IRQHandler                               /* Low-Power Timer 0*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   INTMUX0_0_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-0*/
+    .long   INTMUX0_1_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-1*/
+    .long   INTMUX0_2_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-2*/
+    .long   INTMUX0_3_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-3*/
+    .long   LPTMR1_IRQHandler                               /* Low-Power Timer 1 (INTMUX source IRQ0)*/
+    .long   Reserved49_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ1)*/
+    .long   Reserved50_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ2)*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ3)*/
+    .long   SPI1_IRQHandler                                 /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 status and error (INTMUX source IRQ5)*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
+    .long   I2C1_IRQHandler                                 /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
+    .long   PMC_IRQHandler                                  /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete/read collision (INTMUX source IRQ10)*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator (INTMUX source IRQ11)*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator (INTMUX source IRQ14)*/
+    .long   Reserved63_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ15)*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0 (INTMUX source IRQ16)*/
+    .long   Reserved65_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ17)*/
+    .long   RTC_Alarm_IRQHandler                            /* Real time clock (INTMUX source IRQ18)*/
+    .long   Reserved67_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ19)*/
+    .long   Reserved68_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ20)*/
+    .long   Reserved69_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ21)*/
+    .long   Reserved70_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ22)*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ23)*/
+    .long   DMA4_IRQHandler                                 /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
+    .long   DMA5_IRQHandler                                 /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
+    .long   DMA6_IRQHandler                                 /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
+    .long   DMA7_IRQHandler                                 /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
+    .long   Reserved76_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ28)*/
+    .long   Reserved77_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ29)*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ30)*/
+    .long   Reserved79_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ31)*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .section BootloaderPatchHandler, "a"
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    ldr r0, = ROM_PatchHandler
+    blx r0
+#ifndef __NO_SYSTEM_INIT
+    ldr r0, = SystemInit
+    blx r0
+#endif
+    ldr r0, = init_data_bss
+    blx r0
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr r0, = __START
+    blx r0
+#else
+    ldr r0,=    __libc_init_array
+    blx r0
+    ldr r0, = main,
+    bx r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .text
+    .thumb
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr	r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA4_IRQHandler
+    def_irq_handler    DMA1_DMA5_IRQHandler
+    def_irq_handler    DMA2_DMA6_IRQHandler
+    def_irq_handler    DMA3_DMA7_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    QSPI0_IRQHandler
+    def_irq_handler    Reserved32_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    INTMUX0_0_IRQHandler
+    def_irq_handler    INTMUX0_1_IRQHandler
+    def_irq_handler    INTMUX0_2_IRQHandler
+    def_irq_handler    INTMUX0_3_IRQHandler
+    def_irq_handler    LPTMR1_IRQHandler
+    def_irq_handler    Reserved49_IRQHandler
+    def_irq_handler    Reserved50_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    Reserved63_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    Reserved65_IRQHandler
+    def_irq_handler    RTC_Alarm_IRQHandler
+    def_irq_handler    Reserved67_IRQHandler
+    def_irq_handler    Reserved68_IRQHandler
+    def_irq_handler    Reserved69_IRQHandler
+    def_irq_handler    Reserved70_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    Reserved76_IRQHandler
+    def_irq_handler    Reserved77_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    Reserved79_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/iar/startup_MKL81Z7.s

@@ -0,0 +1,347 @@
+; ---------------------------------------------------------------------------------------
+;  @file:    startup_MKL82Z7.s
+;  @purpose: CMSIS Cortex-M0P Core Device Startup File
+;            MKL82Z7
+;  @version: 1.4
+;  @date:    2015-8-28
+;  @build:   b150910
+; ---------------------------------------------------------------------------------------
+;
+; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN  init_data_bss
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     DMA0_DMA4_IRQHandler                          ;DMA channel 0, 4 transfer complete
+        DCD     DMA1_DMA5_IRQHandler                          ;DMA channel 1, 5 transfer complete
+        DCD     DMA2_DMA6_IRQHandler                          ;DMA channel 2, 6 transfer complete
+        DCD     DMA3_DMA7_IRQHandler                          ;DMA channel 3, 7 transfer complete
+        DCD     DMA_Error_IRQHandler                          ;DMA channel 0 - 7 error
+        DCD     FLEXIO0_IRQHandler                            ;Flexible IO
+        DCD     TPM0_IRQHandler                               ;Timer/PWM module 0
+        DCD     TPM1_IRQHandler                               ;Timer/PWM module 1
+        DCD     TPM2_IRQHandler                               ;Timer/PWM module 2
+        DCD     PIT0_IRQHandler                               ;Periodic Interrupt Timer 0
+        DCD     SPI0_IRQHandler                               ;Serial Peripheral Interface 0
+        DCD     EMVSIM0_IRQHandler                            ;EMVSIM0 common interrupt
+        DCD     LPUART0_IRQHandler                            ;LPUART0 status and error
+        DCD     LPUART1_IRQHandler                            ;LPUART1 status and error
+        DCD     I2C0_IRQHandler                               ;Inter-Integrated Circuit 0
+        DCD     QSPI0_IRQHandler                              ;QuadSPI0 interrupt
+        DCD     Reserved32_IRQHandler                         ;DryIce tamper detect
+        DCD     PORTA_IRQHandler                              ;Pin detect Port A
+        DCD     PORTB_IRQHandler                              ;Pin detect Port B
+        DCD     PORTC_IRQHandler                              ;Pin detect Port C
+        DCD     PORTD_IRQHandler                              ;Pin detect Port D
+        DCD     PORTE_IRQHandler                              ;Pin detect Port E
+        DCD     LLWU_IRQHandler                               ;Low Leakage Wakeup
+        DCD     LTC0_IRQHandler                               ;Low power trusted cryptographic
+        DCD     USB0_IRQHandler                               ;USB OTG interrupt
+        DCD     ADC0_IRQHandler                               ;Analog-to-Digital Converter 0
+        DCD     LPTMR0_IRQHandler                             ;Low-Power Timer 0
+        DCD     RTC_Seconds_IRQHandler                        ;RTC seconds
+        DCD     INTMUX0_0_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-0
+        DCD     INTMUX0_1_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-1
+        DCD     INTMUX0_2_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-2
+        DCD     INTMUX0_3_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-3
+        DCD     LPTMR1_IRQHandler                             ;Low-Power Timer 1 (INTMUX source IRQ0)
+        DCD     Reserved49_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ1)
+        DCD     Reserved50_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ2)
+        DCD     Reserved51_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ3)
+        DCD     SPI1_IRQHandler                               ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+        DCD     LPUART2_IRQHandler                            ;LPUART2 status and error (INTMUX source IRQ5)
+        DCD     EMVSIM1_IRQHandler                            ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+        DCD     I2C1_IRQHandler                               ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+        DCD     TSI0_IRQHandler                               ;Touch Sensing Input 0 (INTMUX source IRQ8)
+        DCD     PMC_IRQHandler                                ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+        DCD     FTFA_IRQHandler                               ;FTFA command complete/read collision (INTMUX source IRQ10)
+        DCD     MCG_IRQHandler                                ;Multipurpose clock generator (INTMUX source IRQ11)
+        DCD     WDOG_EWM_IRQHandler                           ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+        DCD     DAC0_IRQHandler                               ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+        DCD     TRNG0_IRQHandler                              ;True randon number generator (INTMUX source IRQ14)
+        DCD     Reserved63_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ15)
+        DCD     CMP0_IRQHandler                               ;Comparator 0 (INTMUX source IRQ16)
+        DCD     Reserved65_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ17)
+        DCD     RTC_Alarm_IRQHandler                          ;Real time clock (INTMUX source IRQ18)
+        DCD     Reserved67_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ19)
+        DCD     Reserved68_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ20)
+        DCD     Reserved69_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ21)
+        DCD     Reserved70_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ22)
+        DCD     Reserved71_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ23)
+        DCD     DMA4_IRQHandler                               ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+        DCD     DMA5_IRQHandler                               ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+        DCD     DMA6_IRQHandler                               ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+        DCD     DMA7_IRQHandler                               ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+        DCD     Reserved76_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ28)
+        DCD     Reserved77_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ29)
+        DCD     Reserved78_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ30)
+        DCD     Reserved79_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+        SECTION FlashConfig:CODE
+__FlashConfig
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFF3DFE
+__FlashConfig_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        CPSID   I               ; Mask interrupts
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =init_data_bss
+        BLX     R0
+        CPSIE   I               ; Unmask interrupts
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK DMA0_DMA4_IRQHandler
+        PUBWEAK DMA1_DMA5_IRQHandler
+        PUBWEAK DMA2_DMA6_IRQHandler
+        PUBWEAK DMA3_DMA7_IRQHandler
+        PUBWEAK DMA_Error_IRQHandler
+        PUBWEAK FLEXIO0_IRQHandler
+        PUBWEAK TPM0_IRQHandler
+        PUBWEAK TPM1_IRQHandler
+        PUBWEAK TPM2_IRQHandler
+        PUBWEAK PIT0_IRQHandler
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK EMVSIM0_IRQHandler
+        PUBWEAK LPUART0_IRQHandler
+        PUBWEAK LPUART1_IRQHandler
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK QSPI0_IRQHandler
+        PUBWEAK Reserved32_IRQHandler
+        PUBWEAK PORTA_IRQHandler
+        PUBWEAK PORTB_IRQHandler
+        PUBWEAK PORTC_IRQHandler
+        PUBWEAK PORTD_IRQHandler
+        PUBWEAK PORTE_IRQHandler
+        PUBWEAK LLWU_IRQHandler
+        PUBWEAK LTC0_IRQHandler
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK ADC0_IRQHandler
+        PUBWEAK LPTMR0_IRQHandler
+        PUBWEAK RTC_Seconds_IRQHandler
+        PUBWEAK INTMUX0_0_IRQHandler
+        PUBWEAK INTMUX0_1_IRQHandler
+        PUBWEAK INTMUX0_2_IRQHandler
+        PUBWEAK INTMUX0_3_IRQHandler
+        PUBWEAK LPTMR1_IRQHandler
+        PUBWEAK Reserved49_IRQHandler
+        PUBWEAK Reserved50_IRQHandler
+        PUBWEAK Reserved51_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK LPUART2_IRQHandler
+        PUBWEAK EMVSIM1_IRQHandler
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK TSI0_IRQHandler
+        PUBWEAK PMC_IRQHandler
+        PUBWEAK FTFA_IRQHandler
+        PUBWEAK MCG_IRQHandler
+        PUBWEAK WDOG_EWM_IRQHandler
+        PUBWEAK DAC0_IRQHandler
+        PUBWEAK TRNG0_IRQHandler
+        PUBWEAK Reserved63_IRQHandler
+        PUBWEAK CMP0_IRQHandler
+        PUBWEAK Reserved65_IRQHandler
+        PUBWEAK RTC_Alarm_IRQHandler
+        PUBWEAK Reserved67_IRQHandler
+        PUBWEAK Reserved68_IRQHandler
+        PUBWEAK Reserved69_IRQHandler
+        PUBWEAK Reserved70_IRQHandler
+        PUBWEAK Reserved71_IRQHandler
+        PUBWEAK DMA4_IRQHandler
+        PUBWEAK DMA5_IRQHandler
+        PUBWEAK DMA6_IRQHandler
+        PUBWEAK DMA7_IRQHandler
+        PUBWEAK Reserved76_IRQHandler
+        PUBWEAK Reserved77_IRQHandler
+        PUBWEAK Reserved78_IRQHandler
+        PUBWEAK Reserved79_IRQHandler
+        PUBWEAK DefaultISR
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+        LDR R0, =DefaultISR
+        BX R0
+
+        END

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/iar/startup_MKL81Z7_qspi.s

@@ -0,0 +1,347 @@
+; ---------------------------------------------------------------------------------------
+;  @file:    startup_MKL82Z7.s
+;  @purpose: CMSIS Cortex-M0P Core Device Startup File
+;            MKL82Z7
+;  @version: 1.4
+;  @date:    2015-8-28
+;  @build:   b150910
+; ---------------------------------------------------------------------------------------
+;
+; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN  init_data_bss
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     DMA0_DMA4_IRQHandler                          ;DMA channel 0, 4 transfer complete
+        DCD     DMA1_DMA5_IRQHandler                          ;DMA channel 1, 5 transfer complete
+        DCD     DMA2_DMA6_IRQHandler                          ;DMA channel 2, 6 transfer complete
+        DCD     DMA3_DMA7_IRQHandler                          ;DMA channel 3, 7 transfer complete
+        DCD     DMA_Error_IRQHandler                          ;DMA channel 0 - 7 error
+        DCD     FLEXIO0_IRQHandler                            ;Flexible IO
+        DCD     TPM0_IRQHandler                               ;Timer/PWM module 0
+        DCD     TPM1_IRQHandler                               ;Timer/PWM module 1
+        DCD     TPM2_IRQHandler                               ;Timer/PWM module 2
+        DCD     PIT0_IRQHandler                               ;Periodic Interrupt Timer 0
+        DCD     SPI0_IRQHandler                               ;Serial Peripheral Interface 0
+        DCD     EMVSIM0_IRQHandler                            ;EMVSIM0 common interrupt
+        DCD     LPUART0_IRQHandler                            ;LPUART0 status and error
+        DCD     LPUART1_IRQHandler                            ;LPUART1 status and error
+        DCD     I2C0_IRQHandler                               ;Inter-Integrated Circuit 0
+        DCD     QSPI0_IRQHandler                              ;QuadSPI0 interrupt
+        DCD     Reserved32_IRQHandler                         ;DryIce tamper detect
+        DCD     PORTA_IRQHandler                              ;Pin detect Port A
+        DCD     PORTB_IRQHandler                              ;Pin detect Port B
+        DCD     PORTC_IRQHandler                              ;Pin detect Port C
+        DCD     PORTD_IRQHandler                              ;Pin detect Port D
+        DCD     PORTE_IRQHandler                              ;Pin detect Port E
+        DCD     LLWU_IRQHandler                               ;Low Leakage Wakeup
+        DCD     LTC0_IRQHandler                               ;Low power trusted cryptographic
+        DCD     USB0_IRQHandler                               ;USB OTG interrupt
+        DCD     ADC0_IRQHandler                               ;Analog-to-Digital Converter 0
+        DCD     LPTMR0_IRQHandler                             ;Low-Power Timer 0
+        DCD     RTC_Seconds_IRQHandler                        ;RTC seconds
+        DCD     INTMUX0_0_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-0
+        DCD     INTMUX0_1_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-1
+        DCD     INTMUX0_2_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-2
+        DCD     INTMUX0_3_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-3
+        DCD     LPTMR1_IRQHandler                             ;Low-Power Timer 1 (INTMUX source IRQ0)
+        DCD     Reserved49_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ1)
+        DCD     Reserved50_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ2)
+        DCD     Reserved51_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ3)
+        DCD     SPI1_IRQHandler                               ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+        DCD     LPUART2_IRQHandler                            ;LPUART2 status and error (INTMUX source IRQ5)
+        DCD     EMVSIM1_IRQHandler                            ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+        DCD     I2C1_IRQHandler                               ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+        DCD     TSI0_IRQHandler                               ;Touch Sensing Input 0 (INTMUX source IRQ8)
+        DCD     PMC_IRQHandler                                ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+        DCD     FTFA_IRQHandler                               ;FTFA command complete/read collision (INTMUX source IRQ10)
+        DCD     MCG_IRQHandler                                ;Multipurpose clock generator (INTMUX source IRQ11)
+        DCD     WDOG_EWM_IRQHandler                           ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+        DCD     DAC0_IRQHandler                               ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+        DCD     TRNG0_IRQHandler                              ;True randon number generator (INTMUX source IRQ14)
+        DCD     Reserved63_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ15)
+        DCD     CMP0_IRQHandler                               ;Comparator 0 (INTMUX source IRQ16)
+        DCD     Reserved65_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ17)
+        DCD     RTC_Alarm_IRQHandler                          ;Real time clock (INTMUX source IRQ18)
+        DCD     Reserved67_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ19)
+        DCD     Reserved68_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ20)
+        DCD     Reserved69_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ21)
+        DCD     Reserved70_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ22)
+        DCD     Reserved71_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ23)
+        DCD     DMA4_IRQHandler                               ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+        DCD     DMA5_IRQHandler                               ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+        DCD     DMA6_IRQHandler                               ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+        DCD     DMA7_IRQHandler                               ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+        DCD     Reserved76_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ28)
+        DCD     Reserved77_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ29)
+        DCD     Reserved78_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ30)
+        DCD     Reserved79_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+        SECTION FlashConfig:CODE
+__FlashConfig
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFBDFE
+__FlashConfig_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        CPSID   I               ; Mask interrupts
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =init_data_bss
+        BLX     R0
+        CPSIE   I               ; Unmask interrupts
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK DMA0_DMA4_IRQHandler
+        PUBWEAK DMA1_DMA5_IRQHandler
+        PUBWEAK DMA2_DMA6_IRQHandler
+        PUBWEAK DMA3_DMA7_IRQHandler
+        PUBWEAK DMA_Error_IRQHandler
+        PUBWEAK FLEXIO0_IRQHandler
+        PUBWEAK TPM0_IRQHandler
+        PUBWEAK TPM1_IRQHandler
+        PUBWEAK TPM2_IRQHandler
+        PUBWEAK PIT0_IRQHandler
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK EMVSIM0_IRQHandler
+        PUBWEAK LPUART0_IRQHandler
+        PUBWEAK LPUART1_IRQHandler
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK QSPI0_IRQHandler
+        PUBWEAK Reserved32_IRQHandler
+        PUBWEAK PORTA_IRQHandler
+        PUBWEAK PORTB_IRQHandler
+        PUBWEAK PORTC_IRQHandler
+        PUBWEAK PORTD_IRQHandler
+        PUBWEAK PORTE_IRQHandler
+        PUBWEAK LLWU_IRQHandler
+        PUBWEAK LTC0_IRQHandler
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK ADC0_IRQHandler
+        PUBWEAK LPTMR0_IRQHandler
+        PUBWEAK RTC_Seconds_IRQHandler
+        PUBWEAK INTMUX0_0_IRQHandler
+        PUBWEAK INTMUX0_1_IRQHandler
+        PUBWEAK INTMUX0_2_IRQHandler
+        PUBWEAK INTMUX0_3_IRQHandler
+        PUBWEAK LPTMR1_IRQHandler
+        PUBWEAK Reserved49_IRQHandler
+        PUBWEAK Reserved50_IRQHandler
+        PUBWEAK Reserved51_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK LPUART2_IRQHandler
+        PUBWEAK EMVSIM1_IRQHandler
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK TSI0_IRQHandler
+        PUBWEAK PMC_IRQHandler
+        PUBWEAK FTFA_IRQHandler
+        PUBWEAK MCG_IRQHandler
+        PUBWEAK WDOG_EWM_IRQHandler
+        PUBWEAK DAC0_IRQHandler
+        PUBWEAK TRNG0_IRQHandler
+        PUBWEAK Reserved63_IRQHandler
+        PUBWEAK CMP0_IRQHandler
+        PUBWEAK Reserved65_IRQHandler
+        PUBWEAK RTC_Alarm_IRQHandler
+        PUBWEAK Reserved67_IRQHandler
+        PUBWEAK Reserved68_IRQHandler
+        PUBWEAK Reserved69_IRQHandler
+        PUBWEAK Reserved70_IRQHandler
+        PUBWEAK Reserved71_IRQHandler
+        PUBWEAK DMA4_IRQHandler
+        PUBWEAK DMA5_IRQHandler
+        PUBWEAK DMA6_IRQHandler
+        PUBWEAK DMA7_IRQHandler
+        PUBWEAK Reserved76_IRQHandler
+        PUBWEAK Reserved77_IRQHandler
+        PUBWEAK Reserved78_IRQHandler
+        PUBWEAK Reserved79_IRQHandler
+        PUBWEAK DefaultISR
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+        LDR R0, =DefaultISR
+        BX R0
+
+        END

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/iar/startup_MKL81Z7_qspi_patch.s

@@ -0,0 +1,350 @@
+; ---------------------------------------------------------------------------------------
+;  @file:    startup_MKL82Z7.s
+;  @purpose: CMSIS Cortex-M0P Core Device Startup File
+;            MKL82Z7
+;  @version: 1.4
+;  @date:    2015-8-28
+;  @build:   b150910
+; ---------------------------------------------------------------------------------------
+;
+; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN  ROM_PatchHandler
+        EXTERN  init_data_bss
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     DMA0_DMA4_IRQHandler                          ;DMA channel 0, 4 transfer complete
+        DCD     DMA1_DMA5_IRQHandler                          ;DMA channel 1, 5 transfer complete
+        DCD     DMA2_DMA6_IRQHandler                          ;DMA channel 2, 6 transfer complete
+        DCD     DMA3_DMA7_IRQHandler                          ;DMA channel 3, 7 transfer complete
+        DCD     DMA_Error_IRQHandler                          ;DMA channel 0 - 7 error
+        DCD     FLEXIO0_IRQHandler                            ;Flexible IO
+        DCD     TPM0_IRQHandler                               ;Timer/PWM module 0
+        DCD     TPM1_IRQHandler                               ;Timer/PWM module 1
+        DCD     TPM2_IRQHandler                               ;Timer/PWM module 2
+        DCD     PIT0_IRQHandler                               ;Periodic Interrupt Timer 0
+        DCD     SPI0_IRQHandler                               ;Serial Peripheral Interface 0
+        DCD     EMVSIM0_IRQHandler                            ;EMVSIM0 common interrupt
+        DCD     LPUART0_IRQHandler                            ;LPUART0 status and error
+        DCD     LPUART1_IRQHandler                            ;LPUART1 status and error
+        DCD     I2C0_IRQHandler                               ;Inter-Integrated Circuit 0
+        DCD     QSPI0_IRQHandler                              ;QuadSPI0 interrupt
+        DCD     Reserved32_IRQHandler                         ;DryIce tamper detect
+        DCD     PORTA_IRQHandler                              ;Pin detect Port A
+        DCD     PORTB_IRQHandler                              ;Pin detect Port B
+        DCD     PORTC_IRQHandler                              ;Pin detect Port C
+        DCD     PORTD_IRQHandler                              ;Pin detect Port D
+        DCD     PORTE_IRQHandler                              ;Pin detect Port E
+        DCD     LLWU_IRQHandler                               ;Low Leakage Wakeup
+        DCD     LTC0_IRQHandler                               ;Low power trusted cryptographic
+        DCD     USB0_IRQHandler                               ;USB OTG interrupt
+        DCD     ADC0_IRQHandler                               ;Analog-to-Digital Converter 0
+        DCD     LPTMR0_IRQHandler                             ;Low-Power Timer 0
+        DCD     RTC_Seconds_IRQHandler                        ;RTC seconds
+        DCD     INTMUX0_0_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-0
+        DCD     INTMUX0_1_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-1
+        DCD     INTMUX0_2_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-2
+        DCD     INTMUX0_3_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-3
+        DCD     LPTMR1_IRQHandler                             ;Low-Power Timer 1 (INTMUX source IRQ0)
+        DCD     Reserved49_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ1)
+        DCD     Reserved50_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ2)
+        DCD     Reserved51_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ3)
+        DCD     SPI1_IRQHandler                               ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+        DCD     LPUART2_IRQHandler                            ;LPUART2 status and error (INTMUX source IRQ5)
+        DCD     EMVSIM1_IRQHandler                            ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+        DCD     I2C1_IRQHandler                               ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+        DCD     TSI0_IRQHandler                               ;Touch Sensing Input 0 (INTMUX source IRQ8)
+        DCD     PMC_IRQHandler                                ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+        DCD     FTFA_IRQHandler                               ;FTFA command complete/read collision (INTMUX source IRQ10)
+        DCD     MCG_IRQHandler                                ;Multipurpose clock generator (INTMUX source IRQ11)
+        DCD     WDOG_EWM_IRQHandler                           ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+        DCD     DAC0_IRQHandler                               ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+        DCD     TRNG0_IRQHandler                              ;True randon number generator (INTMUX source IRQ14)
+        DCD     Reserved63_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ15)
+        DCD     CMP0_IRQHandler                               ;Comparator 0 (INTMUX source IRQ16)
+        DCD     Reserved65_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ17)
+        DCD     RTC_Alarm_IRQHandler                          ;Real time clock (INTMUX source IRQ18)
+        DCD     Reserved67_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ19)
+        DCD     Reserved68_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ20)
+        DCD     Reserved69_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ21)
+        DCD     Reserved70_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ22)
+        DCD     Reserved71_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ23)
+        DCD     DMA4_IRQHandler                               ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+        DCD     DMA5_IRQHandler                               ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+        DCD     DMA6_IRQHandler                               ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+        DCD     DMA7_IRQHandler                               ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+        DCD     Reserved76_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ28)
+        DCD     Reserved77_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ29)
+        DCD     Reserved78_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ30)
+        DCD     Reserved79_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+        SECTION FlashConfig:CODE
+__FlashConfig
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFBDFE
+__FlashConfig_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION BootloaderPatchHandler:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        CPSID   I               ; Mask interrupts
+        LDR     R0, =ROM_PatchHandler
+        BLX     R0
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =init_data_bss
+        BLX     R0
+        CPSIE   I               ; Unmask interrupts
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK DMA0_DMA4_IRQHandler
+        PUBWEAK DMA1_DMA5_IRQHandler
+        PUBWEAK DMA2_DMA6_IRQHandler
+        PUBWEAK DMA3_DMA7_IRQHandler
+        PUBWEAK DMA_Error_IRQHandler
+        PUBWEAK FLEXIO0_IRQHandler
+        PUBWEAK TPM0_IRQHandler
+        PUBWEAK TPM1_IRQHandler
+        PUBWEAK TPM2_IRQHandler
+        PUBWEAK PIT0_IRQHandler
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK EMVSIM0_IRQHandler
+        PUBWEAK LPUART0_IRQHandler
+        PUBWEAK LPUART1_IRQHandler
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK QSPI0_IRQHandler
+        PUBWEAK Reserved32_IRQHandler
+        PUBWEAK PORTA_IRQHandler
+        PUBWEAK PORTB_IRQHandler
+        PUBWEAK PORTC_IRQHandler
+        PUBWEAK PORTD_IRQHandler
+        PUBWEAK PORTE_IRQHandler
+        PUBWEAK LLWU_IRQHandler
+        PUBWEAK LTC0_IRQHandler
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK ADC0_IRQHandler
+        PUBWEAK LPTMR0_IRQHandler
+        PUBWEAK RTC_Seconds_IRQHandler
+        PUBWEAK INTMUX0_0_IRQHandler
+        PUBWEAK INTMUX0_1_IRQHandler
+        PUBWEAK INTMUX0_2_IRQHandler
+        PUBWEAK INTMUX0_3_IRQHandler
+        PUBWEAK LPTMR1_IRQHandler
+        PUBWEAK Reserved49_IRQHandler
+        PUBWEAK Reserved50_IRQHandler
+        PUBWEAK Reserved51_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK LPUART2_IRQHandler
+        PUBWEAK EMVSIM1_IRQHandler
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK TSI0_IRQHandler
+        PUBWEAK PMC_IRQHandler
+        PUBWEAK FTFA_IRQHandler
+        PUBWEAK MCG_IRQHandler
+        PUBWEAK WDOG_EWM_IRQHandler
+        PUBWEAK DAC0_IRQHandler
+        PUBWEAK TRNG0_IRQHandler
+        PUBWEAK Reserved63_IRQHandler
+        PUBWEAK CMP0_IRQHandler
+        PUBWEAK Reserved65_IRQHandler
+        PUBWEAK RTC_Alarm_IRQHandler
+        PUBWEAK Reserved67_IRQHandler
+        PUBWEAK Reserved68_IRQHandler
+        PUBWEAK Reserved69_IRQHandler
+        PUBWEAK Reserved70_IRQHandler
+        PUBWEAK Reserved71_IRQHandler
+        PUBWEAK DMA4_IRQHandler
+        PUBWEAK DMA5_IRQHandler
+        PUBWEAK DMA6_IRQHandler
+        PUBWEAK DMA7_IRQHandler
+        PUBWEAK Reserved76_IRQHandler
+        PUBWEAK Reserved77_IRQHandler
+        PUBWEAK Reserved78_IRQHandler
+        PUBWEAK Reserved79_IRQHandler
+        PUBWEAK DefaultISR
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+        LDR R0, =DefaultISR
+        BX R0
+
+        END

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/system_MKL81Z7.h

@@ -0,0 +1,390 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.0.3 June 2015
+**     Version:             rev. 1.4, 2015-08-28
+**     Build:               b150910
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7
+ * @version 1.4
+ * @date 2015-08-28
+ * @brief Device specific configuration file for MKL82Z7 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL82Z7_H_
+#define SYSTEM_MKL82Z7_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef DISABLE_WDOG
+#define DISABLE_WDOG 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximal speed configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 96MHz
+         Bus clock  = 24MHz
+   2 ... Chip internally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 96MHz
+         Bus clock  = 24MHz
+   5 ... Maximum achievable clock frequency configuration in RUN mode
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 72MHz
+         Bus clock  = 24MHz
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ \
+    12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ                                                                       \
+    32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
+              */
+#define CPU_INT_SLOW_CLK_HZ 32768U   /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */      /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */      /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
+#define MCG_MODE MCG_MODE_FEI          /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1,OUTDIV5=1 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00011000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+                                           /* SIM_SOPT2:
+                                            * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+                                            */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 1)
+#define DEFAULT_SYSTEM_CLOCK 96000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 2)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPI    /* Clock generator mode */
+/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=4,OUTDIV5=0 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x03040000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 3)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPE    /* Clock generator mode */
+/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0x0B */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 4)
+#define DEFAULT_SYSTEM_CLOCK 96000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=3,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x03U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 5)
+#define DEFAULT_SYSTEM_CLOCK 72000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
+#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=8 */
+#define SYSTEM_MCG_C6_VALUE 0x48U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=2,OUTDIV4=2,OUTDIV5=0 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x02020000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#endif
+#else
+#define DEFAULT_SYSTEM_CLOCK 20971520u
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL82Z7_H_) */

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/system_MKL81Z7_qspi.c

@@ -0,0 +1,309 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.0.3 June 2015
+**     Version:             rev. 1.4, 2015-08-28
+**     Build:               b150910
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7
+ * @version 1.4
+ * @date 2015-08-28
+ * @brief Device specific configuration file for MKL82Z7 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t RESERVED2[2];
+    uint8_t RESERVED3[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED4[12];
+} system_bootloader_config_t;
+
+#ifndef BOOTLOADER_CONFIG
+#define BOOTLOADER_CONFIG 1 /* Enable BootloaderConfig Area by default */
+#endif
+
+#if (BOOTLOADER_CONFIG)
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0xFFFFU, /* Use default timeout */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 72000000ul;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+    uint16_t Divider;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
+    {
+        /* Output of FLL or PLL is selected */
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
+        {
+            /* FLL is selected */
+            if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
+            {
+                /* External reference clock is selected */
+                switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+                {
+                    case 0x00U:
+                        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                        break;
+                    case 0x01U:
+                        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                        break;
+                    case 0x02U:
+                    default:
+                        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                        break;
+                }
+                if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
+                {
+                    switch (MCG->C1 & MCG_C1_FRDIV_MASK)
+                    {
+                        case 0x38U:
+                            Divider = 1536U;
+                            break;
+                        case 0x30U:
+                            Divider = 1280U;
+                            break;
+                        default:
+                            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                            break;
+                    }
+                }
+                else
+                { /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+                    Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                }
+                MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+            }
+            else
+            {                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+                MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+            }                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+            /* Select correct multiplier to calculate the MCG output clock  */
+            switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
+            {
+                case 0x00U:
+                    MCGOUTClock *= 640U;
+                    break;
+                case 0x20U:
+                    MCGOUTClock *= 1280U;
+                    break;
+                case 0x40U:
+                    MCGOUTClock *= 1920U;
+                    break;
+                case 0x60U:
+                    MCGOUTClock *= 2560U;
+                    break;
+                case 0x80U:
+                    MCGOUTClock *= 732U;
+                    break;
+                case 0xA0U:
+                    MCGOUTClock *= 1464U;
+                    break;
+                case 0xC0U:
+                    MCGOUTClock *= 2197U;
+                    break;
+                case 0xE0U:
+                    MCGOUTClock *= 2929U;
+                    break;
+                default:
+                    break;
+            }
+        }
+        else
+        { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+            /* PLL is selected */
+            Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+            MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+            Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+            MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+            MCGOUTClock /= 2;       /* Calculate the MCG output clock */
+        }                           /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
+    {
+        /* Internal reference clock is selected */
+        if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
+        {
+            MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+        }
+        else
+        { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+            Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+            MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+        }                                                            /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
+    {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+        {
+            case 0x00U:
+                MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                break;
+            case 0x01U:
+                MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                break;
+            case 0x02U:
+            default:
+                MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                break;
+        }
+    }
+    else
+    { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+        /* Reserved value */
+        return;
+    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    SystemCoreClock =
+        (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

apps/demo_qspi/led_demo/devices/MKL81Z7/startup/system_MKL81Z7_qspi_patch.c

@@ -0,0 +1,230 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.0.3 June 2015
+**     Version:             rev. 1.4, 2015-08-28
+**     Build:               b150910
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7
+ * @version 1.4
+ * @date 2015-08-28
+ * @brief Device specific configuration file for MKL82Z7 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t RESERVED2[2];
+    uint8_t RESERVED3[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED4[12];
+} system_bootloader_config_t;
+
+#ifndef BOOTLOADER_CONFIG
+#define BOOTLOADER_CONFIG 1 /* Enable BootloaderConfig Area by default */
+#endif
+
+#if (BOOTLOADER_CONFIG)
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0xFFFFU, /* Use default timeout */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .qspiConfigBlockPtr = 0x2000,            /* QCB is placed at 0x2000 */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 72000000ul;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the rom patch code on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "rom_patch_code"
+const uint8_t s_rom_patch[124] @"rom_patch_code" =
+#elif defined(__GNUC__)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+
+#elif defined(__CC_ARM)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    { 0x10, 0xB5, 0x01, 0x00, 0x17, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x17, 0x4B, 0x1B, 0x68, 0xDB, 0x00, 0x02, 0xD5,
+      0x16, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x13, 0x68, 0x15, 0x4C, 0x1C, 0x40, 0x14, 0x60, 0x13, 0x68, 0x0C, 0x69,
+      0x24, 0x04, 0x1C, 0x43, 0x14, 0x60, 0x02, 0x68, 0x11, 0x4B, 0x13, 0x40, 0x03, 0x60, 0xDA, 0x22, 0x52, 0x00,
+      0x89, 0x18, 0x02, 0x68, 0x0B, 0x68, 0x1B, 0x04, 0xFC, 0x24, 0xA4, 0x03, 0x1C, 0x40, 0x14, 0x43, 0x04, 0x60,
+      0x02, 0x68, 0x0B, 0x4B, 0x13, 0x40, 0x03, 0x60, 0x02, 0x68, 0x49, 0x68, 0x09, 0x06, 0xFC, 0x23, 0x9B, 0x05,
+      0x0B, 0x40, 0x13, 0x43, 0x03, 0x60, 0x00, 0x20, 0x10, 0xBD, 0x0C, 0xA0, 0x0D, 0x40, 0x24, 0x80, 0x04, 0x40,
+      0x0C, 0xA0, 0x05, 0x40, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0 };
+
+/*
+ *   ROM patch handler for ROM patch code execution.
+ */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the ROM_PatchHandler on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "BootloaderPatchHandler"
+void ROM_PatchHandler(void) @"BootloaderPatchHandler"
+#elif defined(__GNUC__)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#else
+#error Unsupported compiler!
+#endif
+{
+    typedef int (*patch_handler_t)(uint32_t);
+
+#if defined(__IAR_SYSTEMS_ICC__)
+    uint32_t s_rom_patch_start = (uint32_t)__section_begin("rom_patch_code");
+#elif defined(__CC_ARM)
+    extern uint32_t Load$$EXEC_m_rom_patch_code$$Base[];
+    uint32_t s_rom_patch_start = (uint32_t)&Load$$EXEC_m_rom_patch_code$$Base;
+#elif defined(__GNUC__)
+    extern uint32_t rom_patch_code_start[];
+    uint32_t s_rom_patch_start = (uint32_t)&rom_patch_code_start;
+#endif
+
+    uint32_t patch_start = s_rom_patch_start + 1;
+    patch_handler_t patch_run = (patch_handler_t)patch_start;
+    patch_run(BootloaderConfig.qspiConfigBlockPtr);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+void SystemInit(void)
+{
+}

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/arm/startup_MKL82Z7.s

@@ -0,0 +1,463 @@
+; * ---------------------------------------------------------------------------------------
+; *  @file:    startup_MKL82Z7.s
+; *  @purpose: CMSIS Cortex-M0P Core Device Startup File
+; *            MKL82Z7
+; *  @version: 1.4
+; *  @date:    2015-8-28
+; *  @build:   b150910
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler                         ;NMI Handler
+                DCD     HardFault_Handler                   ;Hard Fault Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     SVC_Handler                         ;SVCall Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     PendSV_Handler                      ;PendSV Handler
+                DCD     SysTick_Handler                     ;SysTick Handler
+
+                                                            ;External Interrupts
+                DCD     DMA0_DMA4_IRQHandler                ;DMA channel 0, 4 transfer complete
+                DCD     DMA1_DMA5_IRQHandler                ;DMA channel 1, 5 transfer complete
+                DCD     DMA2_DMA6_IRQHandler                ;DMA channel 2, 6 transfer complete
+                DCD     DMA3_DMA7_IRQHandler                ;DMA channel 3, 7 transfer complete
+                DCD     DMA_Error_IRQHandler                ;DMA channel 0 - 7 error
+                DCD     FLEXIO0_IRQHandler                  ;Flexible IO
+                DCD     TPM0_IRQHandler                     ;Timer/PWM module 0
+                DCD     TPM1_IRQHandler                     ;Timer/PWM module 1
+                DCD     TPM2_IRQHandler                     ;Timer/PWM module 2
+                DCD     PIT0_IRQHandler                     ;Periodic Interrupt Timer 0
+                DCD     SPI0_IRQHandler                     ;Serial Peripheral Interface 0
+                DCD     EMVSIM0_IRQHandler                  ;EMVSIM0 common interrupt
+                DCD     LPUART0_IRQHandler                  ;LPUART0 status and error
+                DCD     LPUART1_IRQHandler                  ;LPUART1 status and error
+                DCD     I2C0_IRQHandler                     ;Inter-Integrated Circuit 0
+                DCD     QSPI0_IRQHandler                    ;QuadSPI0 interrupt
+                DCD     Reserved32_IRQHandler               ;DryIce tamper detect
+                DCD     PORTA_IRQHandler                    ;Pin detect Port A
+                DCD     PORTB_IRQHandler                    ;Pin detect Port B
+                DCD     PORTC_IRQHandler                    ;Pin detect Port C
+                DCD     PORTD_IRQHandler                    ;Pin detect Port D
+                DCD     PORTE_IRQHandler                    ;Pin detect Port E
+                DCD     LLWU_IRQHandler                     ;Low Leakage Wakeup
+                DCD     LTC0_IRQHandler                     ;Low power trusted cryptographic
+                DCD     USB0_IRQHandler                     ;USB OTG interrupt
+                DCD     ADC0_IRQHandler                     ;Analog-to-Digital Converter 0
+                DCD     LPTMR0_IRQHandler                   ;Low-Power Timer 0
+                DCD     RTC_Seconds_IRQHandler              ;RTC seconds
+                DCD     INTMUX0_0_IRQHandler                ;Selectable peripheral interrupt INTMUX0-0
+                DCD     INTMUX0_1_IRQHandler                ;Selectable peripheral interrupt INTMUX0-1
+                DCD     INTMUX0_2_IRQHandler                ;Selectable peripheral interrupt INTMUX0-2
+                DCD     INTMUX0_3_IRQHandler                ;Selectable peripheral interrupt INTMUX0-3
+                DCD     LPTMR1_IRQHandler                   ;Low-Power Timer 1 (INTMUX source IRQ0)
+                DCD     Reserved49_IRQHandler               ;Reserved interrupt (INTMUX source IRQ1)
+                DCD     Reserved50_IRQHandler               ;Reserved interrupt (INTMUX source IRQ2)
+                DCD     Reserved51_IRQHandler               ;Reserved interrupt (INTMUX source IRQ3)
+                DCD     SPI1_IRQHandler                     ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+                DCD     LPUART2_IRQHandler                  ;LPUART2 status and error (INTMUX source IRQ5)
+                DCD     EMVSIM1_IRQHandler                  ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+                DCD     I2C1_IRQHandler                     ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+                DCD     TSI0_IRQHandler                     ;Touch Sensing Input 0 (INTMUX source IRQ8)
+                DCD     PMC_IRQHandler                      ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+                DCD     FTFA_IRQHandler                     ;FTFA command complete/read collision (INTMUX source IRQ10)
+                DCD     MCG_IRQHandler                      ;Multipurpose clock generator (INTMUX source IRQ11)
+                DCD     WDOG_EWM_IRQHandler                 ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+                DCD     DAC0_IRQHandler                     ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+                DCD     TRNG0_IRQHandler                    ;True randon number generator (INTMUX source IRQ14)
+                DCD     Reserved63_IRQHandler               ;Reserved interrupt (INTMUX source IRQ15)
+                DCD     CMP0_IRQHandler                     ;Comparator 0 (INTMUX source IRQ16)
+                DCD     Reserved65_IRQHandler               ;Reserved interrupt (INTMUX source IRQ17)
+                DCD     RTC_Alarm_IRQHandler                ;Real time clock (INTMUX source IRQ18)
+                DCD     Reserved67_IRQHandler               ;Reserved interrupt (INTMUX source IRQ19)
+                DCD     Reserved68_IRQHandler               ;Reserved interrupt (INTMUX source IRQ20)
+                DCD     Reserved69_IRQHandler               ;Reserved interrupt (INTMUX source IRQ21)
+                DCD     Reserved70_IRQHandler               ;Reserved interrupt (INTMUX source IRQ22)
+                DCD     Reserved71_IRQHandler               ;Reserved interrupt (INTMUX source IRQ23)
+                DCD     DMA4_IRQHandler                     ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+                DCD     DMA5_IRQHandler                     ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+                DCD     DMA6_IRQHandler                     ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+                DCD     DMA7_IRQHandler                     ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+                DCD     Reserved76_IRQHandler               ;Reserved interrupt (INTMUX source IRQ28)
+                DCD     Reserved77_IRQHandler               ;Reserved interrupt (INTMUX source IRQ29)
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt (INTMUX source IRQ30)
+                DCD     Reserved79_IRQHandler               ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict access to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>
+;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>
+;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>
+;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>
+;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>
+;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>
+;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>
+;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program Flash Region Protect Register 0
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0> LPBOOT
+;       <0=> Low-power boot
+;       <1=> Normal boot
+;     <o.1> BOOTPIN_OPT
+;       <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+;       <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+;     <o.2> NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI_b pin/interrupts reset default to enabled
+;     <o.5> FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+;     <o.6..7> BOOTSRC_SEL
+;       <0=> Boot from Flash
+;       <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
+;       <3=> Boot from ROM and enter boot loader mode.
+;         <i> Boot source selection
+FOPT          EQU     0x3D
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor Key Security Enable
+FSEC          EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    FlashConfig, DATA, READONLY
+__FlashConfig
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3
+                DCB     FSEC      , FOPT      , 0xFF      , 0xFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  init_data_bss
+                IMPORT  __main
+
+                IF      :LNOT::DEF:RAM_TARGET
+                REQUIRE FlashConfig
+                ENDIF
+
+                CPSID   I               ; Mask interrupts
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =init_data_bss
+                BLX     R0
+                CPSIE   i               ; Unmask interrupts
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler         [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler         [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler         [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+Default_Handler\
+                PROC
+                EXPORT  DMA0_DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA1_DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA2_DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA3_DMA7_IRQHandler         [WEAK]
+                EXPORT  DMA_Error_IRQHandler         [WEAK]
+                EXPORT  FLEXIO0_IRQHandler         [WEAK]
+                EXPORT  TPM0_IRQHandler         [WEAK]
+                EXPORT  TPM1_IRQHandler         [WEAK]
+                EXPORT  TPM2_IRQHandler         [WEAK]
+                EXPORT  PIT0_IRQHandler         [WEAK]
+                EXPORT  SPI0_IRQHandler         [WEAK]
+                EXPORT  EMVSIM0_IRQHandler         [WEAK]
+                EXPORT  LPUART0_IRQHandler         [WEAK]
+                EXPORT  LPUART1_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  QSPI0_IRQHandler         [WEAK]
+                EXPORT  Reserved32_IRQHandler         [WEAK]
+                EXPORT  PORTA_IRQHandler         [WEAK]
+                EXPORT  PORTB_IRQHandler         [WEAK]
+                EXPORT  PORTC_IRQHandler         [WEAK]
+                EXPORT  PORTD_IRQHandler         [WEAK]
+                EXPORT  PORTE_IRQHandler         [WEAK]
+                EXPORT  LLWU_IRQHandler         [WEAK]
+                EXPORT  LTC0_IRQHandler         [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  LPTMR0_IRQHandler         [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_0_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_1_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_2_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_3_IRQHandler         [WEAK]
+                EXPORT  LPTMR1_IRQHandler         [WEAK]
+                EXPORT  Reserved49_IRQHandler         [WEAK]
+                EXPORT  Reserved50_IRQHandler         [WEAK]
+                EXPORT  Reserved51_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler         [WEAK]
+                EXPORT  LPUART2_IRQHandler         [WEAK]
+                EXPORT  EMVSIM1_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  TSI0_IRQHandler         [WEAK]
+                EXPORT  PMC_IRQHandler         [WEAK]
+                EXPORT  FTFA_IRQHandler         [WEAK]
+                EXPORT  MCG_IRQHandler         [WEAK]
+                EXPORT  WDOG_EWM_IRQHandler         [WEAK]
+                EXPORT  DAC0_IRQHandler         [WEAK]
+                EXPORT  TRNG0_IRQHandler         [WEAK]
+                EXPORT  Reserved63_IRQHandler         [WEAK]
+                EXPORT  CMP0_IRQHandler         [WEAK]
+                EXPORT  Reserved65_IRQHandler         [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler         [WEAK]
+                EXPORT  Reserved67_IRQHandler         [WEAK]
+                EXPORT  Reserved68_IRQHandler         [WEAK]
+                EXPORT  Reserved69_IRQHandler         [WEAK]
+                EXPORT  Reserved70_IRQHandler         [WEAK]
+                EXPORT  Reserved71_IRQHandler         [WEAK]
+                EXPORT  DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA7_IRQHandler         [WEAK]
+                EXPORT  Reserved76_IRQHandler         [WEAK]
+                EXPORT  Reserved77_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  Reserved79_IRQHandler         [WEAK]
+                EXPORT  DefaultISR         [WEAK]
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+                LDR    R0, =DefaultISR
+                BX     R0
+                ENDP
+                  ALIGN
+
+
+                END

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/arm/startup_MKL82Z7_qspi.s

@@ -0,0 +1,463 @@
+; * ---------------------------------------------------------------------------------------
+; *  @file:    startup_MKL82Z7.s
+; *  @purpose: CMSIS Cortex-M0P Core Device Startup File
+; *            MKL82Z7
+; *  @version: 1.4
+; *  @date:    2015-8-28
+; *  @build:   b150910
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler                         ;NMI Handler
+                DCD     HardFault_Handler                   ;Hard Fault Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     SVC_Handler                         ;SVCall Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     PendSV_Handler                      ;PendSV Handler
+                DCD     SysTick_Handler                     ;SysTick Handler
+
+                                                            ;External Interrupts
+                DCD     DMA0_DMA4_IRQHandler                ;DMA channel 0, 4 transfer complete
+                DCD     DMA1_DMA5_IRQHandler                ;DMA channel 1, 5 transfer complete
+                DCD     DMA2_DMA6_IRQHandler                ;DMA channel 2, 6 transfer complete
+                DCD     DMA3_DMA7_IRQHandler                ;DMA channel 3, 7 transfer complete
+                DCD     DMA_Error_IRQHandler                ;DMA channel 0 - 7 error
+                DCD     FLEXIO0_IRQHandler                  ;Flexible IO
+                DCD     TPM0_IRQHandler                     ;Timer/PWM module 0
+                DCD     TPM1_IRQHandler                     ;Timer/PWM module 1
+                DCD     TPM2_IRQHandler                     ;Timer/PWM module 2
+                DCD     PIT0_IRQHandler                     ;Periodic Interrupt Timer 0
+                DCD     SPI0_IRQHandler                     ;Serial Peripheral Interface 0
+                DCD     EMVSIM0_IRQHandler                  ;EMVSIM0 common interrupt
+                DCD     LPUART0_IRQHandler                  ;LPUART0 status and error
+                DCD     LPUART1_IRQHandler                  ;LPUART1 status and error
+                DCD     I2C0_IRQHandler                     ;Inter-Integrated Circuit 0
+                DCD     QSPI0_IRQHandler                    ;QuadSPI0 interrupt
+                DCD     Reserved32_IRQHandler               ;DryIce tamper detect
+                DCD     PORTA_IRQHandler                    ;Pin detect Port A
+                DCD     PORTB_IRQHandler                    ;Pin detect Port B
+                DCD     PORTC_IRQHandler                    ;Pin detect Port C
+                DCD     PORTD_IRQHandler                    ;Pin detect Port D
+                DCD     PORTE_IRQHandler                    ;Pin detect Port E
+                DCD     LLWU_IRQHandler                     ;Low Leakage Wakeup
+                DCD     LTC0_IRQHandler                     ;Low power trusted cryptographic
+                DCD     USB0_IRQHandler                     ;USB OTG interrupt
+                DCD     ADC0_IRQHandler                     ;Analog-to-Digital Converter 0
+                DCD     LPTMR0_IRQHandler                   ;Low-Power Timer 0
+                DCD     RTC_Seconds_IRQHandler              ;RTC seconds
+                DCD     INTMUX0_0_IRQHandler                ;Selectable peripheral interrupt INTMUX0-0
+                DCD     INTMUX0_1_IRQHandler                ;Selectable peripheral interrupt INTMUX0-1
+                DCD     INTMUX0_2_IRQHandler                ;Selectable peripheral interrupt INTMUX0-2
+                DCD     INTMUX0_3_IRQHandler                ;Selectable peripheral interrupt INTMUX0-3
+                DCD     LPTMR1_IRQHandler                   ;Low-Power Timer 1 (INTMUX source IRQ0)
+                DCD     Reserved49_IRQHandler               ;Reserved interrupt (INTMUX source IRQ1)
+                DCD     Reserved50_IRQHandler               ;Reserved interrupt (INTMUX source IRQ2)
+                DCD     Reserved51_IRQHandler               ;Reserved interrupt (INTMUX source IRQ3)
+                DCD     SPI1_IRQHandler                     ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+                DCD     LPUART2_IRQHandler                  ;LPUART2 status and error (INTMUX source IRQ5)
+                DCD     EMVSIM1_IRQHandler                  ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+                DCD     I2C1_IRQHandler                     ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+                DCD     TSI0_IRQHandler                     ;Touch Sensing Input 0 (INTMUX source IRQ8)
+                DCD     PMC_IRQHandler                      ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+                DCD     FTFA_IRQHandler                     ;FTFA command complete/read collision (INTMUX source IRQ10)
+                DCD     MCG_IRQHandler                      ;Multipurpose clock generator (INTMUX source IRQ11)
+                DCD     WDOG_EWM_IRQHandler                 ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+                DCD     DAC0_IRQHandler                     ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+                DCD     TRNG0_IRQHandler                    ;True randon number generator (INTMUX source IRQ14)
+                DCD     Reserved63_IRQHandler               ;Reserved interrupt (INTMUX source IRQ15)
+                DCD     CMP0_IRQHandler                     ;Comparator 0 (INTMUX source IRQ16)
+                DCD     Reserved65_IRQHandler               ;Reserved interrupt (INTMUX source IRQ17)
+                DCD     RTC_Alarm_IRQHandler                ;Real time clock (INTMUX source IRQ18)
+                DCD     Reserved67_IRQHandler               ;Reserved interrupt (INTMUX source IRQ19)
+                DCD     Reserved68_IRQHandler               ;Reserved interrupt (INTMUX source IRQ20)
+                DCD     Reserved69_IRQHandler               ;Reserved interrupt (INTMUX source IRQ21)
+                DCD     Reserved70_IRQHandler               ;Reserved interrupt (INTMUX source IRQ22)
+                DCD     Reserved71_IRQHandler               ;Reserved interrupt (INTMUX source IRQ23)
+                DCD     DMA4_IRQHandler                     ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+                DCD     DMA5_IRQHandler                     ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+                DCD     DMA6_IRQHandler                     ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+                DCD     DMA7_IRQHandler                     ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+                DCD     Reserved76_IRQHandler               ;Reserved interrupt (INTMUX source IRQ28)
+                DCD     Reserved77_IRQHandler               ;Reserved interrupt (INTMUX source IRQ29)
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt (INTMUX source IRQ30)
+                DCD     Reserved79_IRQHandler               ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict access to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>
+;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>
+;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>
+;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>
+;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>
+;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>
+;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>
+;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program Flash Region Protect Register 0
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0> LPBOOT
+;       <0=> Low-power boot
+;       <1=> Normal boot
+;     <o.1> BOOTPIN_OPT
+;       <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+;       <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+;     <o.2> NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI_b pin/interrupts reset default to enabled
+;     <o.5> FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+;     <o.6..7> BOOTSRC_SEL
+;       <0=> Boot from Flash
+;       <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
+;       <3=> Boot from ROM and enter boot loader mode.
+;         <i> Boot source selection
+FOPT          EQU     0xBD
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor Key Security Enable
+FSEC          EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    FlashConfig, DATA, READONLY
+__FlashConfig
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3
+                DCB     FSEC      , FOPT      , 0xFF      , 0xFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  init_data_bss
+                IMPORT  __main
+
+                IF      :LNOT::DEF:RAM_TARGET
+                REQUIRE FlashConfig
+                ENDIF
+
+                CPSID   I               ; Mask interrupts
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =init_data_bss
+                BLX     R0
+                CPSIE   i               ; Unmask interrupts
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler         [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler         [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler         [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+Default_Handler\
+                PROC
+                EXPORT  DMA0_DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA1_DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA2_DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA3_DMA7_IRQHandler         [WEAK]
+                EXPORT  DMA_Error_IRQHandler         [WEAK]
+                EXPORT  FLEXIO0_IRQHandler         [WEAK]
+                EXPORT  TPM0_IRQHandler         [WEAK]
+                EXPORT  TPM1_IRQHandler         [WEAK]
+                EXPORT  TPM2_IRQHandler         [WEAK]
+                EXPORT  PIT0_IRQHandler         [WEAK]
+                EXPORT  SPI0_IRQHandler         [WEAK]
+                EXPORT  EMVSIM0_IRQHandler         [WEAK]
+                EXPORT  LPUART0_IRQHandler         [WEAK]
+                EXPORT  LPUART1_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  QSPI0_IRQHandler         [WEAK]
+                EXPORT  Reserved32_IRQHandler         [WEAK]
+                EXPORT  PORTA_IRQHandler         [WEAK]
+                EXPORT  PORTB_IRQHandler         [WEAK]
+                EXPORT  PORTC_IRQHandler         [WEAK]
+                EXPORT  PORTD_IRQHandler         [WEAK]
+                EXPORT  PORTE_IRQHandler         [WEAK]
+                EXPORT  LLWU_IRQHandler         [WEAK]
+                EXPORT  LTC0_IRQHandler         [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  LPTMR0_IRQHandler         [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_0_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_1_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_2_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_3_IRQHandler         [WEAK]
+                EXPORT  LPTMR1_IRQHandler         [WEAK]
+                EXPORT  Reserved49_IRQHandler         [WEAK]
+                EXPORT  Reserved50_IRQHandler         [WEAK]
+                EXPORT  Reserved51_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler         [WEAK]
+                EXPORT  LPUART2_IRQHandler         [WEAK]
+                EXPORT  EMVSIM1_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  TSI0_IRQHandler         [WEAK]
+                EXPORT  PMC_IRQHandler         [WEAK]
+                EXPORT  FTFA_IRQHandler         [WEAK]
+                EXPORT  MCG_IRQHandler         [WEAK]
+                EXPORT  WDOG_EWM_IRQHandler         [WEAK]
+                EXPORT  DAC0_IRQHandler         [WEAK]
+                EXPORT  TRNG0_IRQHandler         [WEAK]
+                EXPORT  Reserved63_IRQHandler         [WEAK]
+                EXPORT  CMP0_IRQHandler         [WEAK]
+                EXPORT  Reserved65_IRQHandler         [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler         [WEAK]
+                EXPORT  Reserved67_IRQHandler         [WEAK]
+                EXPORT  Reserved68_IRQHandler         [WEAK]
+                EXPORT  Reserved69_IRQHandler         [WEAK]
+                EXPORT  Reserved70_IRQHandler         [WEAK]
+                EXPORT  Reserved71_IRQHandler         [WEAK]
+                EXPORT  DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA7_IRQHandler         [WEAK]
+                EXPORT  Reserved76_IRQHandler         [WEAK]
+                EXPORT  Reserved77_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  Reserved79_IRQHandler         [WEAK]
+                EXPORT  DefaultISR         [WEAK]
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+                LDR    R0, =DefaultISR
+                BX     R0
+                ENDP
+                  ALIGN
+
+
+                END

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/arm/startup_MKL82Z7_qspi_patch.s

@@ -0,0 +1,467 @@
+; * ---------------------------------------------------------------------------------------
+; *  @file:    startup_MKL82Z7.s
+; *  @purpose: CMSIS Cortex-M0P Core Device Startup File
+; *            MKL82Z7
+; *  @version: 1.4
+; *  @date:    2015-8-28
+; *  @build:   b150910
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler                         ;NMI Handler
+                DCD     HardFault_Handler                   ;Hard Fault Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     SVC_Handler                         ;SVCall Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     PendSV_Handler                      ;PendSV Handler
+                DCD     SysTick_Handler                     ;SysTick Handler
+
+                                                            ;External Interrupts
+                DCD     DMA0_DMA4_IRQHandler                ;DMA channel 0, 4 transfer complete
+                DCD     DMA1_DMA5_IRQHandler                ;DMA channel 1, 5 transfer complete
+                DCD     DMA2_DMA6_IRQHandler                ;DMA channel 2, 6 transfer complete
+                DCD     DMA3_DMA7_IRQHandler                ;DMA channel 3, 7 transfer complete
+                DCD     DMA_Error_IRQHandler                ;DMA channel 0 - 7 error
+                DCD     FLEXIO0_IRQHandler                  ;Flexible IO
+                DCD     TPM0_IRQHandler                     ;Timer/PWM module 0
+                DCD     TPM1_IRQHandler                     ;Timer/PWM module 1
+                DCD     TPM2_IRQHandler                     ;Timer/PWM module 2
+                DCD     PIT0_IRQHandler                     ;Periodic Interrupt Timer 0
+                DCD     SPI0_IRQHandler                     ;Serial Peripheral Interface 0
+                DCD     EMVSIM0_IRQHandler                  ;EMVSIM0 common interrupt
+                DCD     LPUART0_IRQHandler                  ;LPUART0 status and error
+                DCD     LPUART1_IRQHandler                  ;LPUART1 status and error
+                DCD     I2C0_IRQHandler                     ;Inter-Integrated Circuit 0
+                DCD     QSPI0_IRQHandler                    ;QuadSPI0 interrupt
+                DCD     Reserved32_IRQHandler               ;DryIce tamper detect
+                DCD     PORTA_IRQHandler                    ;Pin detect Port A
+                DCD     PORTB_IRQHandler                    ;Pin detect Port B
+                DCD     PORTC_IRQHandler                    ;Pin detect Port C
+                DCD     PORTD_IRQHandler                    ;Pin detect Port D
+                DCD     PORTE_IRQHandler                    ;Pin detect Port E
+                DCD     LLWU_IRQHandler                     ;Low Leakage Wakeup
+                DCD     LTC0_IRQHandler                     ;Low power trusted cryptographic
+                DCD     USB0_IRQHandler                     ;USB OTG interrupt
+                DCD     ADC0_IRQHandler                     ;Analog-to-Digital Converter 0
+                DCD     LPTMR0_IRQHandler                   ;Low-Power Timer 0
+                DCD     RTC_Seconds_IRQHandler              ;RTC seconds
+                DCD     INTMUX0_0_IRQHandler                ;Selectable peripheral interrupt INTMUX0-0
+                DCD     INTMUX0_1_IRQHandler                ;Selectable peripheral interrupt INTMUX0-1
+                DCD     INTMUX0_2_IRQHandler                ;Selectable peripheral interrupt INTMUX0-2
+                DCD     INTMUX0_3_IRQHandler                ;Selectable peripheral interrupt INTMUX0-3
+                DCD     LPTMR1_IRQHandler                   ;Low-Power Timer 1 (INTMUX source IRQ0)
+                DCD     Reserved49_IRQHandler               ;Reserved interrupt (INTMUX source IRQ1)
+                DCD     Reserved50_IRQHandler               ;Reserved interrupt (INTMUX source IRQ2)
+                DCD     Reserved51_IRQHandler               ;Reserved interrupt (INTMUX source IRQ3)
+                DCD     SPI1_IRQHandler                     ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+                DCD     LPUART2_IRQHandler                  ;LPUART2 status and error (INTMUX source IRQ5)
+                DCD     EMVSIM1_IRQHandler                  ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+                DCD     I2C1_IRQHandler                     ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+                DCD     TSI0_IRQHandler                     ;Touch Sensing Input 0 (INTMUX source IRQ8)
+                DCD     PMC_IRQHandler                      ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+                DCD     FTFA_IRQHandler                     ;FTFA command complete/read collision (INTMUX source IRQ10)
+                DCD     MCG_IRQHandler                      ;Multipurpose clock generator (INTMUX source IRQ11)
+                DCD     WDOG_EWM_IRQHandler                 ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+                DCD     DAC0_IRQHandler                     ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+                DCD     TRNG0_IRQHandler                    ;True randon number generator (INTMUX source IRQ14)
+                DCD     Reserved63_IRQHandler               ;Reserved interrupt (INTMUX source IRQ15)
+                DCD     CMP0_IRQHandler                     ;Comparator 0 (INTMUX source IRQ16)
+                DCD     Reserved65_IRQHandler               ;Reserved interrupt (INTMUX source IRQ17)
+                DCD     RTC_Alarm_IRQHandler                ;Real time clock (INTMUX source IRQ18)
+                DCD     Reserved67_IRQHandler               ;Reserved interrupt (INTMUX source IRQ19)
+                DCD     Reserved68_IRQHandler               ;Reserved interrupt (INTMUX source IRQ20)
+                DCD     Reserved69_IRQHandler               ;Reserved interrupt (INTMUX source IRQ21)
+                DCD     Reserved70_IRQHandler               ;Reserved interrupt (INTMUX source IRQ22)
+                DCD     Reserved71_IRQHandler               ;Reserved interrupt (INTMUX source IRQ23)
+                DCD     DMA4_IRQHandler                     ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+                DCD     DMA5_IRQHandler                     ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+                DCD     DMA6_IRQHandler                     ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+                DCD     DMA7_IRQHandler                     ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+                DCD     Reserved76_IRQHandler               ;Reserved interrupt (INTMUX source IRQ28)
+                DCD     Reserved77_IRQHandler               ;Reserved interrupt (INTMUX source IRQ29)
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt (INTMUX source IRQ30)
+                DCD     Reserved79_IRQHandler               ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict access to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>
+;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>
+;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>
+;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>
+;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>
+;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>
+;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>
+;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program Flash Region Protect Register 0
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0> LPBOOT
+;       <0=> Low-power boot
+;       <1=> Normal boot
+;     <o.1> BOOTPIN_OPT
+;       <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+;       <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+;     <o.2> NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI_b pin/interrupts reset default to enabled
+;     <o.5> FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+;     <o.6..7> BOOTSRC_SEL
+;       <0=> Boot from Flash
+;       <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
+;       <3=> Boot from ROM and enter boot loader mode.
+;         <i> Boot source selection
+FOPT          EQU     0xBD
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor Key Security Enable
+FSEC          EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    FlashConfig, DATA, READONLY
+__FlashConfig
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3
+                DCB     FSEC      , FOPT      , 0xFF      , 0xFF
+                ENDIF
+
+
+                
+; Reset Handler
+        AREA    BootloaderPatchHandler, CODE, READONLY
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  init_data_bss
+                IMPORT  ROM_PatchHandler
+                IMPORT  __main
+
+                IF      :LNOT::DEF:RAM_TARGET
+                LDR R0, =FlashConfig    ; dummy read, workaround for flashConfig
+                ENDIF
+
+                CPSID   I               ; Mask interrupts
+                LDR     R0, =ROM_PatchHandler
+                BLX     R0
+                NOP
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =init_data_bss
+                BLX     R0
+                CPSIE   i               ; Unmask interrupts
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+        AREA    |.text|, CODE, READONLY
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler         [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler         [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler         [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+Default_Handler\
+                PROC
+                EXPORT  DMA0_DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA1_DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA2_DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA3_DMA7_IRQHandler         [WEAK]
+                EXPORT  DMA_Error_IRQHandler         [WEAK]
+                EXPORT  FLEXIO0_IRQHandler         [WEAK]
+                EXPORT  TPM0_IRQHandler         [WEAK]
+                EXPORT  TPM1_IRQHandler         [WEAK]
+                EXPORT  TPM2_IRQHandler         [WEAK]
+                EXPORT  PIT0_IRQHandler         [WEAK]
+                EXPORT  SPI0_IRQHandler         [WEAK]
+                EXPORT  EMVSIM0_IRQHandler         [WEAK]
+                EXPORT  LPUART0_IRQHandler         [WEAK]
+                EXPORT  LPUART1_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  QSPI0_IRQHandler         [WEAK]
+                EXPORT  Reserved32_IRQHandler         [WEAK]
+                EXPORT  PORTA_IRQHandler         [WEAK]
+                EXPORT  PORTB_IRQHandler         [WEAK]
+                EXPORT  PORTC_IRQHandler         [WEAK]
+                EXPORT  PORTD_IRQHandler         [WEAK]
+                EXPORT  PORTE_IRQHandler         [WEAK]
+                EXPORT  LLWU_IRQHandler         [WEAK]
+                EXPORT  LTC0_IRQHandler         [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  LPTMR0_IRQHandler         [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_0_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_1_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_2_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_3_IRQHandler         [WEAK]
+                EXPORT  LPTMR1_IRQHandler         [WEAK]
+                EXPORT  Reserved49_IRQHandler         [WEAK]
+                EXPORT  Reserved50_IRQHandler         [WEAK]
+                EXPORT  Reserved51_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler         [WEAK]
+                EXPORT  LPUART2_IRQHandler         [WEAK]
+                EXPORT  EMVSIM1_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  TSI0_IRQHandler         [WEAK]
+                EXPORT  PMC_IRQHandler         [WEAK]
+                EXPORT  FTFA_IRQHandler         [WEAK]
+                EXPORT  MCG_IRQHandler         [WEAK]
+                EXPORT  WDOG_EWM_IRQHandler         [WEAK]
+                EXPORT  DAC0_IRQHandler         [WEAK]
+                EXPORT  TRNG0_IRQHandler         [WEAK]
+                EXPORT  Reserved63_IRQHandler         [WEAK]
+                EXPORT  CMP0_IRQHandler         [WEAK]
+                EXPORT  Reserved65_IRQHandler         [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler         [WEAK]
+                EXPORT  Reserved67_IRQHandler         [WEAK]
+                EXPORT  Reserved68_IRQHandler         [WEAK]
+                EXPORT  Reserved69_IRQHandler         [WEAK]
+                EXPORT  Reserved70_IRQHandler         [WEAK]
+                EXPORT  Reserved71_IRQHandler         [WEAK]
+                EXPORT  DMA4_IRQHandler         [WEAK]
+                EXPORT  DMA5_IRQHandler         [WEAK]
+                EXPORT  DMA6_IRQHandler         [WEAK]
+                EXPORT  DMA7_IRQHandler         [WEAK]
+                EXPORT  Reserved76_IRQHandler         [WEAK]
+                EXPORT  Reserved77_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  Reserved79_IRQHandler         [WEAK]
+                EXPORT  DefaultISR         [WEAK]
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+                LDR    R0, =DefaultISR
+                BX     R0
+                ENDP
+                  ALIGN
+
+
+                END

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/gcc/startup_MKL82Z7.S

@@ -0,0 +1,256 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL82Z7.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL82Z7                                                                     */
+/*  @version: 1.4                                                                         */
+/*  @date:    2015-8-28                                                                   */
+/*  @build:   b150910                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA4_IRQHandler                            /* DMA channel 0, 4 transfer complete*/
+    .long   DMA1_DMA5_IRQHandler                            /* DMA channel 1, 5 transfer complete*/
+    .long   DMA2_DMA6_IRQHandler                            /* DMA channel 2, 6 transfer complete*/
+    .long   DMA3_DMA7_IRQHandler                            /* DMA channel 3, 7 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 7 error*/
+    .long   FLEXIO0_IRQHandler                              /* Flexible IO*/
+    .long   TPM0_IRQHandler                                 /* Timer/PWM module 0*/
+    .long   TPM1_IRQHandler                                 /* Timer/PWM module 1*/
+    .long   TPM2_IRQHandler                                 /* Timer/PWM module 2*/
+    .long   PIT0_IRQHandler                                 /* Periodic Interrupt Timer 0*/
+    .long   SPI0_IRQHandler                                 /* Serial Peripheral Interface 0*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   I2C0_IRQHandler                                 /* Inter-Integrated Circuit 0*/
+    .long   QSPI0_IRQHandler                                /* QuadSPI0 interrupt*/
+    .long   Reserved32_IRQHandler                           /* DryIce tamper detect*/
+    .long   PORTA_IRQHandler                                /* Pin detect Port A*/
+    .long   PORTB_IRQHandler                                /* Pin detect Port B*/
+    .long   PORTC_IRQHandler                                /* Pin detect Port C*/
+    .long   PORTD_IRQHandler                                /* Pin detect Port D*/
+    .long   PORTE_IRQHandler                                /* Pin detect Port E*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup*/
+    .long   LTC0_IRQHandler                                 /* Low power trusted cryptographic*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-Digital Converter 0*/
+    .long   LPTMR0_IRQHandler                               /* Low-Power Timer 0*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   INTMUX0_0_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-0*/
+    .long   INTMUX0_1_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-1*/
+    .long   INTMUX0_2_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-2*/
+    .long   INTMUX0_3_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-3*/
+    .long   LPTMR1_IRQHandler                               /* Low-Power Timer 1 (INTMUX source IRQ0)*/
+    .long   Reserved49_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ1)*/
+    .long   Reserved50_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ2)*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ3)*/
+    .long   SPI1_IRQHandler                                 /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 status and error (INTMUX source IRQ5)*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
+    .long   I2C1_IRQHandler                                 /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
+    .long   PMC_IRQHandler                                  /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete/read collision (INTMUX source IRQ10)*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator (INTMUX source IRQ11)*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator (INTMUX source IRQ14)*/
+    .long   Reserved63_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ15)*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0 (INTMUX source IRQ16)*/
+    .long   Reserved65_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ17)*/
+    .long   RTC_Alarm_IRQHandler                            /* Real time clock (INTMUX source IRQ18)*/
+    .long   Reserved67_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ19)*/
+    .long   Reserved68_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ20)*/
+    .long   Reserved69_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ21)*/
+    .long   Reserved70_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ22)*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ23)*/
+    .long   DMA4_IRQHandler                                 /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
+    .long   DMA5_IRQHandler                                 /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
+    .long   DMA6_IRQHandler                                 /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
+    .long   DMA7_IRQHandler                                 /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
+    .long   Reserved76_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ28)*/
+    .long   Reserved77_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ29)*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ30)*/
+    .long   Reserved79_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ31)*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3DFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr	r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA4_IRQHandler
+    def_irq_handler    DMA1_DMA5_IRQHandler
+    def_irq_handler    DMA2_DMA6_IRQHandler
+    def_irq_handler    DMA3_DMA7_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    QSPI0_IRQHandler
+    def_irq_handler    Reserved32_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    INTMUX0_0_IRQHandler
+    def_irq_handler    INTMUX0_1_IRQHandler
+    def_irq_handler    INTMUX0_2_IRQHandler
+    def_irq_handler    INTMUX0_3_IRQHandler
+    def_irq_handler    LPTMR1_IRQHandler
+    def_irq_handler    Reserved49_IRQHandler
+    def_irq_handler    Reserved50_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    Reserved63_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    Reserved65_IRQHandler
+    def_irq_handler    RTC_Alarm_IRQHandler
+    def_irq_handler    Reserved67_IRQHandler
+    def_irq_handler    Reserved68_IRQHandler
+    def_irq_handler    Reserved69_IRQHandler
+    def_irq_handler    Reserved70_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    Reserved76_IRQHandler
+    def_irq_handler    Reserved77_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    Reserved79_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/gcc/startup_MKL82Z7_qspi.S

@@ -0,0 +1,256 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL82Z7.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL82Z7                                                                     */
+/*  @version: 1.4                                                                         */
+/*  @date:    2015-8-28                                                                   */
+/*  @build:   b150910                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA4_IRQHandler                            /* DMA channel 0, 4 transfer complete*/
+    .long   DMA1_DMA5_IRQHandler                            /* DMA channel 1, 5 transfer complete*/
+    .long   DMA2_DMA6_IRQHandler                            /* DMA channel 2, 6 transfer complete*/
+    .long   DMA3_DMA7_IRQHandler                            /* DMA channel 3, 7 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 7 error*/
+    .long   FLEXIO0_IRQHandler                              /* Flexible IO*/
+    .long   TPM0_IRQHandler                                 /* Timer/PWM module 0*/
+    .long   TPM1_IRQHandler                                 /* Timer/PWM module 1*/
+    .long   TPM2_IRQHandler                                 /* Timer/PWM module 2*/
+    .long   PIT0_IRQHandler                                 /* Periodic Interrupt Timer 0*/
+    .long   SPI0_IRQHandler                                 /* Serial Peripheral Interface 0*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   I2C0_IRQHandler                                 /* Inter-Integrated Circuit 0*/
+    .long   QSPI0_IRQHandler                                /* QuadSPI0 interrupt*/
+    .long   Reserved32_IRQHandler                           /* DryIce tamper detect*/
+    .long   PORTA_IRQHandler                                /* Pin detect Port A*/
+    .long   PORTB_IRQHandler                                /* Pin detect Port B*/
+    .long   PORTC_IRQHandler                                /* Pin detect Port C*/
+    .long   PORTD_IRQHandler                                /* Pin detect Port D*/
+    .long   PORTE_IRQHandler                                /* Pin detect Port E*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup*/
+    .long   LTC0_IRQHandler                                 /* Low power trusted cryptographic*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-Digital Converter 0*/
+    .long   LPTMR0_IRQHandler                               /* Low-Power Timer 0*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   INTMUX0_0_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-0*/
+    .long   INTMUX0_1_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-1*/
+    .long   INTMUX0_2_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-2*/
+    .long   INTMUX0_3_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-3*/
+    .long   LPTMR1_IRQHandler                               /* Low-Power Timer 1 (INTMUX source IRQ0)*/
+    .long   Reserved49_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ1)*/
+    .long   Reserved50_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ2)*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ3)*/
+    .long   SPI1_IRQHandler                                 /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 status and error (INTMUX source IRQ5)*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
+    .long   I2C1_IRQHandler                                 /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
+    .long   PMC_IRQHandler                                  /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete/read collision (INTMUX source IRQ10)*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator (INTMUX source IRQ11)*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator (INTMUX source IRQ14)*/
+    .long   Reserved63_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ15)*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0 (INTMUX source IRQ16)*/
+    .long   Reserved65_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ17)*/
+    .long   RTC_Alarm_IRQHandler                            /* Real time clock (INTMUX source IRQ18)*/
+    .long   Reserved67_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ19)*/
+    .long   Reserved68_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ20)*/
+    .long   Reserved69_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ21)*/
+    .long   Reserved70_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ22)*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ23)*/
+    .long   DMA4_IRQHandler                                 /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
+    .long   DMA5_IRQHandler                                 /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
+    .long   DMA6_IRQHandler                                 /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
+    .long   DMA7_IRQHandler                                 /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
+    .long   Reserved76_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ28)*/
+    .long   Reserved77_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ29)*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ30)*/
+    .long   Reserved79_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ31)*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr	r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA4_IRQHandler
+    def_irq_handler    DMA1_DMA5_IRQHandler
+    def_irq_handler    DMA2_DMA6_IRQHandler
+    def_irq_handler    DMA3_DMA7_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    QSPI0_IRQHandler
+    def_irq_handler    Reserved32_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    INTMUX0_0_IRQHandler
+    def_irq_handler    INTMUX0_1_IRQHandler
+    def_irq_handler    INTMUX0_2_IRQHandler
+    def_irq_handler    INTMUX0_3_IRQHandler
+    def_irq_handler    LPTMR1_IRQHandler
+    def_irq_handler    Reserved49_IRQHandler
+    def_irq_handler    Reserved50_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    Reserved63_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    Reserved65_IRQHandler
+    def_irq_handler    RTC_Alarm_IRQHandler
+    def_irq_handler    Reserved67_IRQHandler
+    def_irq_handler    Reserved68_IRQHandler
+    def_irq_handler    Reserved69_IRQHandler
+    def_irq_handler    Reserved70_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    Reserved76_IRQHandler
+    def_irq_handler    Reserved77_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    Reserved79_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/gcc/startup_MKL82Z7_qspi_patch.S

@@ -0,0 +1,266 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL82Z7.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL82Z7                                                                     */
+/*  @version: 1.4                                                                         */
+/*  @date:    2015-8-28                                                                   */
+/*  @build:   b150910                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA4_IRQHandler                            /* DMA channel 0, 4 transfer complete*/
+    .long   DMA1_DMA5_IRQHandler                            /* DMA channel 1, 5 transfer complete*/
+    .long   DMA2_DMA6_IRQHandler                            /* DMA channel 2, 6 transfer complete*/
+    .long   DMA3_DMA7_IRQHandler                            /* DMA channel 3, 7 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 7 error*/
+    .long   FLEXIO0_IRQHandler                              /* Flexible IO*/
+    .long   TPM0_IRQHandler                                 /* Timer/PWM module 0*/
+    .long   TPM1_IRQHandler                                 /* Timer/PWM module 1*/
+    .long   TPM2_IRQHandler                                 /* Timer/PWM module 2*/
+    .long   PIT0_IRQHandler                                 /* Periodic Interrupt Timer 0*/
+    .long   SPI0_IRQHandler                                 /* Serial Peripheral Interface 0*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   I2C0_IRQHandler                                 /* Inter-Integrated Circuit 0*/
+    .long   QSPI0_IRQHandler                                /* QuadSPI0 interrupt*/
+    .long   Reserved32_IRQHandler                           /* DryIce tamper detect*/
+    .long   PORTA_IRQHandler                                /* Pin detect Port A*/
+    .long   PORTB_IRQHandler                                /* Pin detect Port B*/
+    .long   PORTC_IRQHandler                                /* Pin detect Port C*/
+    .long   PORTD_IRQHandler                                /* Pin detect Port D*/
+    .long   PORTE_IRQHandler                                /* Pin detect Port E*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup*/
+    .long   LTC0_IRQHandler                                 /* Low power trusted cryptographic*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-Digital Converter 0*/
+    .long   LPTMR0_IRQHandler                               /* Low-Power Timer 0*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   INTMUX0_0_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-0*/
+    .long   INTMUX0_1_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-1*/
+    .long   INTMUX0_2_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-2*/
+    .long   INTMUX0_3_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-3*/
+    .long   LPTMR1_IRQHandler                               /* Low-Power Timer 1 (INTMUX source IRQ0)*/
+    .long   Reserved49_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ1)*/
+    .long   Reserved50_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ2)*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ3)*/
+    .long   SPI1_IRQHandler                                 /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 status and error (INTMUX source IRQ5)*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
+    .long   I2C1_IRQHandler                                 /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
+    .long   PMC_IRQHandler                                  /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete/read collision (INTMUX source IRQ10)*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator (INTMUX source IRQ11)*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator (INTMUX source IRQ14)*/
+    .long   Reserved63_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ15)*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0 (INTMUX source IRQ16)*/
+    .long   Reserved65_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ17)*/
+    .long   RTC_Alarm_IRQHandler                            /* Real time clock (INTMUX source IRQ18)*/
+    .long   Reserved67_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ19)*/
+    .long   Reserved68_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ20)*/
+    .long   Reserved69_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ21)*/
+    .long   Reserved70_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ22)*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ23)*/
+    .long   DMA4_IRQHandler                                 /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
+    .long   DMA5_IRQHandler                                 /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
+    .long   DMA6_IRQHandler                                 /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
+    .long   DMA7_IRQHandler                                 /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
+    .long   Reserved76_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ28)*/
+    .long   Reserved77_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ29)*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ30)*/
+    .long   Reserved79_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ31)*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFBDFE
+
+    .section BootloaderPatchHandler, "a"
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    ldr r0, = ROM_PatchHandler
+    blx r0
+#ifndef __NO_SYSTEM_INIT
+    ldr r0, = SystemInit
+    blx r0
+#endif
+    ldr r0, = init_data_bss
+    blx r0
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr r0, = __START
+    blx r0
+#else
+    ldr r0,=    __libc_init_array
+    blx r0
+    ldr r0, = main,
+    bx r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .text
+    .thumb
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr	r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_DMA4_IRQHandler
+    def_irq_handler    DMA1_DMA5_IRQHandler
+    def_irq_handler    DMA2_DMA6_IRQHandler
+    def_irq_handler    DMA3_DMA7_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    FLEXIO0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    LPUART0_IRQHandler
+    def_irq_handler    LPUART1_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    QSPI0_IRQHandler
+    def_irq_handler    Reserved32_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    INTMUX0_0_IRQHandler
+    def_irq_handler    INTMUX0_1_IRQHandler
+    def_irq_handler    INTMUX0_2_IRQHandler
+    def_irq_handler    INTMUX0_3_IRQHandler
+    def_irq_handler    LPTMR1_IRQHandler
+    def_irq_handler    Reserved49_IRQHandler
+    def_irq_handler    Reserved50_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    LPUART2_IRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    Reserved63_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    Reserved65_IRQHandler
+    def_irq_handler    RTC_Alarm_IRQHandler
+    def_irq_handler    Reserved67_IRQHandler
+    def_irq_handler    Reserved68_IRQHandler
+    def_irq_handler    Reserved69_IRQHandler
+    def_irq_handler    Reserved70_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    Reserved76_IRQHandler
+    def_irq_handler    Reserved77_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    Reserved79_IRQHandler
+
+    .end

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/iar/startup_MKL82Z7.s

@@ -0,0 +1,347 @@
+; ---------------------------------------------------------------------------------------
+;  @file:    startup_MKL82Z7.s
+;  @purpose: CMSIS Cortex-M0P Core Device Startup File
+;            MKL82Z7
+;  @version: 1.4
+;  @date:    2015-8-28
+;  @build:   b150910
+; ---------------------------------------------------------------------------------------
+;
+; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN  init_data_bss
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     DMA0_DMA4_IRQHandler                          ;DMA channel 0, 4 transfer complete
+        DCD     DMA1_DMA5_IRQHandler                          ;DMA channel 1, 5 transfer complete
+        DCD     DMA2_DMA6_IRQHandler                          ;DMA channel 2, 6 transfer complete
+        DCD     DMA3_DMA7_IRQHandler                          ;DMA channel 3, 7 transfer complete
+        DCD     DMA_Error_IRQHandler                          ;DMA channel 0 - 7 error
+        DCD     FLEXIO0_IRQHandler                            ;Flexible IO
+        DCD     TPM0_IRQHandler                               ;Timer/PWM module 0
+        DCD     TPM1_IRQHandler                               ;Timer/PWM module 1
+        DCD     TPM2_IRQHandler                               ;Timer/PWM module 2
+        DCD     PIT0_IRQHandler                               ;Periodic Interrupt Timer 0
+        DCD     SPI0_IRQHandler                               ;Serial Peripheral Interface 0
+        DCD     EMVSIM0_IRQHandler                            ;EMVSIM0 common interrupt
+        DCD     LPUART0_IRQHandler                            ;LPUART0 status and error
+        DCD     LPUART1_IRQHandler                            ;LPUART1 status and error
+        DCD     I2C0_IRQHandler                               ;Inter-Integrated Circuit 0
+        DCD     QSPI0_IRQHandler                              ;QuadSPI0 interrupt
+        DCD     Reserved32_IRQHandler                         ;DryIce tamper detect
+        DCD     PORTA_IRQHandler                              ;Pin detect Port A
+        DCD     PORTB_IRQHandler                              ;Pin detect Port B
+        DCD     PORTC_IRQHandler                              ;Pin detect Port C
+        DCD     PORTD_IRQHandler                              ;Pin detect Port D
+        DCD     PORTE_IRQHandler                              ;Pin detect Port E
+        DCD     LLWU_IRQHandler                               ;Low Leakage Wakeup
+        DCD     LTC0_IRQHandler                               ;Low power trusted cryptographic
+        DCD     USB0_IRQHandler                               ;USB OTG interrupt
+        DCD     ADC0_IRQHandler                               ;Analog-to-Digital Converter 0
+        DCD     LPTMR0_IRQHandler                             ;Low-Power Timer 0
+        DCD     RTC_Seconds_IRQHandler                        ;RTC seconds
+        DCD     INTMUX0_0_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-0
+        DCD     INTMUX0_1_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-1
+        DCD     INTMUX0_2_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-2
+        DCD     INTMUX0_3_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-3
+        DCD     LPTMR1_IRQHandler                             ;Low-Power Timer 1 (INTMUX source IRQ0)
+        DCD     Reserved49_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ1)
+        DCD     Reserved50_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ2)
+        DCD     Reserved51_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ3)
+        DCD     SPI1_IRQHandler                               ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+        DCD     LPUART2_IRQHandler                            ;LPUART2 status and error (INTMUX source IRQ5)
+        DCD     EMVSIM1_IRQHandler                            ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+        DCD     I2C1_IRQHandler                               ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+        DCD     TSI0_IRQHandler                               ;Touch Sensing Input 0 (INTMUX source IRQ8)
+        DCD     PMC_IRQHandler                                ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+        DCD     FTFA_IRQHandler                               ;FTFA command complete/read collision (INTMUX source IRQ10)
+        DCD     MCG_IRQHandler                                ;Multipurpose clock generator (INTMUX source IRQ11)
+        DCD     WDOG_EWM_IRQHandler                           ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+        DCD     DAC0_IRQHandler                               ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+        DCD     TRNG0_IRQHandler                              ;True randon number generator (INTMUX source IRQ14)
+        DCD     Reserved63_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ15)
+        DCD     CMP0_IRQHandler                               ;Comparator 0 (INTMUX source IRQ16)
+        DCD     Reserved65_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ17)
+        DCD     RTC_Alarm_IRQHandler                          ;Real time clock (INTMUX source IRQ18)
+        DCD     Reserved67_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ19)
+        DCD     Reserved68_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ20)
+        DCD     Reserved69_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ21)
+        DCD     Reserved70_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ22)
+        DCD     Reserved71_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ23)
+        DCD     DMA4_IRQHandler                               ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+        DCD     DMA5_IRQHandler                               ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+        DCD     DMA6_IRQHandler                               ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+        DCD     DMA7_IRQHandler                               ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+        DCD     Reserved76_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ28)
+        DCD     Reserved77_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ29)
+        DCD     Reserved78_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ30)
+        DCD     Reserved79_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+        SECTION FlashConfig:CODE
+__FlashConfig
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFF3DFE
+__FlashConfig_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        CPSID   I               ; Mask interrupts
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =init_data_bss
+        BLX     R0
+        CPSIE   I               ; Unmask interrupts
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK DMA0_DMA4_IRQHandler
+        PUBWEAK DMA1_DMA5_IRQHandler
+        PUBWEAK DMA2_DMA6_IRQHandler
+        PUBWEAK DMA3_DMA7_IRQHandler
+        PUBWEAK DMA_Error_IRQHandler
+        PUBWEAK FLEXIO0_IRQHandler
+        PUBWEAK TPM0_IRQHandler
+        PUBWEAK TPM1_IRQHandler
+        PUBWEAK TPM2_IRQHandler
+        PUBWEAK PIT0_IRQHandler
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK EMVSIM0_IRQHandler
+        PUBWEAK LPUART0_IRQHandler
+        PUBWEAK LPUART1_IRQHandler
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK QSPI0_IRQHandler
+        PUBWEAK Reserved32_IRQHandler
+        PUBWEAK PORTA_IRQHandler
+        PUBWEAK PORTB_IRQHandler
+        PUBWEAK PORTC_IRQHandler
+        PUBWEAK PORTD_IRQHandler
+        PUBWEAK PORTE_IRQHandler
+        PUBWEAK LLWU_IRQHandler
+        PUBWEAK LTC0_IRQHandler
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK ADC0_IRQHandler
+        PUBWEAK LPTMR0_IRQHandler
+        PUBWEAK RTC_Seconds_IRQHandler
+        PUBWEAK INTMUX0_0_IRQHandler
+        PUBWEAK INTMUX0_1_IRQHandler
+        PUBWEAK INTMUX0_2_IRQHandler
+        PUBWEAK INTMUX0_3_IRQHandler
+        PUBWEAK LPTMR1_IRQHandler
+        PUBWEAK Reserved49_IRQHandler
+        PUBWEAK Reserved50_IRQHandler
+        PUBWEAK Reserved51_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK LPUART2_IRQHandler
+        PUBWEAK EMVSIM1_IRQHandler
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK TSI0_IRQHandler
+        PUBWEAK PMC_IRQHandler
+        PUBWEAK FTFA_IRQHandler
+        PUBWEAK MCG_IRQHandler
+        PUBWEAK WDOG_EWM_IRQHandler
+        PUBWEAK DAC0_IRQHandler
+        PUBWEAK TRNG0_IRQHandler
+        PUBWEAK Reserved63_IRQHandler
+        PUBWEAK CMP0_IRQHandler
+        PUBWEAK Reserved65_IRQHandler
+        PUBWEAK RTC_Alarm_IRQHandler
+        PUBWEAK Reserved67_IRQHandler
+        PUBWEAK Reserved68_IRQHandler
+        PUBWEAK Reserved69_IRQHandler
+        PUBWEAK Reserved70_IRQHandler
+        PUBWEAK Reserved71_IRQHandler
+        PUBWEAK DMA4_IRQHandler
+        PUBWEAK DMA5_IRQHandler
+        PUBWEAK DMA6_IRQHandler
+        PUBWEAK DMA7_IRQHandler
+        PUBWEAK Reserved76_IRQHandler
+        PUBWEAK Reserved77_IRQHandler
+        PUBWEAK Reserved78_IRQHandler
+        PUBWEAK Reserved79_IRQHandler
+        PUBWEAK DefaultISR
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+        LDR R0, =DefaultISR
+        BX R0
+
+        END

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/iar/startup_MKL82Z7_qspi.s

@@ -0,0 +1,347 @@
+; ---------------------------------------------------------------------------------------
+;  @file:    startup_MKL82Z7.s
+;  @purpose: CMSIS Cortex-M0P Core Device Startup File
+;            MKL82Z7
+;  @version: 1.4
+;  @date:    2015-8-28
+;  @build:   b150910
+; ---------------------------------------------------------------------------------------
+;
+; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN  init_data_bss
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     DMA0_DMA4_IRQHandler                          ;DMA channel 0, 4 transfer complete
+        DCD     DMA1_DMA5_IRQHandler                          ;DMA channel 1, 5 transfer complete
+        DCD     DMA2_DMA6_IRQHandler                          ;DMA channel 2, 6 transfer complete
+        DCD     DMA3_DMA7_IRQHandler                          ;DMA channel 3, 7 transfer complete
+        DCD     DMA_Error_IRQHandler                          ;DMA channel 0 - 7 error
+        DCD     FLEXIO0_IRQHandler                            ;Flexible IO
+        DCD     TPM0_IRQHandler                               ;Timer/PWM module 0
+        DCD     TPM1_IRQHandler                               ;Timer/PWM module 1
+        DCD     TPM2_IRQHandler                               ;Timer/PWM module 2
+        DCD     PIT0_IRQHandler                               ;Periodic Interrupt Timer 0
+        DCD     SPI0_IRQHandler                               ;Serial Peripheral Interface 0
+        DCD     EMVSIM0_IRQHandler                            ;EMVSIM0 common interrupt
+        DCD     LPUART0_IRQHandler                            ;LPUART0 status and error
+        DCD     LPUART1_IRQHandler                            ;LPUART1 status and error
+        DCD     I2C0_IRQHandler                               ;Inter-Integrated Circuit 0
+        DCD     QSPI0_IRQHandler                              ;QuadSPI0 interrupt
+        DCD     Reserved32_IRQHandler                         ;DryIce tamper detect
+        DCD     PORTA_IRQHandler                              ;Pin detect Port A
+        DCD     PORTB_IRQHandler                              ;Pin detect Port B
+        DCD     PORTC_IRQHandler                              ;Pin detect Port C
+        DCD     PORTD_IRQHandler                              ;Pin detect Port D
+        DCD     PORTE_IRQHandler                              ;Pin detect Port E
+        DCD     LLWU_IRQHandler                               ;Low Leakage Wakeup
+        DCD     LTC0_IRQHandler                               ;Low power trusted cryptographic
+        DCD     USB0_IRQHandler                               ;USB OTG interrupt
+        DCD     ADC0_IRQHandler                               ;Analog-to-Digital Converter 0
+        DCD     LPTMR0_IRQHandler                             ;Low-Power Timer 0
+        DCD     RTC_Seconds_IRQHandler                        ;RTC seconds
+        DCD     INTMUX0_0_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-0
+        DCD     INTMUX0_1_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-1
+        DCD     INTMUX0_2_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-2
+        DCD     INTMUX0_3_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-3
+        DCD     LPTMR1_IRQHandler                             ;Low-Power Timer 1 (INTMUX source IRQ0)
+        DCD     Reserved49_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ1)
+        DCD     Reserved50_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ2)
+        DCD     Reserved51_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ3)
+        DCD     SPI1_IRQHandler                               ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+        DCD     LPUART2_IRQHandler                            ;LPUART2 status and error (INTMUX source IRQ5)
+        DCD     EMVSIM1_IRQHandler                            ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+        DCD     I2C1_IRQHandler                               ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+        DCD     TSI0_IRQHandler                               ;Touch Sensing Input 0 (INTMUX source IRQ8)
+        DCD     PMC_IRQHandler                                ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+        DCD     FTFA_IRQHandler                               ;FTFA command complete/read collision (INTMUX source IRQ10)
+        DCD     MCG_IRQHandler                                ;Multipurpose clock generator (INTMUX source IRQ11)
+        DCD     WDOG_EWM_IRQHandler                           ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+        DCD     DAC0_IRQHandler                               ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+        DCD     TRNG0_IRQHandler                              ;True randon number generator (INTMUX source IRQ14)
+        DCD     Reserved63_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ15)
+        DCD     CMP0_IRQHandler                               ;Comparator 0 (INTMUX source IRQ16)
+        DCD     Reserved65_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ17)
+        DCD     RTC_Alarm_IRQHandler                          ;Real time clock (INTMUX source IRQ18)
+        DCD     Reserved67_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ19)
+        DCD     Reserved68_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ20)
+        DCD     Reserved69_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ21)
+        DCD     Reserved70_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ22)
+        DCD     Reserved71_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ23)
+        DCD     DMA4_IRQHandler                               ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+        DCD     DMA5_IRQHandler                               ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+        DCD     DMA6_IRQHandler                               ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+        DCD     DMA7_IRQHandler                               ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+        DCD     Reserved76_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ28)
+        DCD     Reserved77_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ29)
+        DCD     Reserved78_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ30)
+        DCD     Reserved79_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+        SECTION FlashConfig:CODE
+__FlashConfig
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFBDFE
+__FlashConfig_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        CPSID   I               ; Mask interrupts
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =init_data_bss
+        BLX     R0
+        CPSIE   I               ; Unmask interrupts
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK DMA0_DMA4_IRQHandler
+        PUBWEAK DMA1_DMA5_IRQHandler
+        PUBWEAK DMA2_DMA6_IRQHandler
+        PUBWEAK DMA3_DMA7_IRQHandler
+        PUBWEAK DMA_Error_IRQHandler
+        PUBWEAK FLEXIO0_IRQHandler
+        PUBWEAK TPM0_IRQHandler
+        PUBWEAK TPM1_IRQHandler
+        PUBWEAK TPM2_IRQHandler
+        PUBWEAK PIT0_IRQHandler
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK EMVSIM0_IRQHandler
+        PUBWEAK LPUART0_IRQHandler
+        PUBWEAK LPUART1_IRQHandler
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK QSPI0_IRQHandler
+        PUBWEAK Reserved32_IRQHandler
+        PUBWEAK PORTA_IRQHandler
+        PUBWEAK PORTB_IRQHandler
+        PUBWEAK PORTC_IRQHandler
+        PUBWEAK PORTD_IRQHandler
+        PUBWEAK PORTE_IRQHandler
+        PUBWEAK LLWU_IRQHandler
+        PUBWEAK LTC0_IRQHandler
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK ADC0_IRQHandler
+        PUBWEAK LPTMR0_IRQHandler
+        PUBWEAK RTC_Seconds_IRQHandler
+        PUBWEAK INTMUX0_0_IRQHandler
+        PUBWEAK INTMUX0_1_IRQHandler
+        PUBWEAK INTMUX0_2_IRQHandler
+        PUBWEAK INTMUX0_3_IRQHandler
+        PUBWEAK LPTMR1_IRQHandler
+        PUBWEAK Reserved49_IRQHandler
+        PUBWEAK Reserved50_IRQHandler
+        PUBWEAK Reserved51_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK LPUART2_IRQHandler
+        PUBWEAK EMVSIM1_IRQHandler
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK TSI0_IRQHandler
+        PUBWEAK PMC_IRQHandler
+        PUBWEAK FTFA_IRQHandler
+        PUBWEAK MCG_IRQHandler
+        PUBWEAK WDOG_EWM_IRQHandler
+        PUBWEAK DAC0_IRQHandler
+        PUBWEAK TRNG0_IRQHandler
+        PUBWEAK Reserved63_IRQHandler
+        PUBWEAK CMP0_IRQHandler
+        PUBWEAK Reserved65_IRQHandler
+        PUBWEAK RTC_Alarm_IRQHandler
+        PUBWEAK Reserved67_IRQHandler
+        PUBWEAK Reserved68_IRQHandler
+        PUBWEAK Reserved69_IRQHandler
+        PUBWEAK Reserved70_IRQHandler
+        PUBWEAK Reserved71_IRQHandler
+        PUBWEAK DMA4_IRQHandler
+        PUBWEAK DMA5_IRQHandler
+        PUBWEAK DMA6_IRQHandler
+        PUBWEAK DMA7_IRQHandler
+        PUBWEAK Reserved76_IRQHandler
+        PUBWEAK Reserved77_IRQHandler
+        PUBWEAK Reserved78_IRQHandler
+        PUBWEAK Reserved79_IRQHandler
+        PUBWEAK DefaultISR
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+        LDR R0, =DefaultISR
+        BX R0
+
+        END

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/iar/startup_MKL82Z7_qspi_patch.s

@@ -0,0 +1,350 @@
+; ---------------------------------------------------------------------------------------
+;  @file:    startup_MKL82Z7.s
+;  @purpose: CMSIS Cortex-M0P Core Device Startup File
+;            MKL82Z7
+;  @version: 1.4
+;  @date:    2015-8-28
+;  @build:   b150910
+; ---------------------------------------------------------------------------------------
+;
+; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN  ROM_PatchHandler
+        EXTERN  init_data_bss
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     DMA0_DMA4_IRQHandler                          ;DMA channel 0, 4 transfer complete
+        DCD     DMA1_DMA5_IRQHandler                          ;DMA channel 1, 5 transfer complete
+        DCD     DMA2_DMA6_IRQHandler                          ;DMA channel 2, 6 transfer complete
+        DCD     DMA3_DMA7_IRQHandler                          ;DMA channel 3, 7 transfer complete
+        DCD     DMA_Error_IRQHandler                          ;DMA channel 0 - 7 error
+        DCD     FLEXIO0_IRQHandler                            ;Flexible IO
+        DCD     TPM0_IRQHandler                               ;Timer/PWM module 0
+        DCD     TPM1_IRQHandler                               ;Timer/PWM module 1
+        DCD     TPM2_IRQHandler                               ;Timer/PWM module 2
+        DCD     PIT0_IRQHandler                               ;Periodic Interrupt Timer 0
+        DCD     SPI0_IRQHandler                               ;Serial Peripheral Interface 0
+        DCD     EMVSIM0_IRQHandler                            ;EMVSIM0 common interrupt
+        DCD     LPUART0_IRQHandler                            ;LPUART0 status and error
+        DCD     LPUART1_IRQHandler                            ;LPUART1 status and error
+        DCD     I2C0_IRQHandler                               ;Inter-Integrated Circuit 0
+        DCD     QSPI0_IRQHandler                              ;QuadSPI0 interrupt
+        DCD     Reserved32_IRQHandler                         ;DryIce tamper detect
+        DCD     PORTA_IRQHandler                              ;Pin detect Port A
+        DCD     PORTB_IRQHandler                              ;Pin detect Port B
+        DCD     PORTC_IRQHandler                              ;Pin detect Port C
+        DCD     PORTD_IRQHandler                              ;Pin detect Port D
+        DCD     PORTE_IRQHandler                              ;Pin detect Port E
+        DCD     LLWU_IRQHandler                               ;Low Leakage Wakeup
+        DCD     LTC0_IRQHandler                               ;Low power trusted cryptographic
+        DCD     USB0_IRQHandler                               ;USB OTG interrupt
+        DCD     ADC0_IRQHandler                               ;Analog-to-Digital Converter 0
+        DCD     LPTMR0_IRQHandler                             ;Low-Power Timer 0
+        DCD     RTC_Seconds_IRQHandler                        ;RTC seconds
+        DCD     INTMUX0_0_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-0
+        DCD     INTMUX0_1_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-1
+        DCD     INTMUX0_2_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-2
+        DCD     INTMUX0_3_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-3
+        DCD     LPTMR1_IRQHandler                             ;Low-Power Timer 1 (INTMUX source IRQ0)
+        DCD     Reserved49_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ1)
+        DCD     Reserved50_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ2)
+        DCD     Reserved51_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ3)
+        DCD     SPI1_IRQHandler                               ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+        DCD     LPUART2_IRQHandler                            ;LPUART2 status and error (INTMUX source IRQ5)
+        DCD     EMVSIM1_IRQHandler                            ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+        DCD     I2C1_IRQHandler                               ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+        DCD     TSI0_IRQHandler                               ;Touch Sensing Input 0 (INTMUX source IRQ8)
+        DCD     PMC_IRQHandler                                ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+        DCD     FTFA_IRQHandler                               ;FTFA command complete/read collision (INTMUX source IRQ10)
+        DCD     MCG_IRQHandler                                ;Multipurpose clock generator (INTMUX source IRQ11)
+        DCD     WDOG_EWM_IRQHandler                           ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+        DCD     DAC0_IRQHandler                               ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+        DCD     TRNG0_IRQHandler                              ;True randon number generator (INTMUX source IRQ14)
+        DCD     Reserved63_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ15)
+        DCD     CMP0_IRQHandler                               ;Comparator 0 (INTMUX source IRQ16)
+        DCD     Reserved65_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ17)
+        DCD     RTC_Alarm_IRQHandler                          ;Real time clock (INTMUX source IRQ18)
+        DCD     Reserved67_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ19)
+        DCD     Reserved68_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ20)
+        DCD     Reserved69_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ21)
+        DCD     Reserved70_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ22)
+        DCD     Reserved71_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ23)
+        DCD     DMA4_IRQHandler                               ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+        DCD     DMA5_IRQHandler                               ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+        DCD     DMA6_IRQHandler                               ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+        DCD     DMA7_IRQHandler                               ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+        DCD     Reserved76_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ28)
+        DCD     Reserved77_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ29)
+        DCD     Reserved78_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ30)
+        DCD     Reserved79_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+        SECTION FlashConfig:CODE
+__FlashConfig
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFFFFF
+      	DCD	0xFFFFBDFE
+__FlashConfig_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION BootloaderPatchHandler:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        CPSID   I               ; Mask interrupts
+        LDR     R0, =ROM_PatchHandler
+        BLX     R0
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =init_data_bss
+        BLX     R0
+        CPSIE   I               ; Unmask interrupts
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK DMA0_DMA4_IRQHandler
+        PUBWEAK DMA1_DMA5_IRQHandler
+        PUBWEAK DMA2_DMA6_IRQHandler
+        PUBWEAK DMA3_DMA7_IRQHandler
+        PUBWEAK DMA_Error_IRQHandler
+        PUBWEAK FLEXIO0_IRQHandler
+        PUBWEAK TPM0_IRQHandler
+        PUBWEAK TPM1_IRQHandler
+        PUBWEAK TPM2_IRQHandler
+        PUBWEAK PIT0_IRQHandler
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK EMVSIM0_IRQHandler
+        PUBWEAK LPUART0_IRQHandler
+        PUBWEAK LPUART1_IRQHandler
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK QSPI0_IRQHandler
+        PUBWEAK Reserved32_IRQHandler
+        PUBWEAK PORTA_IRQHandler
+        PUBWEAK PORTB_IRQHandler
+        PUBWEAK PORTC_IRQHandler
+        PUBWEAK PORTD_IRQHandler
+        PUBWEAK PORTE_IRQHandler
+        PUBWEAK LLWU_IRQHandler
+        PUBWEAK LTC0_IRQHandler
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK ADC0_IRQHandler
+        PUBWEAK LPTMR0_IRQHandler
+        PUBWEAK RTC_Seconds_IRQHandler
+        PUBWEAK INTMUX0_0_IRQHandler
+        PUBWEAK INTMUX0_1_IRQHandler
+        PUBWEAK INTMUX0_2_IRQHandler
+        PUBWEAK INTMUX0_3_IRQHandler
+        PUBWEAK LPTMR1_IRQHandler
+        PUBWEAK Reserved49_IRQHandler
+        PUBWEAK Reserved50_IRQHandler
+        PUBWEAK Reserved51_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK LPUART2_IRQHandler
+        PUBWEAK EMVSIM1_IRQHandler
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK TSI0_IRQHandler
+        PUBWEAK PMC_IRQHandler
+        PUBWEAK FTFA_IRQHandler
+        PUBWEAK MCG_IRQHandler
+        PUBWEAK WDOG_EWM_IRQHandler
+        PUBWEAK DAC0_IRQHandler
+        PUBWEAK TRNG0_IRQHandler
+        PUBWEAK Reserved63_IRQHandler
+        PUBWEAK CMP0_IRQHandler
+        PUBWEAK Reserved65_IRQHandler
+        PUBWEAK RTC_Alarm_IRQHandler
+        PUBWEAK Reserved67_IRQHandler
+        PUBWEAK Reserved68_IRQHandler
+        PUBWEAK Reserved69_IRQHandler
+        PUBWEAK Reserved70_IRQHandler
+        PUBWEAK Reserved71_IRQHandler
+        PUBWEAK DMA4_IRQHandler
+        PUBWEAK DMA5_IRQHandler
+        PUBWEAK DMA6_IRQHandler
+        PUBWEAK DMA7_IRQHandler
+        PUBWEAK Reserved76_IRQHandler
+        PUBWEAK Reserved77_IRQHandler
+        PUBWEAK Reserved78_IRQHandler
+        PUBWEAK Reserved79_IRQHandler
+        PUBWEAK DefaultISR
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DMA4_IRQHandler
+DMA1_DMA5_IRQHandler
+DMA2_DMA6_IRQHandler
+DMA3_DMA7_IRQHandler
+DMA_Error_IRQHandler
+FLEXIO0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_IRQHandler
+EMVSIM0_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+I2C0_IRQHandler
+QSPI0_IRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_IRQHandler
+INTMUX0_1_IRQHandler
+INTMUX0_2_IRQHandler
+INTMUX0_3_IRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_IRQHandler
+LPUART2_IRQHandler
+EMVSIM1_IRQHandler
+I2C1_IRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+        LDR R0, =DefaultISR
+        BX R0
+
+        END

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/system_MKL82Z7.h

@@ -0,0 +1,390 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.0.3 June 2015
+**     Version:             rev. 1.4, 2015-08-28
+**     Build:               b150910
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7
+ * @version 1.4
+ * @date 2015-08-28
+ * @brief Device specific configuration file for MKL82Z7 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL82Z7_H_
+#define SYSTEM_MKL82Z7_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef DISABLE_WDOG
+#define DISABLE_WDOG 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximal speed configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 96MHz
+         Bus clock  = 24MHz
+   2 ... Chip internally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 96MHz
+         Bus clock  = 24MHz
+   5 ... Maximum achievable clock frequency configuration in RUN mode
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 72MHz
+         Bus clock  = 24MHz
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ \
+    12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ                                                                       \
+    32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
+              */
+#define CPU_INT_SLOW_CLK_HZ 32768U   /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */      /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */      /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
+#define MCG_MODE MCG_MODE_FEI          /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1,OUTDIV5=1 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x00011000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+                                           /* SIM_SOPT2:
+                                            * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+                                            */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 1)
+#define DEFAULT_SYSTEM_CLOCK 96000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 2)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPI    /* Clock generator mode */
+/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=4,OUTDIV5=0 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x03040000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 3)
+#define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_BLPE    /* Clock generator mode */
+/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+#define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0x0B */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 4)
+#define DEFAULT_SYSTEM_CLOCK 96000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
+#define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=3,USBFRAC=0 */
+#define SYSTEM_SIM_CLKDIV2_VALUE 0x03U       /* SIM_CLKDIV2 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#elif(CLOCK_SETUP == 5)
+#define DEFAULT_SYSTEM_CLOCK 72000000U /* Default System clock value */
+#define MCG_MODE MCG_MODE_PEE     /* Clock generator mode */
+/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+#define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
+/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
+#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=8 */
+#define SYSTEM_MCG_C6_VALUE 0x48U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=2,OUTDIV4=2,OUTDIV5=0 */
+#define SYSTEM_SIM_CLKDIV1_VALUE 0x02020000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
+#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2:
+ * EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
+ */
+#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
+#endif
+#else
+#define DEFAULT_SYSTEM_CLOCK 20971520u
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL82Z7_H_) */

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/system_MKL82Z7_qspi.c

@@ -0,0 +1,309 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.0.3 June 2015
+**     Version:             rev. 1.4, 2015-08-28
+**     Build:               b150910
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7
+ * @version 1.4
+ * @date 2015-08-28
+ * @brief Device specific configuration file for MKL82Z7 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t RESERVED2[2];
+    uint8_t RESERVED3[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED4[12];
+} system_bootloader_config_t;
+
+#ifndef BOOTLOADER_CONFIG
+#define BOOTLOADER_CONFIG 1 /* Enable BootloaderConfig Area by default */
+#endif
+
+#if (BOOTLOADER_CONFIG)
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0xFFFFU, /* Use default timeout */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 72000000ul;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+    uint16_t Divider;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U)
+    {
+        /* Output of FLL or PLL is selected */
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
+        {
+            /* FLL is selected */
+            if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)
+            {
+                /* External reference clock is selected */
+                switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+                {
+                    case 0x00U:
+                        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                        break;
+                    case 0x01U:
+                        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                        break;
+                    case 0x02U:
+                    default:
+                        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                        break;
+                }
+                if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
+                {
+                    switch (MCG->C1 & MCG_C1_FRDIV_MASK)
+                    {
+                        case 0x38U:
+                            Divider = 1536U;
+                            break;
+                        case 0x30U:
+                            Divider = 1280U;
+                            break;
+                        default:
+                            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                            break;
+                    }
+                }
+                else
+                { /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+                    Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                }
+                MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+            }
+            else
+            {                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+                MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+            }                                      /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+            /* Select correct multiplier to calculate the MCG output clock  */
+            switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK))
+            {
+                case 0x00U:
+                    MCGOUTClock *= 640U;
+                    break;
+                case 0x20U:
+                    MCGOUTClock *= 1280U;
+                    break;
+                case 0x40U:
+                    MCGOUTClock *= 1920U;
+                    break;
+                case 0x60U:
+                    MCGOUTClock *= 2560U;
+                    break;
+                case 0x80U:
+                    MCGOUTClock *= 732U;
+                    break;
+                case 0xA0U:
+                    MCGOUTClock *= 1464U;
+                    break;
+                case 0xC0U:
+                    MCGOUTClock *= 2197U;
+                    break;
+                case 0xE0U:
+                    MCGOUTClock *= 2929U;
+                    break;
+                default:
+                    break;
+            }
+        }
+        else
+        { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+            /* PLL is selected */
+            Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+            MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+            Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+            MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+            MCGOUTClock /= 2;       /* Calculate the MCG output clock */
+        }                           /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
+    {
+        /* Internal reference clock is selected */
+        if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
+        {
+            MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+        }
+        else
+        { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+            Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+            MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+        }                                                            /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+    }
+    else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
+    {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK)
+        {
+            case 0x00U:
+                MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+                break;
+            case 0x01U:
+                MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+                break;
+            case 0x02U:
+            default:
+                MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+                break;
+        }
+    }
+    else
+    { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+        /* Reserved value */
+        return;
+    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    SystemCoreClock =
+        (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

apps/demo_qspi/led_demo/devices/MKL82Z7/startup/system_MKL82Z7_qspi_patch.c

@@ -0,0 +1,230 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.0.3 June 2015
+**     Version:             rev. 1.4, 2015-08-28
+**     Build:               b150910
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7
+ * @version 1.4
+ * @date 2015-08-28
+ * @brief Device specific configuration file for MKL82Z7 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+    uint32_t tag;               /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+    uint32_t crcStartAddress;   /*!< Start address for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check. */
+    uint32_t crcByteCount;      /*!< Byte count for application image CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not prform any CRC check. */
+    uint32_t crcExpectedValue;  /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis
+                                   bootloader by default will not perform any CRC check.*/
+    uint8_t enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                     bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                     Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+    uint8_t i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C
+                                   slave address */
+    uint16_t peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF,
+                                              defaults to 5 seconds. */
+    uint16_t usbVid; /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to
+                        0x15A2. */
+    uint16_t usbPid; /*!< Sets the USB Product ID reported by the device during enumeration. */
+    uint32_t usbStringsPointer; /*!< Sets the USB Strings reported by the device during enumeration. */
+    uint8_t clockFlags;   /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is
+                             cleared (0).
+                              bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+    uint8_t clockDivider; /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+    uint8_t bootFlags; /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal
+                          flash image depending on FOPT BOOTSRC_SEL bits.
+                           If the bit is set, then Kinetis bootloader will prepare for host communication over serial
+                          peripherals. */
+    uint8_t RESERVED1;
+    uint32_t RESERVED2[2];
+    uint8_t RESERVED3[8];
+    uint32_t qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+    uint8_t RESERVED4[12];
+} system_bootloader_config_t;
+
+#ifndef BOOTLOADER_CONFIG
+#define BOOTLOADER_CONFIG 1 /* Enable BootloaderConfig Area by default */
+#endif
+
+#if (BOOTLOADER_CONFIG)
+/* Bootlader configuration area */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language = extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @"BootloaderConfig" =
+#elif defined(__GNUC__)
+__attribute__((section(".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    {
+      .tag = 0x6766636BU,                      /* Magic Number */
+      .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+      .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+      .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+      .enabledPeripherals = 0x17,              /* Enable all peripherals */
+      .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+      .peripheralDetectionTimeoutMs = 0xFFFFU, /* Use default timeout */
+      .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+      .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+      .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+      .clockFlags = 0x01,                      /* Enable High speed mode */
+      .clockDivider = 0xFF,                    /* Use clock divider 1 */
+      .bootFlags = 0x01,                       /* Enable communication with host */
+      .qspiConfigBlockPtr = 0x2000,            /* QCB is placed at 0x2000 */
+    };
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = 72000000ul;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the rom patch code on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "rom_patch_code"
+const uint8_t s_rom_patch[124] @"rom_patch_code" =
+#elif defined(__GNUC__)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+
+#elif defined(__CC_ARM)
+__attribute__((section("rom_patch_code"))) const uint8_t s_rom_patch[124] __attribute__((used)) =
+#else
+#error Unsupported compiler!
+#endif
+    { 0x10, 0xB5, 0x01, 0x00, 0x17, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x17, 0x4B, 0x1B, 0x68, 0xDB, 0x00, 0x02, 0xD5,
+      0x16, 0x4A, 0x10, 0x00, 0x18, 0x30, 0x13, 0x68, 0x15, 0x4C, 0x1C, 0x40, 0x14, 0x60, 0x13, 0x68, 0x0C, 0x69,
+      0x24, 0x04, 0x1C, 0x43, 0x14, 0x60, 0x02, 0x68, 0x11, 0x4B, 0x13, 0x40, 0x03, 0x60, 0xDA, 0x22, 0x52, 0x00,
+      0x89, 0x18, 0x02, 0x68, 0x0B, 0x68, 0x1B, 0x04, 0xFC, 0x24, 0xA4, 0x03, 0x1C, 0x40, 0x14, 0x43, 0x04, 0x60,
+      0x02, 0x68, 0x0B, 0x4B, 0x13, 0x40, 0x03, 0x60, 0x02, 0x68, 0x49, 0x68, 0x09, 0x06, 0xFC, 0x23, 0x9B, 0x05,
+      0x0B, 0x40, 0x13, 0x43, 0x03, 0x60, 0x00, 0x20, 0x10, 0xBD, 0x0C, 0xA0, 0x0D, 0x40, 0x24, 0x80, 0x04, 0x40,
+      0x0C, 0xA0, 0x05, 0x40, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0 };
+
+/*
+ *   ROM patch handler for ROM patch code execution.
+ */
+#if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the ROM_PatchHandler on correct location defined in linker file. */
+#pragma language = extended
+#pragma section = "BootloaderPatchHandler"
+void ROM_PatchHandler(void) @"BootloaderPatchHandler"
+#elif defined(__GNUC__)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#elif defined(__CC_ARM)
+__attribute__((section("BootloaderPatchHandler"))) void ROM_PatchHandler(void)
+#else
+#error Unsupported compiler!
+#endif
+{
+    typedef int (*patch_handler_t)(uint32_t);
+
+#if defined(__IAR_SYSTEMS_ICC__)
+    uint32_t s_rom_patch_start = (uint32_t)__section_begin("rom_patch_code");
+#elif defined(__CC_ARM)
+    extern uint32_t Load$$EXEC_m_rom_patch_code$$Base[];
+    uint32_t s_rom_patch_start = (uint32_t)&Load$$EXEC_m_rom_patch_code$$Base;
+#elif defined(__GNUC__)
+    extern uint32_t rom_patch_code_start[];
+    uint32_t s_rom_patch_start = (uint32_t)&rom_patch_code_start;
+#endif
+
+    uint32_t patch_start = s_rom_patch_start + 1;
+    patch_handler_t patch_run = (patch_handler_t)patch_start;
+    patch_run(BootloaderConfig.qspiConfigBlockPtr);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+void SystemInit(void)
+{
+}

apps/demo_qspi/led_demo/src/boot_to_qspi_alias_memory.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+
+typedef void (*application_handler_t)(void);
+
+enum
+{
+    QuadSPI_Image_Start = 0x04001000ul,
+};
+
+int main(void)
+{
+    static uint32_t s_stackPointer = 0;
+    static application_handler_t runApplication;
+
+    // Set the VTOR to the application vector table address
+    SCB->VTOR = QuadSPI_Image_Start;
+
+    s_stackPointer = *(uint32_t *)QuadSPI_Image_Start;
+    runApplication = *(application_handler_t *)(QuadSPI_Image_Start + 4);
+
+    __set_MSP(s_stackPointer);
+    __set_PSP(s_stackPointer);
+
+    runApplication();
+
+    // Never run here
+    while (1)
+    {
+    }
+}

apps/demo_qspi/led_demo/src/led_bsp.h

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LED_BSP_H__
+#define __LED_BSP_H__
+
+#include "fsl_device_registers.h"
+
+#define LED_ON_LOW_LEVEL 1
+#define LED_ON_HIGH_LEVEL 2
+
+#define LED0 (1)
+#define LED1 (2)
+#define LED2 (4)
+
+#if defined(TWR_K80F150M)
+#define MAX_LED_IDX (LED1)
+#define LED0_OFFSET 14
+#define LED1_OFFSET 15
+#define LED0_PORT (PORTD)
+#define LED0_GPIO (GPIOD)
+#define LED1_PORT (PORTD)
+#define LED1_GPIO (GPIOD)
+#define LED_POLARITY LED_ON_HIGH_LEVEL
+#elif defined(FRDM_K82F)
+#define MAX_LED_IDX (LED2)
+#define LED0_OFFSET 8
+#define LED1_OFFSET 9
+#define LED2_OFFSET 10
+#define LED0_PORT (PORTC)
+#define LED0_GPIO (GPIOC)
+#define LED1_PORT (PORTC)
+#define LED1_GPIO (GPIOC)
+#define LED2_PORT (PORTC)
+#define LED2_GPIO (GPIOC)
+#define LED_POLARITY LED_ON_LOW_LEVEL
+#elif defined(TWR_POS_K81)
+#define MAX_LED_IDX (LED2)
+#define LED0_OFFSET 7
+#define LED1_OFFSET 8
+#define LED2_OFFSET 13
+#define LED0_PORT (PORTC)
+#define LED0_GPIO (GPIOC)
+#define LED1_PORT (PORTC)
+#define LED1_GPIO (GPIOC)
+#define LED2_PORT (PORTC)
+#define LED2_GPIO (GPIOC)
+#define LED_POLARITY LED_ON_LOW_LEVEL
+#elif defined(TWR_KL8272M)
+#define MAX_LED_IDX (LED1)
+#define LED0_OFFSET 14
+#define LED1_OFFSET 15
+#define LED0_PORT (PORTD)
+#define LED0_GPIO (GPIOD)
+#define LED1_PORT (PORTD)
+#define LED1_GPIO (GPIOD)
+#define LED_POLARITY LED_ON_HIGH_LEVEL
+#elif defined(FRDM_KL82Z)
+#define MAX_LED_IDX (LED2)
+#define LED0_OFFSET 0
+#define LED1_OFFSET 1
+#define LED2_OFFSET 2
+#define LED0_PORT (PORTC)
+#define LED0_GPIO (GPIOC)
+#define LED1_PORT (PORTC)
+#define LED1_GPIO (GPIOC)
+#define LED2_PORT (PORTC)
+#define LED2_GPIO (GPIOC)
+#define LED_POLARITY LED_ON_LOW_LEVEL
+#elif defined(TWR_POS_KL81)
+#define MAX_LED_IDX (LED2)
+#define LED0_OFFSET 7
+#define LED1_OFFSET 8
+#define LED2_OFFSET 13
+#define LED0_PORT (PORTC)
+#define LED0_GPIO (GPIOC)
+#define LED1_PORT (PORTC)
+#define LED1_GPIO (GPIOC)
+#define LED2_PORT (PORTC)
+#define LED2_GPIO (GPIOC)
+#define LED_POLARITY LED_ON_LOW_LEVEL
+#else
+#error This board is not supported!
+#endif
+
+#endif

apps/demo_qspi/led_demo/src/led_demo.c

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "milliseconds_delay.h"
+#include "led_bsp.h"
+
+//! @brief Intialize necessary IPs.
+void hardware_init(void);
+//! @brief Toggle LEDs according to specified parameter leds.
+void led_toggle(uint32_t leds);
+
+int main(void)
+{
+    hardware_init();
+    milliseconds_delay_init();
+
+    uint32_t led_idx = LED0;
+    while (1)
+    {
+        led_toggle(led_idx);
+        milliseconds_delay(500);
+        led_toggle(led_idx);
+
+        led_idx <<= 1;
+        if (led_idx > MAX_LED_IDX)
+        {
+            led_idx = LED0;
+        }
+    }
+}
+
+void hardware_init(void)
+{
+#if defined(SIM_SCGC5_PORTA_MASK)
+    SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
+                   SIM_SCGC5_PORTE_MASK);
+#else
+    SIM->SCGC5 |=
+        (SIM_SCGC5_PTA_MASK | SIM_SCGC5_PTB_MASK | SIM_SCGC5_PTC_MASK | SIM_SCGC5_PTD_MASK | SIM_SCGC5_PTE_MASK);
+#endif
+
+    // Enable the LED pins GPIO
+    LED0_PORT->PCR[LED0_OFFSET] = PORT_PCR_MUX(1);
+    LED1_PORT->PCR[LED1_OFFSET] = PORT_PCR_MUX(1);
+#if MAX_LED_IDX == LED2
+    LED2_PORT->PCR[LED2_OFFSET] = PORT_PCR_MUX(1);
+#endif // #if MAX_LED_IDX == LED2
+
+    // Configure port to output mode
+    LED0_GPIO->PDDR |= (1 << LED0_OFFSET);
+    LED1_GPIO->PDDR |= (1 << LED1_OFFSET);
+#if MAX_LED_IDX == LED2
+    LED2_GPIO->PDDR |= (1 << LED2_OFFSET);
+#endif // #if MAX_LED_IDX == LED2
+
+// If led will be turned on with low level, need to turn all of them off at startup.
+#if LED_POLARITY == LED_ON_LOW_LEVEL
+    LED0_GPIO->PTOR |= (1 << LED0_OFFSET);
+    LED1_GPIO->PTOR |= (1 << LED1_OFFSET);
+#if MAX_LED_IDX == LED2
+    LED2_GPIO->PTOR |= (1 << LED2_OFFSET);
+#endif // #if MAX_LED_IDX == LED2
+#endif // #if LED_POLARITY == LED_ON_LOW_LEVEL
+}
+
+void led_toggle(uint32_t leds)
+{
+    if (leds & LED0)
+    {
+        LED0_GPIO->PTOR |= (1 << LED0_OFFSET);
+    }
+    if (leds & LED1)
+    {
+        LED1_GPIO->PTOR |= (1 << LED1_OFFSET);
+    }
+#if MAX_LED_IDX == LED2
+    if (leds & LED2)
+    {
+        LED2_GPIO->PTOR |= (1 << LED2_OFFSET);
+    }
+#endif // #if MAX_LED_IDX == LED2
+}

apps/demo_qspi/led_demo/src/led_demo_qspi.c

@@ -0,0 +1,359 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *
+ *
+ *
+ *          This demo shows a simple led blinking example, to re-enter Kinetis Bootloader,
+ *          hold SW2 about 2 seconds, then you can talk to Kinetis Bootloader via host tool again.
+ *
+ *
+ *
+ */
+
+#include "fsl_device_registers.h"
+#include "milliseconds_delay.h"
+#include "misc.h"
+#include "led_bsp.h"
+#include <stdbool.h>
+
+//! @brief Intialize necessary IPs.
+void hardware_init(void);
+//! @brief Toggle LEDs according to specified parameter leds.
+void led_toggle(uint32_t leds);
+
+//! @brief switch to PEE mode from FEE mode.
+//! In this function, the QuadSPI source clock is changed to MCGFLL,
+//! The QuadSPI serial clock divider is set to 1.
+//! The SystemCoreClock is updated to 120MHz, the MCG is swithced from FEE to PEE mode.
+#if defined(__ICCARM__)
+#pragma section = "ramfunc_section"
+#pragma section = "ramfunc_section_init"
+void clock_change(void) @"ramfunc_section";
+#elif defined(__CC_ARM)
+extern uint32_t Load$$EXEC_m_ramfunc$$Base[];   // Base address for loading ram function
+extern uint32_t Load$$EXEC_m_ramfunc$$Length[]; // Size of ram function
+extern uint32_t Image$$EXEC_m_ramfunc$$Base[];
+void clock_change(void) __attribute__((section("ramfunc_section"))); // Execute address of ram function
+#elif defined(__GNUC__)
+extern uint32_t ramfunc_load_address[];
+extern uint32_t ramfunc_length[];
+extern uint32_t ramfunc_execution_address[];
+void clock_change(void) __attribute__((section("ramfunc_section"))); // Execute address of ram function
+#endif
+
+// Copy ram functions from ROM to RAM.
+void copy_to_ram(void);
+
+int main(void)
+{
+    copy_to_ram();
+    clock_change();
+
+    hardware_init();
+    milliseconds_delay_init();
+
+    uint32_t led_idx = LED0;
+    while (1)
+    {
+        led_toggle(led_idx);
+        milliseconds_delay(500);
+        led_toggle(led_idx);
+
+        led_idx <<= 1;
+        if (led_idx > MAX_LED_IDX)
+        {
+            led_idx = LED0;
+        }
+
+        // Re-enter bootloader if the bootloader pin is clicked.
+        if (is_bootloader_pin_clicked())
+        {
+            app_enter_bootloader();
+        }
+    }
+}
+
+void hardware_init(void)
+{
+#if defined(SIM_SCGC5_PORTA_MASK)
+    SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
+                   SIM_SCGC5_PORTE_MASK);
+#else
+    SIM->SCGC5 |=
+        (SIM_SCGC5_PTA_MASK | SIM_SCGC5_PTB_MASK | SIM_SCGC5_PTC_MASK | SIM_SCGC5_PTD_MASK | SIM_SCGC5_PTE_MASK);
+#endif
+
+    // Enable the LED pins GPIO
+    LED0_PORT->PCR[LED0_OFFSET] = PORT_PCR_MUX(1);
+    LED1_PORT->PCR[LED1_OFFSET] = PORT_PCR_MUX(1);
+#if MAX_LED_IDX == LED2
+    LED2_PORT->PCR[LED2_OFFSET] = PORT_PCR_MUX(1);
+#endif // #if MAX_LED_IDX == LED2
+
+    // Configure port to output mode
+    LED0_GPIO->PDDR |= (1 << LED0_OFFSET);
+    LED1_GPIO->PDDR |= (1 << LED1_OFFSET);
+#if MAX_LED_IDX == LED2
+    LED2_GPIO->PDDR |= (1 << LED2_OFFSET);
+#endif // #if MAX_LED_IDX == LED2
+
+// If led will be turned on with low level, need to turn all of them off at startup.
+#if LED_POLARITY == LED_ON_LOW_LEVEL
+    LED0_GPIO->PTOR |= (1 << LED0_OFFSET);
+    LED1_GPIO->PTOR |= (1 << LED1_OFFSET);
+#if MAX_LED_IDX == LED2
+    LED2_GPIO->PTOR |= (1 << LED2_OFFSET);
+#endif // #if MAX_LED_IDX == LED2
+#endif // #if LED_POLARITY == LED_ON_LOW_LEVEL
+
+    bootloader_pin_init();
+}
+
+void led_toggle(uint32_t leds)
+{
+    if (leds & LED0)
+    {
+        LED0_GPIO->PTOR |= (1 << LED0_OFFSET);
+    }
+    if (leds & LED1)
+    {
+        LED1_GPIO->PTOR |= (1 << LED1_OFFSET);
+    }
+#if MAX_LED_IDX == LED2
+    if (leds & LED2)
+    {
+        LED2_GPIO->PTOR |= (1 << LED2_OFFSET);
+    }
+#endif // #if MAX_LED_IDX == LED2
+}
+
+void clock_change(void)
+{
+    __disable_irq(); // Disable global variable before changing the clock in case an interrupt is triggered during
+                     // change clock source.
+                     // Disable QuadSPI module, avoid glitch during clock switching.
+    QuadSPI0->MCR |= QuadSPI_MCR_MDIS_MASK;
+
+/*
+ * Configure CLKDIV1 first, in case some clock exceeds the maximum clock during clock switch.
+ */
+#if CPU_IS_ARM_CORTEX_M4
+    /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+    SIM->CLKDIV1 = 0x01140000U;
+#elif CPU_IS_ARM_CORTEX_M0P
+    /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=5,OUTDIV4=5,OUTDIV5=1 */
+    SIM->CLKDIV1 = 0x15051000U;
+#endif
+
+    // Restore to FEI mode before configuring external OSC.
+    MCG->C4 &= (uint8_t) ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK);
+    MCG->C1 |= MCG_C1_IREFS_MASK;
+    while ((MCG->S & MCG_S_IREFST_MASK) == 0x00U)
+    {
+    }
+
+/*
+ *  Switch to PEE mode, reuse almost the codes from SystemInit()
+ */
+/* SIM_SCGC5: PORTA=1 */
+#if defined(SIM_SCGC5_PORTA_MASK)
+    SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
+#else
+    SIM->SCGC5 |= SIM_SCGC5_PTA_MASK;
+#endif
+    /* Configure external OSC pinmux */
+    PORTA->PCR[18] &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+    PORTA->PCR[19] &= (uint32_t) ~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+    MCG->SC = 0;     /* Set SC (fast clock internal reference divider) */
+    MCG->C2 = 0x24U; /* Set C2 (freq. range, ext. and int. reference selection etc) */
+    // Delay about 50us to ensure the C2[RANGE] is updated correctly.
+    for (volatile uint32_t delayCnt = 0; delayCnt < 4800; delayCnt++)
+    {
+        __ASM("nop");
+    }
+    OSC->CR = 0x80U;                    /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+    MCG->C7 = 0;                        /* Set C7 (OSC Clock Select) */
+    MCG->C1 = 0x22 | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference
+                                           enable etc.) - PBE mode*/
+    while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U)
+    {
+    }
+
+    /* Set C4 (FLL output; trim values not changed) */
+    MCG->C4 &= (uint8_t) ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK);
+    /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+    MCG->C5 = 0x00U; /* Set C5 (PLL settings, PLL reference divider etc.) */
+#if CPU_IS_ARM_CORTEX_M4
+    /* OSC is 12MHz, PLL clock = 12 * 20 / 2 = 120MHz */
+    MCG->C6 = 0x44U & (uint8_t) ~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+#elif CPU_IS_ARM_CORTEX_M0P
+    /* OSC is 12MHz, PLL clock = 12 * 24 / 2 = 144MHz */
+    MCG->C6 = 0x48U & (uint8_t) ~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+#endif
+    MCG->C6 |= MCG_C6_PLLS_MASK;
+    while ((MCG->S & MCG_S_LOCK0_MASK) == 0x00U)
+    { /* Wait until PLL is locked*/
+    }
+    MCG->C1 &= (uint8_t) ~(MCG_C1_CLKS_MASK);
+
+    // Need to wait about 1ms until the MCGPLL is stable.
+    for (volatile uint32_t delayCnt = 0; delayCnt < 60000; delayCnt++)
+    {
+        __ASM("nop");
+    }
+
+    /*
+     *
+     * Now switch the QuadSPI Clock source and Configure the Clock divider
+     *
+     */
+    // If the serial clock divider is 1, need to change it to 2 because the maximum
+    // supported clock under SDK mode is 100MHz while QuadSPI source clock is 120MHz.
+    // For DDR mode, it is OK, because the actual serial clock is QuadSPI source clock / 4.
+    uint32_t sclkcfg = (QuadSPI0->MCR & QuadSPI_MCR_SCLKCFG_MASK) >> QuadSPI_MCR_SCLKCFG_SHIFT;
+    if (sclkcfg == 0U)
+    {
+        uint32_t tmp = QuadSPI0->MCR;
+        tmp &= (uint32_t)~QuadSPI_MCR_SCLKCFG_MASK;
+        tmp |= QuadSPI_MCR_SCLKCFG(1);
+        QuadSPI0->MCR = tmp;
+    }
+    uint32_t tmp = QuadSPI0->SOCCR;
+    tmp &= (uint32_t)~QuadSPI_SOCCR_QSPISRC_MASK;
+    tmp |= QuadSPI_SOCCR_QSPISRC(2);
+    QuadSPI0->SOCCR = tmp; // Change QuadSPI source clock to MCGPLL
+
+    // Cleare AHB buffer after switching clock source.
+    QuadSPI0->MCR &= (uint32_t)~QuadSPI_MCR_MDIS_MASK; // Re-enable QuadSPI module
+    // Clear AHB buffer first here to avoid potential timing issue
+    QuadSPI0->MCR |= QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK;
+    // Wait ~10ms to ensure the AHB buffer is cleared.
+    for (volatile uint32_t delayCnt = 0; delayCnt < 960; delayCnt++)
+    {
+        __ASM("nop");
+    }
+    // Disable module during the reset procedure
+    QuadSPI0->MCR |= QuadSPI_MCR_MDIS_MASK;
+    // Clear the reset bits.
+    QuadSPI0->MCR &= (uint32_t) ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
+    QuadSPI0->MCR &= (uint32_t)~QuadSPI_MCR_MDIS_MASK; // Re-enable QuadSPI module
+
+    __DSB();
+    __ISB();
+
+    // Enable global IRQ because the clock switch is complete.
+    __enable_irq();
+
+#if CPU_IS_ARM_CORTEX_M4
+    SystemCoreClock = 120000000ul; // SystemCoreClock is 120MHz now.
+#elif CPU_IS_ARM_CORTEX_M0P
+    SystemCoreClock = 72000000ul;                    // SystemCoreClock is 72MHz now.
+#endif
+}
+
+void copy_to_ram(void)
+{
+    uint8_t *codeRelocateRomStart;
+    uint32_t codeRelocateSize;
+    uint8_t *codeReloocateRamStart;
+#if defined(__ICCARM__)
+    codeRelocateRomStart = (uint8_t *)__section_begin("ramfunc_section_init");
+    codeRelocateSize = (uint32_t)__section_size("ramfunc_section_init");
+    codeReloocateRamStart = (uint8_t *)__section_begin("ramfunc_section");
+#elif defined(__CC_ARM)
+    codeRelocateRomStart = (uint8_t *)Load$$EXEC_m_ramfunc$$Base;
+    codeRelocateSize = (uint32_t)Load$$EXEC_m_ramfunc$$Length;
+    codeReloocateRamStart = (uint8_t *)Image$$EXEC_m_ramfunc$$Base;
+#elif defined(__GNUC__)
+    codeRelocateRomStart = (uint8_t *)ramfunc_load_address;
+    codeRelocateSize = (uint32_t)ramfunc_length;
+    codeReloocateRamStart = (uint8_t *)ramfunc_execution_address;
+#endif
+
+    while (codeRelocateSize)
+    {
+        *codeReloocateRamStart++ = *codeRelocateRomStart++;
+        codeRelocateSize--;
+    }
+}
+
+//! @brief Init bootloader pin
+void bootloader_pin_init(void)
+{
+    // Configure Enter Kinetis Bootloader pin (SW2-PTA4)
+    PORTA->PCR[4] = PORT_PCR_MUX(1);     // Configure PTA21 to GPIO mode
+    GPIOA->PDDR &= (uint32_t) ~(1 << 4); // Configure SW1 to input mode
+}
+
+//! @brief determine whether boot pin is asserted
+bool is_bootloader_pin_clicked(void)
+{
+    static uint32_t count = 0;
+    static bool isPinAsserted = false;
+    static bool isPinReleased = false;
+    if (!isPinAsserted)
+    {
+        if (!(GPIOA->PDIR & (1 << 4)))
+        {
+            count++;
+        }
+        else
+        {
+            count = 0;
+        }
+
+        if (count == 2)
+        {
+            isPinAsserted = true;
+            count = 0;
+        }
+    }
+    else
+    {
+        if (GPIOA->PDIR & (1 << 4))
+        {
+            count++;
+        }
+        else
+        {
+            count = 0;
+        }
+
+        if (count == 2)
+        {
+            isPinReleased = true;
+            count = 0;
+        }
+    }
+
+    return (isPinAsserted && isPinReleased);
+}

apps/demo_qspi/led_demo/src/milliseconds_delay.c

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "milliseconds_delay.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+static volatile uint32_t s_milliseconds_left = 0;
+
+static inline uint32_t milliseconds_left_get(void)
+{
+    return s_milliseconds_left;
+}
+
+static inline void milliseconds_left_set(uint32_t ms)
+{
+    s_milliseconds_left = ms;
+}
+
+static inline void milliseconds_left_decrement(void)
+{
+    --s_milliseconds_left;
+}
+
+void milliseconds_delay_init(void)
+{
+    SysTick_Config(SystemCoreClock / 1000);
+}
+
+void milliseconds_delay(uint32_t ms)
+{
+    milliseconds_left_set(ms);
+    while (milliseconds_left_get())
+    {
+    }
+}
+
+void SysTick_Handler(void)
+{
+    if (milliseconds_left_get())
+    {
+        milliseconds_left_decrement();
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

apps/demo_qspi/led_demo/src/milliseconds_delay.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MILLISECONDS_DELAY_H__
+#define __MILLISECONDS_DELAY_H__
+
+#include <stdint.h>
+
+extern void milliseconds_delay_init(void);
+extern void milliseconds_delay(uint32_t ms);
+
+#endif

apps/demo_qspi/led_demo/src/misc.c

@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_device_registers.h"
+
+//! @brief Type used for all status and error return values.
+typedef int32_t status_t;
+
+//! @brief Enumeration for supported flash margin levels.
+typedef enum _flash_margin_value
+{
+    kFlashMargin_Normal,
+    kFlashMargin_User,
+    kFlashMargin_Factory,
+
+    // Not real margin level, Used to determine the range of valid margin level.
+    kFlashMargin_Invalid
+} flash_margin_value_t;
+
+//! @brief Enumeration for the three possible flash security states.
+typedef enum _flash_security_state
+{
+    kFlashNotSecure,
+    kFlashSecureBackdoorEnabled,
+    kFlashSecureBackdoorDisabled
+} flash_security_state_t;
+
+//! @brief Enumeration for the three possible flash protection levels.
+typedef enum _flash_protection_state
+{
+    kFlashProtection_Unprotected,
+    kFlashProtection_Protected,
+    kFlashProtection_Mixed
+} flash_protection_state_t;
+
+//! @brief Enumeration for the three possible flash execute access levels.
+typedef enum _flash_execute_only_access_state
+{
+    kFlashAccess_UnLimited,
+    kFlashAccess_ExecuteOnly,
+    kFlashAccess_Mixed
+} flash_execute_only_access_state_t;
+
+//! @brief Enumeration for various flash properties.
+typedef enum _flash_property
+{
+    kFlashProperty_SectorSize = 0,
+    kFlashProperty_TotalFlashSize = 1,
+    kFlashProperty_BlockCount = 3,
+    kFlashProperty_FlashBlockBaseAddr,
+    kFlashProperty_FlashFacSupport,
+    kFlashProperty_FlashAccessSegmentSize,
+    kFlashProperty_FlashAccessSegmentCount,
+    kFlashProperty_Version,
+} flash_property_t;
+
+//! @brief callback type used for pflash block
+typedef void (*flash_callback_t)(void);
+
+//! @brief Flash driver state information.
+//!
+//! An instance of this structure is allocated by the user of the flash driver and
+//! passed into each of the driver APIs.
+typedef struct _flash_driver
+{
+    uint32_t PFlashBlockBase;          //!< Base address of the first PFlash block
+    uint32_t PFlashTotalSize;          //!< Size of all combined PFlash block.
+    uint32_t PFlashBlockCount;         //!< Number of PFlash blocks.
+    uint32_t PFlashSectorSize;         //!< Size in bytes of a sector of PFlash.
+    flash_callback_t PFlashCallback;   //!< Callback function for flash API.
+    uint32_t PFlashAccessSegmentSize;  //!< Size in bytes of a access segment of PFlash.
+    uint32_t PFlashAccessSegmentCount; //!< Number of PFlash access segments.
+} flash_driver_t;
+
+/*!
+* @brief Enumeration for the two possible options of flash read resource command.
+*/
+typedef enum _flash_read_resource_option
+{
+    kFlashResource_ProgramIFR = 0,
+    kFlashResource_VersionID = 1
+} flash_read_resource_option_t;
+
+//! @brief Interface for the flash driver.
+typedef struct FlashDriverInterface
+{
+    uint32_t version; //!< flash driver API version number.
+    status_t (*flash_init)(flash_driver_t *driver);
+    status_t (*flash_erase_all)(flash_driver_t *driver, uint32_t key);
+    status_t (*flash_erase_all_unsecure)(flash_driver_t *driver, uint32_t key);
+    status_t (*flash_erase)(flash_driver_t *driver, uint32_t start, uint32_t lengthInBytes, uint32_t key);
+    status_t (*flash_program)(flash_driver_t *driver, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
+    status_t (*flash_get_security_state)(flash_driver_t *driver, flash_security_state_t *state);
+    status_t (*flash_security_bypass)(flash_driver_t *driver, const uint8_t *backdoorKey);
+    status_t (*flash_verify_erase_all)(flash_driver_t *driver, flash_margin_value_t margin);
+    status_t (*flash_verify_erase)(flash_driver_t *driver,
+                                   uint32_t start,
+                                   uint32_t lengthInBytes,
+                                   flash_margin_value_t margin);
+    status_t (*flash_verify_program)(flash_driver_t *driver,
+                                     uint32_t start,
+                                     uint32_t lengthInBytes,
+                                     const uint8_t *expectedData,
+                                     flash_margin_value_t margin,
+                                     uint32_t *failedAddress,
+                                     uint32_t *failedData);
+    status_t (*flash_get_property)(flash_driver_t *driver, flash_property_t whichProperty, uint32_t *value);
+    status_t (*flash_register_callback)(flash_driver_t *driver, flash_callback_t callback);
+    status_t (*flash_program_once)(flash_driver_t *driver, uint32_t index, uint32_t *src, uint32_t lengthInBytes);
+    status_t (*flash_read_once)(flash_driver_t *driver, uint32_t index, uint32_t *dst, uint32_t lengthInBytes);
+    status_t (*flash_read_resource)(flash_driver_t *driver,
+                                    uint32_t start,
+                                    uint32_t *dst,
+                                    uint32_t lengthInBytes,
+                                    flash_read_resource_option_t option);
+} flash_driver_interface_t;
+
+//! @brief Interface for AES 128 functions
+typedef struct AesDriverInterface
+{
+    void (*aes_init)(uint32_t *key);
+    void (*aes_encrypt)(uint32_t *in, uint32_t *key, uint32_t *out);
+    void (*aes_decrypt)(uint32_t *in, uint32_t *key, uint32_t *out);
+} aes_driver_interface_t;
+
+typedef struct BootloaderTree
+{
+    void (*runBootloader)(void *arg); //!< Function to start the bootloader executing.
+    uint32_t version;                 //!< Bootloader version number.
+    const char *copyright;            //!< Copyright string.
+    const uint32_t *reserved;
+    const flash_driver_interface_t *flashDriver; //!< Flash driver API.
+    const aes_driver_interface_t *aesDriver;     //!< AES driver API.
+} bootloader_tree_t;
+
+#define BOOTLOADER_TREE_ROOT (0x1c00001cul)
+enum
+{
+    kFlashEraseKey = 0x6B65666BUL,
+#ifndef BL_TARGET_FLASH
+    kApplicationBase = 0x0000,
+#else
+    kApplicationBase = 0xa000,
+#endif
+};
+
+// See misc.h for more details.
+void app_enter_bootloader(void)
+{
+    // Disable IRQ first
+    __disable_irq();
+
+    // Get Kinetis Bootloader Tree pointer.
+    const bootloader_tree_t *bootloaderTree = *(const bootloader_tree_t **)BOOTLOADER_TREE_ROOT;
+    // Initialize Flash Driver
+    flash_driver_t flashInstance;
+    uint32_t status = bootloaderTree->flashDriver->flash_init(&flashInstance);
+    if (status != 0)
+    {
+        // Handle error code here
+    }
+    // Save the flash config field before erase
+    uint32_t flashConfigField[4];
+    const uint32_t *flashConfigFieldStart = (const uint32_t *)(kApplicationBase + 0x400);
+    for (uint32_t i = 0; i < sizeof(flashConfigField) / sizeof(flashConfigField[0]); i++)
+    {
+        flashConfigField[i] = *flashConfigFieldStart++;
+    }
+    // Erase the first sector.
+    status = bootloaderTree->flashDriver->flash_erase(&flashInstance, kApplicationBase, 0x800, kFlashEraseKey);
+    if (status != 0)
+    {
+        // Handle error code here
+    }
+    // Write the flash config field back.
+    status = bootloaderTree->flashDriver->flash_program(&flashInstance, kApplicationBase + 0x400, flashConfigField,
+                                                        sizeof(flashConfigField));
+    if (status != 0)
+    {
+        // Handle error code here
+    }
+
+// Enter Kinetis Bootloader
+#ifndef BL_TARGET_FLASH
+    bootloaderTree->runBootloader(0);
+#else
+    NVIC_SystemReset();
+#endif
+}

apps/demo_qspi/led_demo/src/misc.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdbool.h>
+
+//! @brief Enter bootloader from user application.
+void app_enter_bootloader(void);
+
+//! @brief Init bootloader pin
+void bootloader_pin_init(void);
+
+//! @brief determine whether boot pin is asserted
+bool is_bootloader_pin_clicked(void);

apps/demo_qspi/led_demo/targets/FRDM-K82F/iar/binaries/boot_to_qspi_alias_memory_rom.srec

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apps/demo_qspi/led_demo/targets/FRDM-K82F/iar/binaries/led_demo_pflash_0000.srec

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apps/demo_qspi/led_demo/targets/FRDM-K82F/iar/binaries/led_demo_qspi_0000.srec

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