fpga_clock_registers.h
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
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#if !defined(__FPGA_CLOCK_REGISTERS_H__)
#define __FPGA_CLOCK_REGISTERS_H__
#define CY22393_ADDR 0x69
// REG
#define CY22393_REG_CLKA_DIVIDE (0x08) // divsel:0
#define CY22393_REG_CLKB_DIVIDE (0x0A) // divsel:0
#define CY22393_REG_CLKC_DIVIDE (0x0C) // CLKC
#define CY22393_REG_CLKD_DIVIDE (0x0D) // CLKD
#define CY22393_REG_SOURCE 0x0E
#define CY22393_REG_AC 0x0F
#define CY22393_REG_DC 0x10
#define CY22393_REG_CLKA_DIV 0x08
#define CY22393_REG_PLL3Q 0x14
#define CY22393_REG_PLL3P 0x15
#define CY22393_REG_PLL3E 0x16
// This is the low register value of the lower bank
#define CY22393_REG_LOW 0x08
// This is the high register value of the high bank
#define CY22393_REG_HIGH 0x17
#define CY22393_AC 0x55
#define CY22393_DC 0x55
#define CY22393_DIVIDE_OFF 0 // close clk ouput
// Maximum post div value when using VCO frequency above 333 MHZ
#define CY22393_POSTDIV_MAX_VAL 31
// Reference clock to cypress chip
#define CY22393_REF_CLK 24000000
// This is the minimum value that Reference divided by Q can be equal to
#define CY22393_MIN_REF_DIV_Q 250000
// Max clock frequency the chip supports, for CY22393 it is 200Mhz
#define CY22393_MAX_OUTPUT_CLK 200000000
// Max VCO clock frequency the chip supports, for CY22393 it is 375Mhz
#define CY22393_MAX_VCO_CLK 375000000
#endif // __FPGA_CLOCK_REGISTERS_H__