fsl_port.h
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_PORT_H_
#define _FSL_PORT_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
enum _port_pull
{
kPORT_PullDisable = 0U,
kPORT_PullDown = 2U,
kPORT_PullUp = 3U,
};
enum _port_slew_rate
{
kPORT_FastSlewRate = 0U,
kPORT_SlowSlewRate = 1U,
};
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
enum _port_open_drain_enable
{
kPORT_OpenDrainDisable = 0U,
kPORT_OpenDrainEnable = 1U,
};
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
enum _port_passive_filter_enable
{
kPORT_PassiveFilterDisable = 0U,
kPORT_PassiveFilterEnable = 1U,
};
enum _port_drive_strength
{
kPORT_LowDriveStrength = 0U,
kPORT_HighDriveStrength = 1U,
};
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
enum _port_lock_register
{
kPORT_UnLockRegister = 0U,
kPORT_LockRegister = 1U,
};
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
typedef enum _port_mux
{
kPORT_PinDisabledOrAnalog = 0U,
kPORT_MuxAsGpio = 1U,
kPORT_MuxAlt2 = 2U,
kPORT_MuxAlt3 = 3U,
kPORT_MuxAlt4 = 4U,
kPORT_MuxAlt5 = 5U,
kPORT_MuxAlt6 = 6U,
kPORT_MuxAlt7 = 7U,
} port_mux_t;
typedef enum _port_interrupt
{
kPORT_InterruptOrDMADisabled = 0x0U,
#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
kPORT_DmaRisingEdge = 0x1U,
kPORT_DmaFallingEdge = 0x2U,
kPORT_DmaEitherEdge = 0x3U,
#endif
kPORT_InterruptLogicZero = 0x8U,
kPORT_InterruptRisingEdge = 0x9U,
kPORT_InterruptFallingEdge = 0xAU,
kPORT_InterruptEitherEdge = 0xBU,
kPORT_InterruptLogicOne = 0xCU,
kPORT_ActiveHighTriggerOutputEnable = 0xDU,
kPORT_ActiveLowTriggerOutputEnable = 0xEU,
} port_interrupt_t;
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
typedef enum _port_digital_filter_clock_source
{
kPORT_BusClock = 0U,
kPORT_LpoClock = 1U,
} port_digital_filter_clock_source_t;
typedef struct _port_digital_filter_config
{
uint32_t digitalFilterWidth;
port_digital_filter_clock_source_t clockSource;
} port_digital_filter_config_t;
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
typedef struct _port_pin_config
{
uint16_t pullSelect : 2;
uint16_t slewRate : 1;
uint16_t : 1;
uint16_t passiveFilterEnable : 1;
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
uint16_t openDrainEnable : 1;
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
uint16_t driveStrength : 1;
uint16_t : 1;
uint16_t mux : 3;
uint16_t : 4;
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
uint16_t lockRegister : 1;
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
} port_pin_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
{
assert(config);
uint32_t addr = (uint32_t)&base->PCR[pin];
*(volatile uint16_t *)(addr) = *((const uint16_t *)config);
}
static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
{
assert(config);
uint16_t PCRL = *((const uint16_t *)config);
if (mask & 0xffffU)
{
base->GPCLR = (mask & 0xffffU) | PCRL;
}
if (mask >> 16)
{
base->GPCHR = (mask >> 16) | PCRL;
}
}
static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
{
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
}
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
{
if (enable == true)
{
base->DFER |= mask;
}
else
{
base->DFER &= ~mask;
}
}
static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
{
assert(config);
base->DFCR = PORT_DFCR_CS(config->clockSource);
base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
}
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, const port_interrupt_t config)
{
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
}
static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
{
return base->ISFR;
}
static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
{
base->ISFR = mask;
}
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_PORT_H_ */
PORT_EnablePinsDigitalFilter
static void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
Enables the digital filter in one port. Each bit of the 32-bit register represents one pin...
Definition: fsl_port.h:272
kPORT_SlowSlewRate
Definition: fsl_port.h:59
kPORT_LpoClock
Definition: fsl_port.h:130
kPORT_MuxAlt2
Definition: fsl_port.h:99
kPORT_PassiveFilterDisable
Definition: fsl_port.h:74
kPORT_OpenDrainEnable
Definition: fsl_port.h:67
PORT_SetPinConfig
static void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
Sets the port PCR register.
Definition: fsl_port.h:196
kPORT_MuxAlt4
Definition: fsl_port.h:101
kPORT_UnLockRegister
Definition: fsl_port.h:89
port_digital_filter_clock_source_t
port_digital_filter_clock_source_t
Digital filter clock source selection.
Definition: fsl_port.h:127
_port_open_drain_enable
_port_open_drain_enable
Internal resistor pull feature enable/disable.
Definition: fsl_port.h:64
kPORT_OpenDrainDisable
Definition: fsl_port.h:66
PORT_SetMultiplePinsConfig
static void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
Sets the port PCR register.
Definition: fsl_port.h:228
kPORT_PassiveFilterEnable
Definition: fsl_port.h:75
PORT_GetPinsInterruptFlags
static uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
Reads the whole port status flag.
Definition: fsl_port.h:342
kPORT_InterruptOrDMADisabled
Definition: fsl_port.h:110
kPORT_BusClock
Definition: fsl_port.h:129
kPORT_DmaRisingEdge
Definition: fsl_port.h:112
kPORT_InterruptFallingEdge
Definition: fsl_port.h:118
kPORT_HighDriveStrength
Definition: fsl_port.h:82
kPORT_DmaFallingEdge
Definition: fsl_port.h:113
PORT_SetPinMux
static void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
Configures the pin muxing.
Definition: fsl_port.h:259
kPORT_FastSlewRate
Definition: fsl_port.h:58
_port_passive_filter_enable
_port_passive_filter_enable
Passive filter feature enable/disable.
Definition: fsl_port.h:72
kPORT_LowDriveStrength
Definition: fsl_port.h:81
port_digital_filter_config_t::clockSource
port_digital_filter_clock_source_t clockSource
Definition: fsl_port.h:137
PORT_SetDigitalFilterConfig
static void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
set the digital filter in one port. Each bit of the 32-bit register represents one pin...
Definition: fsl_port.h:291
kPORT_ActiveHighTriggerOutputEnable
Definition: fsl_port.h:121
kPORT_InterruptLogicOne
Definition: fsl_port.h:120
port_digital_filter_config_t::digitalFilterWidth
uint32_t digitalFilterWidth
Definition: fsl_port.h:136
PORT_ClearPinsInterruptFlags
static void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
Clears the multiple pins&#39; interrupt status flag.
Definition: fsl_port.h:352
_port_pull
_port_pull
Internal resistor pull feature selection.
Definition: fsl_port.h:48
kPORT_PullUp
Definition: fsl_port.h:52
kPORT_DmaEitherEdge
Definition: fsl_port.h:114
port_digital_filter_config_t
PORT digital filter feature configuration definition.
Definition: fsl_port.h:134
kPORT_MuxAlt5
Definition: fsl_port.h:102
PORT_SetPinInterruptConfig
static void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, const port_interrupt_t config)
Configures the port pin interrupt/DMA request.
Definition: fsl_port.h:324
kPORT_MuxAlt6
Definition: fsl_port.h:103
kPORT_InterruptEitherEdge
Definition: fsl_port.h:119
kPORT_MuxAlt3
Definition: fsl_port.h:100
kPORT_PullDisable
Definition: fsl_port.h:50
port_pin_config_t
PORT pin config structure.
Definition: fsl_port.h:142
port_mux_t
port_mux_t
Pin mux selection.
Definition: fsl_port.h:95
kPORT_LockRegister
Definition: fsl_port.h:90
kPORT_MuxAsGpio
Definition: fsl_port.h:98
kPORT_PinDisabledOrAnalog
Definition: fsl_port.h:97
port_interrupt_t
port_interrupt_t
Configures the interrupt generation condition.
Definition: fsl_port.h:108
kPORT_ActiveLowTriggerOutputEnable
Definition: fsl_port.h:122
kPORT_InterruptLogicZero
Definition: fsl_port.h:116
kPORT_InterruptRisingEdge
Definition: fsl_port.h:117
kPORT_MuxAlt7
Definition: fsl_port.h:104
_port_drive_strength
_port_drive_strength
Configures the drive strength.
Definition: fsl_port.h:79
_port_slew_rate
_port_slew_rate
Slew rate selection.
Definition: fsl_port.h:56
kPORT_PullDown
Definition: fsl_port.h:51
_port_lock_register
_port_lock_register
unlock/lock the pin control register field[15:0]
Definition: fsl_port.h:87