fsl_spi.h
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used tom endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_SPI_H_
#define _FSL_SPI_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
#define SPI_DUMMYDATA (0xFFU)
enum _spi_status
{
kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_SPI, 0),
kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_SPI, 1),
kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_SPI, 2)
};
typedef enum _spi_clock_polarity
{
kSPI_ClockPolarityActiveHigh = 0x0U,
kSPI_ClockPolarityActiveLow
} spi_clock_polarity_t;
typedef enum _spi_clock_phase
{
kSPI_ClockPhaseFirstEdge = 0x0U,
kSPI_ClockPhaseSecondEdge
} spi_clock_phase_t;
typedef enum _spi_shift_direction
{
kSPI_MsbFirst = 0x0U,
kSPI_LsbFirst
} spi_shift_direction_t;
typedef enum _spi_ss_output_mode
{
kSPI_SlaveSelectAsGpio = 0x0U,
kSPI_SlaveSelectFaultInput = 0x2U,
kSPI_SlaveSelectAutomaticOutput = 0x3U
} spi_ss_output_mode_t;
typedef enum _spi_pin_mode
{
kSPI_PinModeNormal = 0x0U,
kSPI_PinModeInput = 0x1U,
kSPI_PinModeOutput = 0x3U
} spi_pin_mode_t;
typedef enum _spi_data_bitcount_mode
{
kSPI_8BitMode = 0x0U,
kSPI_16BitMode
} spi_data_bitcount_mode_t;
enum _spi_interrupt_enable
{
kSPI_RxFullAndModfInterruptEnable = 0x1U,
kSPI_TxEmptyInterruptEnable = 0x2U,
kSPI_MatchInterruptEnable = 0x4U,
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kSPI_RxFifoNearFullInterruptEnable = 0x8U,
kSPI_TxFifoNearEmptyInterruptEnable = 0x10U,
#endif /* FSL_FEATURE_SPI_HAS_FIFO */
};
enum _spi_flags
{
kSPI_RxBufferFullFlag = SPI_S_SPRF_MASK,
kSPI_MatchFlag = SPI_S_SPMF_MASK,
kSPI_TxBufferEmptyFlag = SPI_S_SPTEF_MASK,
kSPI_ModeFaultFlag = SPI_S_MODF_MASK,
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kSPI_RxFifoNearFullFlag = SPI_S_RNFULLF_MASK,
kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK,
kSPI_RxFifoFullFlag = SPI_S_TXFULLF_MASK,
kSPI_TxFifoEmptyFlag = SPI_S_RFIFOEF_MASK,
kSPI_TxFifoError = SPI_CI_TXFERR_MASK << 8U,
kSPI_RxFifoError = SPI_CI_RXFERR_MASK << 8U,
kSPI_TxOverflow = SPI_CI_TXFOF_MASK << 8U,
kSPI_RxOverflow = SPI_CI_RXFOF_MASK << 8U
#endif /* FSL_FEATURE_SPI_HAS_FIFO */
};
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
typedef enum _spi_w1c_interrupt
{
kSPI_RxFifoFullClearInterrupt = SPI_CI_SPRFCI_MASK,
kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK,
kSPI_RxNearFullClearInterrupt = SPI_CI_RNFULLFCI_MASK,
kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK
} spi_w1c_interrupt_t;
typedef enum _spi_txfifo_watermark
{
kSPI_TxFifoOneFourthEmpty = 0,
kSPI_TxFifoOneHalfEmpty = 1
} spi_txfifo_watermark_t;
typedef enum _spi_rxfifo_watermark
{
kSPI_RxFifoThreeFourthsFull = 0,
kSPI_RxFifoOneHalfFull = 1
} spi_rxfifo_watermark_t;
#endif /* FSL_FEATURE_SPI_HAS_FIFO */
#if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
enum _spi_dma_enable_t
{
kSPI_TxDmaEnable = SPI_C2_TXDMAE_MASK,
kSPI_RxDmaEnable = SPI_C2_RXDMAE_MASK,
kSPI_DmaAllEnable = (SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK)
};
#endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
typedef struct _spi_master_config
{
bool enableMaster;
bool enableStopInWaitMode;
spi_clock_polarity_t polarity;
spi_clock_phase_t phase;
spi_shift_direction_t direction;
#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
spi_data_bitcount_mode_t dataMode;
#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
bool enableFifoInterruptClear;
spi_txfifo_watermark_t txWatermark;
spi_rxfifo_watermark_t rxWatermark;
#endif /* FSL_FEATURE_SPI_HAS_FIFO */
spi_ss_output_mode_t outputMode;
spi_pin_mode_t pinMode;
uint32_t baudRate_Bps;
} spi_master_config_t;
typedef struct _spi_slave_config
{
bool enableSlave;
bool enableStopInWaitMode;
spi_clock_polarity_t polarity;
spi_clock_phase_t phase;
spi_shift_direction_t direction;
#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
spi_data_bitcount_mode_t dataMode;
#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
bool enableFifoInterruptClear;
spi_txfifo_watermark_t txWatermark;
spi_rxfifo_watermark_t rxWatermark;
#endif /* FSL_FEATURE_SPI_HAS_FIFO */
} spi_slave_config_t;
typedef struct _spi_transfer
{
uint8_t *txData;
uint8_t *rxData;
size_t dataSize;
uint32_t flags;
} spi_transfer_t;
typedef struct _spi_master_handle spi_master_handle_t;
typedef spi_master_handle_t spi_slave_handle_t;
typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
struct _spi_master_handle
{
uint8_t *volatile txData;
uint8_t *volatile rxData;
volatile size_t txRemainingBytes;
volatile size_t rxRemainingBytes;
volatile uint32_t state;
size_t transferSize;
uint8_t bytePerFrame;
uint8_t watermark;
spi_master_callback_t callback;
void *userData;
};
#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
* APIs
******************************************************************************/
void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
void SPI_Deinit(SPI_Type *base);
static inline void SPI_Enable(I2C_Type *base, bool enable)
{
if (enable)
{
base->C1 |= SPI_C1_SPE_MASK;
}
else
{
base->C1 &= ~SPI_C1_SPE_MASK;
}
}
uint32_t SPI_GetStatusFlags(SPI_Type *base);
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
static inline void SPI_ClearInterrupt(SPI_Type *base, uint32_t mask)
{
base->CI |= mask;
}
#endif /* FSL_FEATURE_SPI_HAS_FIFO */
void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask);
#if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
static inline void SPI_EnableDMA(SPI_Type *base, uint32_t mask, bool enable)
{
if (enable)
{
base->C2 |= mask;
}
else
{
base->C2 &= ~mask;
}
}
#endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
static inline uint32_t SPI_GetDataRegisterAddress(SPI_Type *base)
{
#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
return (uint32_t)(&(base->DL));
#else
return (uint32_t)(&(base->D));
#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
}
void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
static inline void SPI_SetMatchData(SPI_Type *base, uint32_t matchData)
{
#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
base->ML = matchData & 0xFFU;
base->MH = (matchData >> 8U) & 0xFFU;
#else
base->M = matchData;
#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
}
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
void SPI_EnableFIFO(SPI_Type *base, bool enable);
#endif
void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size);
void SPI_WriteData(SPI_Type *base, uint16_t data);
uint16_t SPI_ReadData(SPI_Type *base);
void SPI_MasterTransferCreateHandle(SPI_Type *base,
spi_master_handle_t *handle,
spi_master_callback_t callback,
void *userData);
status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
static inline void SPI_SlaveTransferCreateHandle(SPI_Type *base,
spi_slave_handle_t *handle,
spi_slave_callback_t callback,
void *userData)
{
SPI_MasterTransferCreateHandle(base, handle, callback, userData);
}
static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
{
return SPI_MasterTransferNonBlocking(base, handle, xfer);
}
static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
{
return SPI_MasterTransferGetCount(base, handle, count);
}
static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
{
SPI_MasterTransferAbort(base, handle);
}
static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
{
SPI_MasterTransferHandleIRQ(base, handle);
}
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_SPI_H_*/
spi_slave_config_t::enableSlave
bool enableSlave
Definition: fsl_spi.h:195
_spi_interrupt_enable
_spi_interrupt_enable
SPI interrupt sources.
Definition: fsl_spi.h:106
spi_master_config_t::enableMaster
bool enableMaster
Definition: fsl_spi.h:174
SPI_WriteBlocking
void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size)
Sends a buffer of data bytes in blocking way.
Definition: fsl_spi.c:536
SPI_SlaveTransferGetCount
static status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
Get the bytes of SPI Interrupt transferred.
Definition: fsl_spi.h:667
SPI_ReadData
uint16_t SPI_ReadData(SPI_Type *base)
Get a data from SPI data register.
Definition: fsl_spi.c:584
spi_master_config_t::txWatermark
spi_txfifo_watermark_t txWatermark
Definition: fsl_spi.h:184
_spi_flags
_spi_flags
SPI status flags.
Definition: fsl_spi.h:118
kSPI_TxFifoError
Definition: fsl_spi.h:129
SPI_WriteData
void SPI_WriteData(SPI_Type *base, uint16_t data)
Write a data into SPI data register.
Definition: fsl_spi.c:574
spi_txfifo_watermark_t
spi_txfifo_watermark_t
SPI TX FIFO watermark settings.
Definition: fsl_spi.h:147
spi_clock_phase_t
spi_clock_phase_t
SPI clock phase configuration.
Definition: fsl_spi.h:65
SPI_MasterTransferCreateHandle
void SPI_MasterTransferCreateHandle(SPI_Type *base, spi_master_handle_t *handle, spi_master_callback_t callback, void *userData)
Initialize the SPI master handle.
Definition: fsl_spi.c:658
kSPI_TxFifoOneHalfEmpty
Definition: fsl_spi.h:150
spi_slave_handle_t
spi_master_handle_t spi_slave_handle_t
Slave handle is the same with master handle.
Definition: fsl_spi.h:222
_spi_dma_enable_t
_spi_dma_enable_t
SPI dma source.
Definition: fsl_spi.h:163
kSPI_TxFifoNearEmptyInterruptEnable
Definition: fsl_spi.h:113
kStatus_SPI_Error
Definition: fsl_spi.h:54
SPI_Deinit
void SPI_Deinit(SPI_Type *base)
De-initialize SPI.
Definition: fsl_spi.c:381
kSPI_RxFifoNearFullFlag
Definition: fsl_spi.h:125
SPI_MasterTransferNonBlocking
status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer)
Performs a non-blocking SPI interrupt transfer.
Definition: fsl_spi.c:707
kSPI_TxFifoOneFourthEmpty
Definition: fsl_spi.h:149
kSPI_TxNearEmptyClearInterrupt
Definition: fsl_spi.h:143
kSPI_MatchFlag
Definition: fsl_spi.h:121
spi_transfer_t
SPI transfer structure.
Definition: fsl_spi.h:211
kSPI_ClockPhaseFirstEdge
Definition: fsl_spi.h:67
_spi_master_handle::rxData
uint8_t *volatile rxData
Definition: fsl_spi.h:234
kSPI_ClockPolarityActiveLow
Definition: fsl_spi.h:61
kSPI_16BitMode
Definition: fsl_spi.h:102
kSPI_DmaAllEnable
Definition: fsl_spi.h:167
_spi_master_handle::bytePerFrame
uint8_t bytePerFrame
Definition: fsl_spi.h:239
kSPI_8BitMode
Definition: fsl_spi.h:101
SPI_DisableInterrupts
void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
Disable interrupt for SPI.
Definition: fsl_spi.c:445
spi_master_config_t::phase
spi_clock_phase_t phase
Definition: fsl_spi.h:177
_spi_master_handle::watermark
uint8_t watermark
Definition: fsl_spi.h:240
spi_transfer_t::txData
uint8_t * txData
Definition: fsl_spi.h:213
SPI_MasterInit
void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz)
Initialize SPI with master configuration.
Definition: fsl_spi.c:287
spi_w1c_interrupt_t
spi_w1c_interrupt_t
SPI FIFO write-1-to-clear interrupt flags.
Definition: fsl_spi.h:138
SPI_SlaveTransferHandleIRQ
static void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
Interrupt handler for SPI slave.
Definition: fsl_spi.h:689
kSPI_TxFifoNearEmptyFlag
Definition: fsl_spi.h:126
kSPI_TxOverflow
Definition: fsl_spi.h:131
_spi_master_handle::callback
spi_master_callback_t callback
Definition: fsl_spi.h:241
kSPI_RxFifoFullFlag
Definition: fsl_spi.h:127
kStatusGroup_SPI
Definition: fsl_common.h:79
spi_master_config_t::enableFifoInterruptClear
bool enableFifoInterruptClear
Definition: fsl_spi.h:183
spi_slave_config_t
SPI slave user configure structure.
Definition: fsl_spi.h:193
kSPI_MatchInterruptEnable
Definition: fsl_spi.h:110
spi_transfer_t::flags
uint32_t flags
Definition: fsl_spi.h:216
spi_clock_polarity_t
spi_clock_polarity_t
SPI clock polarity configuration.
Definition: fsl_spi.h:58
kStatus_SPI_Busy
Definition: fsl_spi.h:52
kSPI_RxFifoOneHalfFull
Definition: fsl_spi.h:157
SPI_ClearInterrupt
static void SPI_ClearInterrupt(SPI_Type *base, uint32_t mask)
Clear the interrupt if enable INCTLR.
Definition: fsl_spi.h:385
SPI_SlaveGetDefaultConfig
void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config)
Set the SPI slave configuration structure to default values.
Definition: fsl_spi.c:328
kSPI_RxNearFullClearInterrupt
Definition: fsl_spi.h:142
_spi_master_handle
SPI transfer handle structure.
Definition: fsl_spi.h:231
kSPI_MsbFirst
Definition: fsl_spi.h:76
_spi_master_handle::txRemainingBytes
volatile size_t txRemainingBytes
Definition: fsl_spi.h:235
kStatus_SPI_Idle
Definition: fsl_spi.h:53
spi_master_config_t::polarity
spi_clock_polarity_t polarity
Definition: fsl_spi.h:176
_spi_master_handle::state
volatile uint32_t state
Definition: fsl_spi.h:237
spi_master_config_t::outputMode
spi_ss_output_mode_t outputMode
Definition: fsl_spi.h:187
kSPI_SlaveSelectAsGpio
Definition: fsl_spi.h:83
kSPI_RxDmaEnable
Definition: fsl_spi.h:166
spi_master_config_t::enableStopInWaitMode
bool enableStopInWaitMode
Definition: fsl_spi.h:175
SPI_SlaveTransferNonBlocking
static status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
Performs a non-blocking SPI slave interrupt transfer.
Definition: fsl_spi.h:653
spi_slave_callback_t
void(* spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData)
SPI master callback for finished transmit.
Definition: fsl_spi.h:228
spi_master_callback_t
void(* spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData)
SPI master callback for finished transmit.
Definition: fsl_spi.h:225
kSPI_RxOverflow
Definition: fsl_spi.h:132
spi_master_config_t::rxWatermark
spi_rxfifo_watermark_t rxWatermark
Definition: fsl_spi.h:185
kSPI_PinModeInput
Definition: fsl_spi.h:92
spi_shift_direction_t
spi_shift_direction_t
SPI data shifter direction options.
Definition: fsl_spi.h:74
spi_ss_output_mode_t
spi_ss_output_mode_t
SPI slave select output mode options.
Definition: fsl_spi.h:81
SPI_EnableDMA
static void SPI_EnableDMA(SPI_Type *base, uint32_t mask, bool enable)
Enable dma source for SPI.
Definition: fsl_spi.h:439
SPI_EnableInterrupts
void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask)
Enable interrupt for SPI.
Definition: fsl_spi.c:406
kSPI_RxFifoThreeFourthsFull
Definition: fsl_spi.h:156
SPI_SlaveTransferAbort
static void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
Abort a SPI slave transfer using interrupt.
Definition: fsl_spi.h:678
kSPI_SlaveSelectAutomaticOutput
Definition: fsl_spi.h:85
kSPI_TxFifoEmptyFlag
Definition: fsl_spi.h:128
kSPI_RxBufferFullFlag
Definition: fsl_spi.h:120
kSPI_ClockPhaseSecondEdge
Definition: fsl_spi.h:69
kSPI_TxBufferEmptyFlag
Definition: fsl_spi.h:122
_spi_master_handle::rxRemainingBytes
volatile size_t rxRemainingBytes
Definition: fsl_spi.h:236
SPI_SetMatchData
static void SPI_SetMatchData(SPI_Type *base, uint32_t matchData)
Set match data for SPI.
Definition: fsl_spi.h:495
SPI_MasterTransferBlocking
status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer)
Transfer a block of data in polling way.
Definition: fsl_spi.c:596
kSPI_PinModeOutput
Definition: fsl_spi.h:94
SPI_GetStatusFlags
uint32_t SPI_GetStatusFlags(SPI_Type *base)
Get the status flag.
Definition: fsl_spi.c:390
SPI_MasterGetDefaultConfig
void SPI_MasterGetDefaultConfig(spi_master_config_t *config)
Set the SPI master configuration structure to default values.
Definition: fsl_spi.c:265
kSPI_RxFifoNearFullInterruptEnable
Definition: fsl_spi.h:112
SPI_Enable
static void SPI_Enable(I2C_Type *base, bool enable)
Enable or disables the SPI.
Definition: fsl_spi.h:346
_spi_master_handle::txData
uint8_t *volatile txData
Definition: fsl_spi.h:233
spi_master_config_t::direction
spi_shift_direction_t direction
Definition: fsl_spi.h:178
spi_transfer_t::dataSize
size_t dataSize
Definition: fsl_spi.h:215
kSPI_TxEmptyInterruptEnable
Definition: fsl_spi.h:109
spi_master_config_t::baudRate_Bps
uint32_t baudRate_Bps
Definition: fsl_spi.h:189
kSPI_RxFifoError
Definition: fsl_spi.h:130
SPI_MasterTransferGetCount
status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count)
Get the bytes of SPI Interrupt transferred.
Definition: fsl_spi.c:758
SPI_GetDataRegisterAddress
static uint32_t SPI_GetDataRegisterAddress(SPI_Type *base)
Get SPI tx/rx data register address.
Definition: fsl_spi.h:460
SPI_SlaveInit
void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config)
Initialize SPI with slave configuration.
Definition: fsl_spi.c:346
spi_master_config_t
SPI master user configure structure.
Definition: fsl_spi.h:172
spi_data_bitcount_mode_t
spi_data_bitcount_mode_t
SPI data length mode options.
Definition: fsl_spi.h:99
spi_master_config_t::dataMode
spi_data_bitcount_mode_t dataMode
Definition: fsl_spi.h:180
_spi_status
_spi_status
Return status for the SPI driver.
Definition: fsl_spi.h:50
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_Type *base, bool enable)
Enable or Disable FIFO if there is FIFO.
Definition: fsl_spi.c:558
SPI_SlaveTransferCreateHandle
static void SPI_SlaveTransferCreateHandle(SPI_Type *base, spi_slave_handle_t *handle, spi_slave_callback_t callback, void *userData)
Initialize the SPI slave handle.
Definition: fsl_spi.h:628
spi_pin_mode_t
spi_pin_mode_t
SPI pin mode options.
Definition: fsl_spi.h:89
spi_master_config_t::pinMode
spi_pin_mode_t pinMode
Definition: fsl_spi.h:188
spi_transfer_t::rxData
uint8_t * rxData
Definition: fsl_spi.h:214
SPI_MasterTransferHandleIRQ
void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle)
Interrupt handler for SPI.
Definition: fsl_spi.c:810
_spi_master_handle::userData
void * userData
Definition: fsl_spi.h:242
kSPI_SlaveSelectFaultInput
Definition: fsl_spi.h:84
kSPI_ClockPolarityActiveHigh
Definition: fsl_spi.h:60
kSPI_LsbFirst
Definition: fsl_spi.h:77
status_t
int32_t status_t
Type used for all status and error return values.
Definition: fsl_common.h:121
kSPI_RxFullAndModfInterruptEnable
Definition: fsl_spi.h:108
_spi_master_handle::transferSize
size_t transferSize
Definition: fsl_spi.h:238
kSPI_TxFifoEmptyClearInterrupt
Definition: fsl_spi.h:141
kSPI_ModeFaultFlag
Definition: fsl_spi.h:123
spi_rxfifo_watermark_t
spi_rxfifo_watermark_t
SPI RX FIFO watermark settings.
Definition: fsl_spi.h:154
kSPI_PinModeNormal
Definition: fsl_spi.h:91
SPI_MasterSetBaudRate
void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
Set Baud rate for SPI transfer, this only used in master.
Definition: fsl_spi.c:483
kSPI_RxFifoFullClearInterrupt
Definition: fsl_spi.h:140
kSPI_TxDmaEnable
Definition: fsl_spi.h:165
SPI_MasterTransferAbort
void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle)
Abort a SPI transfer using interrupt.
Definition: fsl_spi.c:784