fsl_dspi.h
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_DSPI_H_
#define _FSL_DSPI_H_
#include "fsl_common.h"
/**********************************************************************************************************************
* Definitions
*********************************************************************************************************************/
#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
#define DSPI_MASTER_DUMMY_DATA (0x00U)
#define DSPI_SLAVE_DUMMY_DATA (0x00U)
enum _dspi_status
{
kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0),
kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1),
kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2),
kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3)
};
enum _dspi_flags
{
kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK,
kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK,
kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK,
kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK,
kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK,
kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK,
kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK,
kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK |
SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK
};
enum _dspi_interrupt_enable
{
kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK,
kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK,
kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK,
kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK,
kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK,
kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK,
kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK |
SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK
};
enum _dspi_dma_enable
{
kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK),
kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK)
};
typedef enum _dspi_master_slave_mode
{
kDSPI_Master = 1U,
kDSPI_Slave = 0U
} dspi_master_slave_mode_t;
typedef enum _dspi_master_sample_point
{
kDSPI_SckToSin0Clock = 0U,
kDSPI_SckToSin1Clock = 1U,
kDSPI_SckToSin2Clock = 2U
} dspi_master_sample_point_t;
typedef enum _dspi_which_pcs_config
{
kDSPI_Pcs0 = 1U << 0,
kDSPI_Pcs1 = 1U << 1,
kDSPI_Pcs2 = 1U << 2,
kDSPI_Pcs3 = 1U << 3,
kDSPI_Pcs4 = 1U << 4,
kDSPI_Pcs5 = 1U << 5
} dspi_which_pcs_t;
typedef enum _dspi_pcs_polarity_config
{
kDSPI_PcsActiveHigh = 0U,
kDSPI_PcsActiveLow = 1U
} dspi_pcs_polarity_config_t;
enum _dspi_pcs_polarity
{
kDSPI_Pcs0ActiveLow = 1U << 0,
kDSPI_Pcs1ActiveLow = 1U << 1,
kDSPI_Pcs2ActiveLow = 1U << 2,
kDSPI_Pcs3ActiveLow = 1U << 3,
kDSPI_Pcs4ActiveLow = 1U << 4,
kDSPI_Pcs5ActiveLow = 1U << 5,
kDSPI_PcsAllActiveLow = 0xFFU
};
typedef enum _dspi_clock_polarity
{
kDSPI_ClockPolarityActiveHigh = 0U,
kDSPI_ClockPolarityActiveLow = 1U
} dspi_clock_polarity_t;
typedef enum _dspi_clock_phase
{
kDSPI_ClockPhaseFirstEdge = 0U,
kDSPI_ClockPhaseSecondEdge = 1U
} dspi_clock_phase_t;
typedef enum _dspi_shift_direction
{
kDSPI_MsbFirst = 0U,
kDSPI_LsbFirst = 1U
} dspi_shift_direction_t;
typedef enum _dspi_delay_type
{
kDSPI_PcsToSck = 1U,
kDSPI_LastSckToPcs,
kDSPI_BetweenTransfer
} dspi_delay_type_t;
typedef enum _dspi_ctar_selection
{
kDSPI_Ctar0 = 0U,
kDSPI_Ctar1 = 1U,
kDSPI_Ctar2 = 2U,
kDSPI_Ctar3 = 3U,
kDSPI_Ctar4 = 4U,
kDSPI_Ctar5 = 5U,
kDSPI_Ctar6 = 6U,
kDSPI_Ctar7 = 7U
} dspi_ctar_selection_t;
#define DSPI_MASTER_CTAR_SHIFT (0U)
#define DSPI_MASTER_CTAR_MASK (0x0FU)
#define DSPI_MASTER_PCS_SHIFT (4U)
#define DSPI_MASTER_PCS_MASK (0xF0U)
enum _dspi_transfer_config_flag_for_master
{
kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT,
kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT,
kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT,
kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT,
kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT,
kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT,
kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT,
kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT,
kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT,
kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT,
kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT,
kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT,
kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT,
kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT,
kDSPI_MasterPcsContinuous = 1U << 20,
kDSPI_MasterActiveAfterTransfer = 1U << 21,
};
#define DSPI_SLAVE_CTAR_SHIFT (0U)
#define DSPI_SLAVE_CTAR_MASK (0x07U)
enum _dspi_transfer_config_flag_for_slave
{
kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT,
};
enum _dspi_transfer_state
{
kDSPI_Idle = 0x0U,
kDSPI_Busy,
kDSPI_Error
};
typedef struct _dspi_command_data_config
{
bool isPcsContinuous;
dspi_ctar_selection_t whichCtar;
dspi_which_pcs_t whichPcs;
bool isEndOfQueue;
bool clearTransferCount;
} dspi_command_data_config_t;
typedef struct _dspi_master_ctar_config
{
uint32_t baudRate;
uint32_t bitsPerFrame;
dspi_clock_polarity_t cpol;
dspi_clock_phase_t cpha;
dspi_shift_direction_t direction;
uint32_t pcsToSckDelayInNanoSec;
uint32_t lastSckToPcsDelayInNanoSec;
uint32_t betweenTransferDelayInNanoSec;
} dspi_master_ctar_config_t;
typedef struct _dspi_master_config
{
dspi_ctar_selection_t whichCtar;
dspi_master_ctar_config_t ctarConfig;
dspi_which_pcs_t whichPcs;
dspi_pcs_polarity_config_t pcsActiveHighOrLow;
bool enableContinuousSCK;
bool enableRxFifoOverWrite;
bool enableModifiedTimingFormat;
dspi_master_sample_point_t samplePoint;
} dspi_master_config_t;
typedef struct _dspi_slave_ctar_config
{
uint32_t bitsPerFrame;
dspi_clock_polarity_t cpol;
dspi_clock_phase_t cpha;
} dspi_slave_ctar_config_t;
typedef struct _dspi_slave_config
{
dspi_ctar_selection_t whichCtar;
dspi_slave_ctar_config_t ctarConfig;
bool enableContinuousSCK;
bool enableRxFifoOverWrite;
bool enableModifiedTimingFormat;
dspi_master_sample_point_t samplePoint;
} dspi_slave_config_t;
typedef struct _dspi_master_handle dspi_master_handle_t;
typedef struct _dspi_slave_handle dspi_slave_handle_t;
typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base,
dspi_master_handle_t *handle,
status_t status,
void *userData);
typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base,
dspi_slave_handle_t *handle,
status_t status,
void *userData);
typedef struct _dspi_transfer
{
uint8_t *txData;
uint8_t *rxData;
volatile size_t dataSize;
uint32_t
configFlags;
} dspi_transfer_t;
struct _dspi_master_handle
{
uint32_t bitsPerFrame;
volatile uint32_t command;
volatile uint32_t lastCommand;
uint8_t fifoSize;
volatile bool isPcsActiveAfterTransfer;
volatile bool isThereExtraByte;
uint8_t *volatile txData;
uint8_t *volatile rxData;
volatile size_t remainingSendByteCount;
volatile size_t remainingReceiveByteCount;
size_t totalByteCount;
volatile uint8_t state;
dspi_master_transfer_callback_t callback;
void *userData;
};
struct _dspi_slave_handle
{
uint32_t bitsPerFrame;
volatile bool isThereExtraByte;
uint8_t *volatile txData;
uint8_t *volatile rxData;
volatile size_t remainingSendByteCount;
volatile size_t remainingReceiveByteCount;
size_t totalByteCount;
volatile uint8_t state;
volatile uint32_t errorCount;
dspi_slave_transfer_callback_t callback;
void *userData;
};
/**********************************************************************************************************************
* API
*********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /*_cplusplus*/
void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig);
void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
void DSPI_Deinit(SPI_Type *base);
static inline void DSPI_Enable(SPI_Type *base, bool enable)
{
if (enable)
{
base->MCR &= ~SPI_MCR_MDIS_MASK;
}
else
{
base->MCR |= SPI_MCR_MDIS_MASK;
}
}
static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
{
return (base->SR);
}
static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
{
base->SR = statusFlags;
}
void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
{
base->RSER &= ~mask;
}
static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
{
base->RSER |= mask;
}
static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
{
base->RSER &= ~mask;
}
static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
{
return (uint32_t) & (base->PUSHR);
}
static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
{
return (uint32_t) & (base->PUSHR_SLAVE);
}
static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
{
return (uint32_t) & (base->POPR);
}
static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
{
base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode);
}
static inline bool DSPI_IsMaster(SPI_Type *base)
{
return (bool)((base->MCR) & SPI_MCR_MSTR_MASK);
}
static inline void DSPI_StartTransfer(SPI_Type *base)
{
base->MCR &= ~SPI_MCR_HALT_MASK;
}
static inline void DSPI_StopTransfer(SPI_Type *base)
{
base->MCR |= SPI_MCR_HALT_MASK;
}
static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
{
base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) |
SPI_MCR_DIS_RXF(!enableRxFifo);
}
static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
{
base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) |
SPI_MCR_CLR_RXF(flushRxFifo);
}
static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
{
base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask);
}
uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
dspi_ctar_selection_t whichCtar,
uint32_t baudRate_Bps,
uint32_t srcClock_Hz);
void DSPI_MasterSetDelayScaler(
SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
dspi_ctar_selection_t whichCtar,
dspi_delay_type_t whichDelay,
uint32_t srcClock_Hz,
uint32_t delayTimeInNanoSec);
static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
{
base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data);
}
void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data);
static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
{
/* Format the 16-bit command word according to the PUSHR data register bit field*/
return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
SPI_PUSHR_CTCNT(command->clearTransferCount));
}
void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
{
base->PUSHR_SLAVE = data;
}
void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data);
static inline uint32_t DSPI_ReadData(SPI_Type *base)
{
return (base->POPR);
}
/*Transactional APIs*/
void DSPI_MasterTransferCreateHandle(SPI_Type *base,
dspi_master_handle_t *handle,
dspi_master_transfer_callback_t callback,
void *userData);
status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);
status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count);
void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);
void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);
void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
dspi_slave_handle_t *handle,
dspi_slave_transfer_callback_t callback,
void *userData);
status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer);
status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count);
void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);
void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle);
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
#endif /*_FSL_DSPI_H_*/
kDSPI_TxCompleteFlag
Definition: fsl_dspi.h:63
kStatusGroup_DSPI
Definition: fsl_common.h:71
dspi_transfer_t::rxData
uint8_t * rxData
Definition: fsl_dspi.h:349
dspi_master_ctar_config_t::cpha
dspi_clock_phase_t cpha
Definition: fsl_dspi.h:251
kDSPI_TxDmaEnable
Definition: fsl_dspi.h:91
dspi_master_ctar_config_t::lastSckToPcsDelayInNanoSec
uint32_t lastSckToPcsDelayInNanoSec
Definition: fsl_dspi.h:256
dspi_transfer_t::txData
uint8_t * txData
Definition: fsl_dspi.h:348
kDSPI_Pcs3ActiveLow
Definition: fsl_dspi.h:139
kDSPI_MasterPcs3
Definition: fsl_dspi.h:209
kDSPI_Pcs4ActiveLow
Definition: fsl_dspi.h:140
kDSPI_TxCompleteInterruptEnable
Definition: fsl_dspi.h:77
kDSPI_ClockPolarityActiveHigh
Definition: fsl_dspi.h:148
_dspi_flags
_dspi_flags
DSPI status flags in SPIx_SR register.
Definition: fsl_dspi.h:61
_dspi_master_handle
DSPI master transfer handle structure used for transactional API.
Definition: fsl_dspi.h:359
kDSPI_MasterCtar6
Definition: fsl_dspi.h:203
dspi_master_ctar_config_t
DSPI master ctar config structure.
Definition: fsl_dspi.h:246
kDSPI_MasterCtar0
Definition: fsl_dspi.h:197
DSPI_SlaveGetTxRegisterAddress
static uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
Gets the DSPI slave PUSHR data register address for the DMA operation.
Definition: fsl_dspi.h:659
dspi_master_slave_mode_t
dspi_master_slave_mode_t
DSPI master or slave mode configuration.
Definition: fsl_dspi.h:98
DSPI_MasterGetDefaultConfig
void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig)
Sets the dspi_master_config_t structure to default values.
Definition: fsl_dspi.c:202
DSPI_SlaveTransferGetCount
status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count)
Gets the slave transfer count.
Definition: fsl_dspi.c:1281
kDSPI_Ctar6
Definition: fsl_dspi.h:186
kDSPI_TxFifoUnderflowFlag
Definition: fsl_dspi.h:65
_dspi_dma_enable
_dspi_dma_enable
DSPI DMA source.
Definition: fsl_dspi.h:89
DSPI_MasterWriteCommandDataBlocking
void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data)
Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data buffer...
Definition: fsl_dspi.c:488
dspi_master_config_t::enableContinuousSCK
bool enableContinuousSCK
Definition: fsl_dspi.h:272
DSPI_StartTransfer
static void DSPI_StartTransfer(SPI_Type *base)
Starts the DSPI transfers and clears HALT bit in MCR.
Definition: fsl_dspi.h:714
kDSPI_ClockPolarityActiveLow
Definition: fsl_dspi.h:149
dspi_command_data_config_t::clearTransferCount
bool clearTransferCount
Definition: fsl_dspi.h:242
dspi_clock_phase_t
dspi_clock_phase_t
DSPI clock phase configuration for a given CTAR.
Definition: fsl_dspi.h:153
kDSPI_RxFifoOverflowInterruptEnable
Definition: fsl_dspi.h:81
kDSPI_Slave
Definition: fsl_dspi.h:101
DSPI_EnableInterrupts
void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask)
Enables the DSPI interrupts.
Definition: fsl_dspi.c:528
kDSPI_MasterActiveAfterTransfer
Definition: fsl_dspi.h:214
_dspi_master_handle::state
volatile uint8_t state
Definition: fsl_dspi.h:376
dspi_master_ctar_config_t::pcsToSckDelayInNanoSec
uint32_t pcsToSckDelayInNanoSec
Definition: fsl_dspi.h:254
kDSPI_RxFifoDrainRequestInterruptEnable
Definition: fsl_dspi.h:82
dspi_command_data_config_t::whichCtar
dspi_ctar_selection_t whichCtar
Definition: fsl_dspi.h:238
DSPI_ReadData
static uint32_t DSPI_ReadData(SPI_Type *base)
Reads data from the data buffer.
Definition: fsl_dspi.h:1015
DSPI_MasterTransferGetCount
status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count)
Gets the master transfer count.
Definition: fsl_dspi.c:924
_dspi_slave_handle::userData
void * userData
Definition: fsl_dspi.h:399
DSPI_SetAllPcsPolarity
static void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
Configures the DSPI peripheral chip select polarity simultaneously. For example, PCS0 and PCS1 set to...
Definition: fsl_dspi.h:770
DSPI_MasterWriteData
static void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
Writes data into the data buffer for master mode.
Definition: fsl_dspi.h:868
DSPI_DisableDMA
static void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
Disables the DSPI DMA request.
Definition: fsl_dspi.h:633
kDSPI_MasterPcs2
Definition: fsl_dspi.h:208
_dspi_master_handle::totalByteCount
size_t totalByteCount
Definition: fsl_dspi.h:374
kDSPI_MasterCtar1
Definition: fsl_dspi.h:198
kDSPI_MasterCtar7
Definition: fsl_dspi.h:204
kDSPI_SckToSin2Clock
Definition: fsl_dspi.h:112
dspi_ctar_selection_t
dspi_ctar_selection_t
DSPI Clock and Transfer Attributes Register (CTAR) selection.
Definition: fsl_dspi.h:177
DSPI_MasterTransferHandleIRQ
void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle)
DSPI Master IRQ handler function.
Definition: fsl_dspi.c:1092
DSPI_SetFifoEnable
static void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
Enables (or disables) the DSPI FIFOs.
Definition: fsl_dspi.h:741
kDSPI_TxFifoFillRequestFlag
Definition: fsl_dspi.h:66
kStatus_DSPI_OutOfRange
Definition: fsl_dspi.h:57
dspi_slave_config_t
DSPI slave configuration structure.
Definition: fsl_dspi.h:294
_dspi_master_handle::callback
dspi_master_transfer_callback_t callback
Definition: fsl_dspi.h:378
kDSPI_ClockPhaseFirstEdge
Definition: fsl_dspi.h:155
dspi_master_ctar_config_t::direction
dspi_shift_direction_t direction
Definition: fsl_dspi.h:252
DSPI_SlaveTransferCreateHandle
void DSPI_SlaveTransferCreateHandle(SPI_Type *base, dspi_slave_handle_t *handle, dspi_slave_transfer_callback_t callback, void *userData)
Initializes the DSPI slave handle.
Definition: fsl_dspi.c:1197
kDSPI_EndOfQueueFlag
Definition: fsl_dspi.h:64
dspi_master_ctar_config_t::bitsPerFrame
uint32_t bitsPerFrame
Definition: fsl_dspi.h:249
DSPI_ClearStatusFlags
static void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
Clears the DSPI status flag.
Definition: fsl_dspi.h:553
dspi_master_config_t::samplePoint
dspi_master_sample_point_t samplePoint
Definition: fsl_dspi.h:280
_dspi_master_handle::lastCommand
volatile uint32_t lastCommand
Definition: fsl_dspi.h:363
kDSPI_Pcs2
Definition: fsl_dspi.h:120
kDSPI_Pcs3
Definition: fsl_dspi.h:121
kDSPI_Pcs5
Definition: fsl_dspi.h:123
DSPI_GetStatusFlags
static uint32_t DSPI_GetStatusFlags(SPI_Type *base)
Gets the DSPI status flag state.
Definition: fsl_dspi.h:534
DSPI_MasterSetDelayScaler
void DSPI_MasterSetDelayScaler(SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay)
Manually configures the delay prescaler and scaler for a particular CTAR.
Definition: fsl_dspi.c:360
kDSPI_LsbFirst
Definition: fsl_dspi.h:165
dspi_transfer_t
DSPI master/slave transfer structure.
Definition: fsl_dspi.h:346
dspi_slave_config_t::ctarConfig
dspi_slave_ctar_config_t ctarConfig
Definition: fsl_dspi.h:297
kDSPI_Pcs1
Definition: fsl_dspi.h:119
kDSPI_Ctar1
Definition: fsl_dspi.h:181
DSPI_SlaveWriteDataBlocking
void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data)
Writes data into the data buffer in slave mode, waits till data was transmitted, and returns...
Definition: fsl_dspi.c:508
DSPI_MasterGetFormattedCommand
static uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
Returns the DSPI command word formatted to the PUSHR data register bit field.
Definition: fsl_dspi.h:935
kDSPI_Ctar4
Definition: fsl_dspi.h:184
DSPI_Deinit
void DSPI_Deinit(SPI_Type *base)
De-initializes the DSPI peripheral. Call this API to disable the DSPI clock.
Definition: fsl_dspi.c:269
kDSPI_Pcs5ActiveLow
Definition: fsl_dspi.h:141
kDSPI_BetweenTransfer
Definition: fsl_dspi.h:173
kDSPI_ClockPhaseSecondEdge
Definition: fsl_dspi.h:157
DSPI_MasterTransferNonBlocking
status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer)
DSPI master transfer data using interrupts.
Definition: fsl_dspi.c:887
DSPI_FlushFifo
static void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
Flushes the DSPI FIFOs.
Definition: fsl_dspi.h:754
dspi_master_config_t::ctarConfig
dspi_master_ctar_config_t ctarConfig
Definition: fsl_dspi.h:267
kDSPI_Pcs0ActiveLow
Definition: fsl_dspi.h:136
DSPI_MasterTransferBlocking
status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
DSPI master transfer data using polling.
Definition: fsl_dspi.c:559
kDSPI_PcsActiveHigh
Definition: fsl_dspi.h:129
dspi_master_config_t::pcsActiveHighOrLow
dspi_pcs_polarity_config_t pcsActiveHighOrLow
Definition: fsl_dspi.h:270
dspi_delay_type_t
dspi_delay_type_t
DSPI delay type selection.
Definition: fsl_dspi.h:169
kDSPI_SlaveCtar0
Definition: fsl_dspi.h:222
kDSPI_TxAndRxStatusFlag
Definition: fsl_dspi.h:69
DSPI_MasterSetDelayTimes
uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, dspi_ctar_selection_t whichCtar, dspi_delay_type_t whichDelay, uint32_t srcClock_Hz, uint32_t delayTimeInNanoSec)
Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
Definition: fsl_dspi.c:386
_dspi_slave_handle
DSPI slave transfer handle structure used for transactional API.
Definition: fsl_dspi.h:383
dspi_command_data_config_t
DSPI master command date configuration used for SPIx_PUSHR.
Definition: fsl_dspi.h:235
dspi_master_sample_point_t
dspi_master_sample_point_t
DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format...
Definition: fsl_dspi.h:108
dspi_slave_transfer_callback_t
void(* dspi_slave_transfer_callback_t)(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
Completion callback function pointer type.
Definition: fsl_dspi.h:340
DSPI_StopTransfer
static void DSPI_StopTransfer(SPI_Type *base)
Stops (halts) DSPI transfers and sets HALT bit in MCR.
Definition: fsl_dspi.h:725
dspi_transfer_t::dataSize
volatile size_t dataSize
Definition: fsl_dspi.h:350
kDSPI_Ctar0
Definition: fsl_dspi.h:179
kStatus_DSPI_Error
Definition: fsl_dspi.h:55
kDSPI_MsbFirst
Definition: fsl_dspi.h:164
dspi_command_data_config_t::isPcsContinuous
bool isPcsContinuous
Definition: fsl_dspi.h:237
kDSPI_TxFifoUnderflowInterruptEnable
Definition: fsl_dspi.h:79
DSPI_GetDefaultDataCommandConfig
void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command)
Sets the dspi_command_data_config_t structure to default values.
Definition: fsl_dspi.c:458
_dspi_master_handle::remainingSendByteCount
volatile size_t remainingSendByteCount
Definition: fsl_dspi.h:372
dspi_which_pcs_t
dspi_which_pcs_t
DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).
Definition: fsl_dspi.h:116
kDSPI_Busy
Definition: fsl_dspi.h:230
_dspi_slave_handle::errorCount
volatile uint32_t errorCount
Definition: fsl_dspi.h:396
kDSPI_RxFifoOverflowFlag
Definition: fsl_dspi.h:67
_dspi_master_handle::rxData
uint8_t *volatile rxData
Definition: fsl_dspi.h:371
DSPI_SlaveGetDefaultConfig
void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig)
Sets the dspi_slave_config_t structure to default values.
Definition: fsl_dspi.c:256
DSPI_EnableDMA
static void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
Enables the DSPI DMA request.
Definition: fsl_dspi.h:617
DSPI_MasterTransferAbort
void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle)
DSPI master aborts transfer using an interrupt.
Definition: fsl_dspi.c:1082
dspi_shift_direction_t
dspi_shift_direction_t
DSPI data shifter direction options for a given CTAR.
Definition: fsl_dspi.h:162
kDSPI_Idle
Definition: fsl_dspi.h:229
dspi_master_ctar_config_t::cpol
dspi_clock_polarity_t cpol
Definition: fsl_dspi.h:250
dspi_slave_ctar_config_t
DSPI slave ctar configuration structure.
Definition: fsl_dspi.h:285
DSPI_SlaveTransferAbort
void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle)
DSPI slave aborts a transfer using an interrupt.
Definition: fsl_dspi.c:1417
DSPI_GetRxRegisterAddress
static uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
Gets the DSPI POPR data register address for the DMA operation.
Definition: fsl_dspi.h:672
_dspi_interrupt_enable
_dspi_interrupt_enable
DSPI interrupt source.
Definition: fsl_dspi.h:75
kDSPI_Pcs4
Definition: fsl_dspi.h:122
kDSPI_SckToSin1Clock
Definition: fsl_dspi.h:111
DSPI_MasterInit
void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
Initializes the DSPI master.
Definition: fsl_dspi.c:159
kDSPI_Master
Definition: fsl_dspi.h:100
dspi_transfer_t::configFlags
uint32_t configFlags
Definition: fsl_dspi.h:353
dspi_command_data_config_t::isEndOfQueue
bool isEndOfQueue
Definition: fsl_dspi.h:241
kDSPI_MasterPcs1
Definition: fsl_dspi.h:207
DSPI_Enable
static void DSPI_Enable(SPI_Type *base, bool enable)
Enables the DSPI peripheral and sets the MCR MDIS to 0.
Definition: fsl_dspi.h:508
DSPI_DisableInterrupts
static void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
Disables the DSPI interrupts.
Definition: fsl_dspi.h:592
DSPI_MasterWriteDataBlocking
void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
Writes data into the data buffer master mode and waits till complete to return.
Definition: fsl_dspi.c:467
dspi_pcs_polarity_config_t
dspi_pcs_polarity_config_t
DSPI Peripheral Chip Select (Pcs) Polarity configuration.
Definition: fsl_dspi.h:127
DSPI_MasterTransferCreateHandle
void DSPI_MasterTransferCreateHandle(SPI_Type *base, dspi_master_handle_t *handle, dspi_master_transfer_callback_t callback, void *userData)
Initializes the DSPI master handle.
Definition: fsl_dspi.c:543
DSPI_IsMaster
static bool DSPI_IsMaster(SPI_Type *base)
Returns whether the DSPI module is in master mode.
Definition: fsl_dspi.h:703
DSPI_SlaveInit
void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig)
DSPI slave configuration.
Definition: fsl_dspi.c:224
kStatus_DSPI_Busy
Definition: fsl_dspi.h:54
_dspi_master_handle::isThereExtraByte
volatile bool isThereExtraByte
Definition: fsl_dspi.h:368
kDSPI_MasterCtar2
Definition: fsl_dspi.h:199
_dspi_pcs_polarity
_dspi_pcs_polarity
DSPI Peripheral Chip Select (Pcs) Polarity.
Definition: fsl_dspi.h:134
kDSPI_PcsActiveLow
Definition: fsl_dspi.h:130
kDSPI_AllStatusFlag
Definition: fsl_dspi.h:70
kDSPI_MasterPcs5
Definition: fsl_dspi.h:211
kDSPI_LastSckToPcs
Definition: fsl_dspi.h:172
kDSPI_MasterPcs4
Definition: fsl_dspi.h:210
dspi_command_data_config_t::whichPcs
dspi_which_pcs_t whichPcs
Definition: fsl_dspi.h:240
kDSPI_Pcs1ActiveLow
Definition: fsl_dspi.h:137
kDSPI_MasterCtar3
Definition: fsl_dspi.h:200
kDSPI_PcsAllActiveLow
Definition: fsl_dspi.h:142
DSPI_SlaveTransferNonBlocking
status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer)
DSPI slave transfers data using an interrupt.
Definition: fsl_dspi.c:1213
kDSPI_Pcs0
Definition: fsl_dspi.h:118
dspi_master_ctar_config_t::betweenTransferDelayInNanoSec
uint32_t betweenTransferDelayInNanoSec
Definition: fsl_dspi.h:259
kDSPI_MasterPcsContinuous
Definition: fsl_dspi.h:213
kDSPI_PcsToSck
Definition: fsl_dspi.h:171
kDSPI_TxFifoFillRequestInterruptEnable
Definition: fsl_dspi.h:80
kDSPI_Ctar3
Definition: fsl_dspi.h:183
_dspi_master_handle::isPcsActiveAfterTransfer
volatile bool isPcsActiveAfterTransfer
Definition: fsl_dspi.h:367
DSPI_SlaveWriteData
static void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
Writes data into the data buffer in slave mode.
Definition: fsl_dspi.h:993
dspi_master_transfer_callback_t
void(* dspi_master_transfer_callback_t)(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
Completion callback function pointer type.
Definition: fsl_dspi.h:328
_dspi_slave_handle::callback
dspi_slave_transfer_callback_t callback
Definition: fsl_dspi.h:398
dspi_master_config_t
DSPI master config structure.
Definition: fsl_dspi.h:264
dspi_clock_polarity_t
dspi_clock_polarity_t
DSPI clock polarity configuration for a given CTAR.
Definition: fsl_dspi.h:146
DSPI_SlaveTransferHandleIRQ
void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle)
DSPI Master IRQ handler function.
Definition: fsl_dspi.c:1430
dspi_master_ctar_config_t::baudRate
uint32_t baudRate
Definition: fsl_dspi.h:248
DSPI_MasterGetTxRegisterAddress
static uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
Gets the DSPI master PUSHR data register address for the DMA operation.
Definition: fsl_dspi.h:646
kDSPI_MasterCtar4
Definition: fsl_dspi.h:201
kDSPI_EndOfQueueInterruptEnable
Definition: fsl_dspi.h:78
kDSPI_MasterCtar5
Definition: fsl_dspi.h:202
kStatus_DSPI_Idle
Definition: fsl_dspi.h:56
kDSPI_SckToSin0Clock
Definition: fsl_dspi.h:110
kDSPI_Error
Definition: fsl_dspi.h:231
_dspi_master_handle::fifoSize
uint8_t fifoSize
Definition: fsl_dspi.h:365
kDSPI_Ctar2
Definition: fsl_dspi.h:182
_dspi_master_handle::remainingReceiveByteCount
volatile size_t remainingReceiveByteCount
Definition: fsl_dspi.h:373
kDSPI_MasterPcs0
Definition: fsl_dspi.h:206
dspi_master_config_t::enableModifiedTimingFormat
bool enableModifiedTimingFormat
Definition: fsl_dspi.h:279
kDSPI_Ctar7
Definition: fsl_dspi.h:187
status_t
int32_t status_t
Type used for all status and error return values.
Definition: fsl_common.h:121
kDSPI_Pcs2ActiveLow
Definition: fsl_dspi.h:138
kDSPI_RxDmaEnable
Definition: fsl_dspi.h:93
DSPI_MasterSetBaudRate
uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
Sets the DSPI baud rate in bits per second.
Definition: fsl_dspi.c:296
DSPI_SetMasterSlaveMode
static void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
Configures the DSPI for master or slave.
Definition: fsl_dspi.h:692
kDSPI_Ctar5
Definition: fsl_dspi.h:185
kDSPI_RxFifoDrainRequestFlag
Definition: fsl_dspi.h:68
_dspi_master_handle::command
volatile uint32_t command
Definition: fsl_dspi.h:362
_dspi_transfer_state
_dspi_transfer_state
DSPI transfer state, which is used for DSPI transactiaonl APIs&#39; state machine.
Definition: fsl_dspi.h:227
dspi_master_config_t::enableRxFifoOverWrite
bool enableRxFifoOverWrite
Definition: fsl_dspi.h:274
kDSPI_AllInterruptEnable
Definition: fsl_dspi.h:83
_dspi_master_handle::txData
uint8_t *volatile txData
Definition: fsl_dspi.h:370