Kinetis Bootloader
2.0.0
Common bootloader for Kinetis devices
Introduction
Related Pages
Modules
system_MKL82Z7.h
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/*
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** ###################################################################
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** Processors: MKL82Z128VLH7
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** MKL82Z128VLK7
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** MKL82Z128VLL7
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** MKL82Z128VMC7
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** MKL82Z128VMP7
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**
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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**
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** Reference manual: KL82P121M72SF0RM, Rev.1.2 September 2015
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** Version: rev. 1.5, 2015-09-24
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** Build: b151023
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright (c) 2015 Freescale Semiconductor, Inc.
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 1.0 (2015-04-18)
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** Initial version.
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** - rev. 1.1 (2015-05-04)
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** Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
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** - rev. 1.2 (2015-08-11)
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** Correct clock configuration.
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** - rev. 1.3 (2015-08-20)
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** Align with RM Rev.1.
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** - rev. 1.4 (2015-08-28)
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** Update LPUART to add FIFO.
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** - rev. 1.5 (2015-09-24)
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** Update to align with RM Rev.1.2.
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**
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** ###################################################################
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*/
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#ifndef _SYSTEM_MKL82Z7_H_
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#define _SYSTEM_MKL82Z7_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#include <stdint.h>
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#ifndef DISABLE_WDOG
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#define DISABLE_WDOG 1
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#endif
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/* MCG mode constants */
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#define MCG_MODE_FEI 0U
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#define MCG_MODE_FBI 1U
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#define MCG_MODE_BLPI 2U
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#define MCG_MODE_FEE 3U
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#define MCG_MODE_FBE 4U
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#define MCG_MODE_BLPE 5U
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#define MCG_MODE_PBE 6U
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#define MCG_MODE_PEE 7U
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/* Predefined clock setups
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0 ... Default part configuration
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Multipurpose Clock Generator (MCG) in FEI mode.
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Reference clock source for MCG module: Slow internal reference clock
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Core clock = 20.97152MHz
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Bus clock = 20.97152MHz
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1 ... Maximal speed configuration
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Multipurpose Clock Generator (MCG) in PEE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 96MHz
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Bus clock = 24MHz
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2 ... Chip internally clocked, ready for Very Low Power Run mode.
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Multipurpose Clock Generator (MCG) in BLPI mode.
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Reference clock source for MCG module: Fast internal reference clock
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Core clock = 4MHz
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Bus clock = 4MHz
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3 ... Chip externally clocked, ready for Very Low Power Run mode.
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Multipurpose Clock Generator (MCG) in BLPE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 4MHz
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Bus clock = 4MHz
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4 ... USB clock setup
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Multipurpose Clock Generator (MCG) in PEE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 96MHz
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Bus clock = 24MHz
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5 ... Maximum achievable clock frequency configuration in RUN mode
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Multipurpose Clock Generator (MCG) in PEE mode.
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Reference clock source for MCG module: System oscillator 0 reference clock
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Core clock = 72MHz
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Bus clock = 24MHz
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*/
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/* Define clock source values */
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#define CPU_XTAL_CLK_HZ \
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12000000U
/* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
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#define CPU_XTAL32k_CLK_HZ \
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32768U
/* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
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*/
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#define CPU_INT_SLOW_CLK_HZ 32768U
/* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000U
/* Value of the fast internal oscillator clock frequency in Hz */
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#define CPU_INT_IRC_CLK_HZ 48000000U
/* Value of the 48M internal oscillator clock frequency in Hz */
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/* RTC oscillator setting */
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/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
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#define SYSTEM_RTC_CR_VALUE 0x0300U
/* RTC_CR */
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/* Low power mode enable */
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/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
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#define SYSTEM_SMC_PMPROT_VALUE 0xAAU
/* SMC_PMPROT */
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/* Internal reference clock trim */
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/* #undef SLOW_TRIM_ADDRESS */
/* Slow oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef SLOW_FINE_TRIM_ADDRESS */
/* Slow oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef FAST_TRIM_ADDRESS */
/* Fast oscillator not trimmed. Commented out for MISRA compliance. */
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/* #undef FAST_FINE_TRIM_ADDRESS */
/* Fast oscillator not trimmed. Commented out for MISRA compliance. */
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#ifdef CLOCK_SETUP
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#if (CLOCK_SETUP == 0)
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#define DEFAULT_SYSTEM_CLOCK 20971520U
/* Default System clock value */
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#define MCG_MODE MCG_MODE_FEI
/* Clock generator mode */
168
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
169
#define SYSTEM_MCG_C1_VALUE 0x06U
/* MCG_C1 */
170
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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#define SYSTEM_MCG_C2_VALUE 0x24U
/* MCG_C2 */
172
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
173
#define SYSTEM_MCG_C4_VALUE 0x00U
/* MCG_C4 */
174
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U
/* MCG_SC */
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/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
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#define SYSTEM_MCG_C5_VALUE 0x00U
/* MCG_C5 */
178
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
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#define SYSTEM_MCG_C6_VALUE 0x00U
/* MCG_C6 */
180
/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U
/* MCG_C7 */
182
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x80U
/* OSC_CR */
184
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x00U
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1,OUTDIV5=1 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x00011000U
/* SIM_CLKDIV1 */
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/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
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#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U
/* SIM_CLKDIV3 */
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/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U
/* SIM_SOPT1 */
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/* SIM_SOPT2:
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* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
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*/
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#define SYSTEM_SIM_SOPT2_VALUE 0x01000000U
/* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 1)
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#define DEFAULT_SYSTEM_CLOCK 96000000U
/* Default System clock value */
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#define MCG_MODE MCG_MODE_PEE
/* Clock generator mode */
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/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x22U
/* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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#define SYSTEM_MCG_C2_VALUE 0x24U
/* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U
/* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U
/* MCG_SC */
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/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
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#define SYSTEM_MCG_C5_VALUE 0x00U
/* MCG_C5 */
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/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
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#define SYSTEM_MCG_C6_VALUE 0x40U
/* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U
/* MCG_C7 */
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/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x80U
/* OSC_CR */
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/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x60U
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U
/* SIM_CLKDIV1 */
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/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
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#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U
/* SIM_CLKDIV3 */
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/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U
/* SIM_SOPT1 */
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/* SIM_SOPT2:
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* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
225
*/
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#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U
/* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 2)
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#define DEFAULT_SYSTEM_CLOCK 4000000U
/* Default System clock value */
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#define MCG_MODE MCG_MODE_BLPI
/* Clock generator mode */
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/* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0x46U
/* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
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#define SYSTEM_MCG_C2_VALUE 0x27U
/* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U
/* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x00U
/* MCG_SC */
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/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
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#define SYSTEM_MCG_C5_VALUE 0x00U
/* MCG_C5 */
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/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
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#define SYSTEM_MCG_C6_VALUE 0x00U
/* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U
/* MCG_C7 */
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/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x80U
/* OSC_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x00U
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=4,OUTDIV5=0 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x03040000U
/* SIM_CLKDIV1 */
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/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
251
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U
/* SIM_CLKDIV3 */
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/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U
/* SIM_SOPT1 */
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/* SIM_SOPT2:
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* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
256
*/
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#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U
/* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 3)
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#define DEFAULT_SYSTEM_CLOCK 4000000U
/* Default System clock value */
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#define MCG_MODE MCG_MODE_BLPE
/* Clock generator mode */
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/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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#define SYSTEM_MCG_C1_VALUE 0xA2U
/* MCG_C1 */
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/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
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#define SYSTEM_MCG_C2_VALUE 0x27U
/* MCG_C2 */
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/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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#define SYSTEM_MCG_C4_VALUE 0x00U
/* MCG_C4 */
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/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
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#define SYSTEM_MCG_SC_VALUE 0x02U
/* MCG_SC */
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/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
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#define SYSTEM_MCG_C5_VALUE 0x00U
/* MCG_C5 */
271
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
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#define SYSTEM_MCG_C6_VALUE 0x00U
/* MCG_C6 */
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/* MCG_C7: OSCSEL=0 */
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#define SYSTEM_MCG_C7_VALUE 0x00U
/* MCG_C7 */
275
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define SYSTEM_OSC_CR_VALUE 0x80U
/* OSC_CR */
277
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SYSTEM_SMC_PMCTRL_VALUE 0x00U
/* SMC_PMCTRL */
279
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0x0B */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U
/* SIM_CLKDIV1 */
281
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
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#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U
/* SIM_CLKDIV3 */
283
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U
/* SIM_SOPT1 */
285
/* SIM_SOPT2:
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* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
287
*/
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#define SYSTEM_SIM_SOPT2_VALUE 0x01030000U
/* SIM_SOPT2 */
289
#elif(CLOCK_SETUP == 4)
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#define DEFAULT_SYSTEM_CLOCK 96000000U
/* Default System clock value */
291
#define MCG_MODE MCG_MODE_PEE
/* Clock generator mode */
292
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
293
#define SYSTEM_MCG_C1_VALUE 0x22U
/* MCG_C1 */
294
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
295
#define SYSTEM_MCG_C2_VALUE 0x24U
/* MCG_C2 */
296
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
297
#define SYSTEM_MCG_C4_VALUE 0x00U
/* MCG_C4 */
298
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
299
#define SYSTEM_MCG_SC_VALUE 0x00U
/* MCG_SC */
300
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
301
#define SYSTEM_MCG_C5_VALUE 0x00U
/* MCG_C5 */
302
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0 */
303
#define SYSTEM_MCG_C6_VALUE 0x40U
/* MCG_C6 */
304
/* MCG_C7: OSCSEL=0 */
305
#define SYSTEM_MCG_C7_VALUE 0x00U
/* MCG_C7 */
306
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
307
#define SYSTEM_OSC_CR_VALUE 0x80U
/* OSC_CR */
308
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
309
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U
/* SMC_PMCTRL */
310
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=3,OUTDIV4=3,OUTDIV5=0 */
311
#define SYSTEM_SIM_CLKDIV1_VALUE 0x03030000U
/* SIM_CLKDIV1 */
312
/* SIM_CLKDIV2: USBDIV=3,USBFRAC=0 */
313
#define SYSTEM_SIM_CLKDIV2_VALUE 0x03U
/* SIM_CLKDIV2 */
314
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
315
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U
/* SIM_CLKDIV3 */
316
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
317
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U
/* SIM_SOPT1 */
318
/* SIM_SOPT2:
319
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
320
*/
321
#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U
/* SIM_SOPT2 */
322
#elif(CLOCK_SETUP == 5)
323
#define DEFAULT_SYSTEM_CLOCK 72000000U
/* Default System clock value */
324
#define MCG_MODE MCG_MODE_PEE
/* Clock generator mode */
325
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
326
#define SYSTEM_MCG_C1_VALUE 0x22U
/* MCG_C1 */
327
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
328
#define SYSTEM_MCG_C2_VALUE 0x24U
/* MCG_C2 */
329
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
330
#define SYSTEM_MCG_C4_VALUE 0x00U
/* MCG_C4 */
331
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
332
#define SYSTEM_MCG_SC_VALUE 0x00U
/* MCG_SC */
333
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
334
#define SYSTEM_MCG_C5_VALUE 0x01U
/* MCG_C5 */
335
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=8 */
336
#define SYSTEM_MCG_C6_VALUE 0x48U
/* MCG_C6 */
337
/* MCG_C7: OSCSEL=0 */
338
#define SYSTEM_MCG_C7_VALUE 0x00U
/* MCG_C7 */
339
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
340
#define SYSTEM_OSC_CR_VALUE 0x80U
/* OSC_CR */
341
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
342
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U
/* SMC_PMCTRL */
343
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=2,OUTDIV4=2,OUTDIV5=0 */
344
#define SYSTEM_SIM_CLKDIV1_VALUE 0x02020000U
/* SIM_CLKDIV1 */
345
/* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
346
#define SYSTEM_SIM_CLKDIV3_VALUE 0x00U
/* SIM_CLKDIV3 */
347
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
348
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U
/* SIM_SOPT1 */
349
/* SIM_SOPT2:
350
* EMVSIMSRC=0,SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,FLEXIOSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0
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*/
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#define SYSTEM_SIM_SOPT2_VALUE 0x01010000U
/* SIM_SOPT2 */
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#endif
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#else
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#define DEFAULT_SYSTEM_CLOCK 20971520u
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#endif
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extern
uint32_t SystemCoreClock;
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void
SystemInit(
void
);
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385
void
SystemCoreClockUpdate(
void
);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* _SYSTEM_MKL82Z7_H_ */
apps
flash_driver_api
MKL82Z7
src
startup
system_MKL82Z7.h
Generated on Mon Mar 7 2016 16:48:23 for Kinetis Bootloader by
1.8.11
1.8.11 
