Kinetis Bootloader
2.0.0
Common bootloader for Kinetis devices
Introduction
Related Pages
Modules
system_MKL43Z4.h
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/*
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** ###################################################################
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** Processors: MKL43Z256VLH4
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** MKL43Z128VLH4
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** MKL43Z64VLH4
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** MKL43Z256VMP4
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** MKL43Z128VMP4
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** MKL43Z64VMP4
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**
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** GNU C Compiler - CodeSourcery Sourcery G++
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** IAR ANSI C/C++ Compiler for ARM
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**
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** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
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** Version: rev. 1.5, 2014-09-05
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** Build: b141218
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright (c) 2014 Freescale Semiconductor, Inc.
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 1.0 (2014-03-27)
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** Initial version.
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** - rev. 1.1 (2014-05-26)
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** I2S registers TCR2/RCR2 and others were changed.
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** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
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** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.:
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*FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
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** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
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** Clock configuration for high range external oscillator has been added.
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** RFSYS module access has been added.
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** - rev. 1.2 (2014-07-10)
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** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
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** UART0 - UART0 module renamed to UART2.
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** I2S - removed MDR register.
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** - rev. 1.3 (2014-08-21)
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** UART2 - Removed ED register.
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** UART2 - Removed MODEM register.
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** UART2 - Removed IR register.
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** UART2 - Removed PFIFO register.
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** UART2 - Removed CFIFO register.
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** UART2 - Removed SFIFO register.
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** UART2 - Removed TWFIFO register.
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** UART2 - Removed TCFIFO register.
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** UART2 - Removed RWFIFO register.
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** UART2 - Removed RCFIFO register.
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** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
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** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
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** SIM - Removed bitfield DIEID in SDID register.
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** - rev. 1.4 (2014-09-01)
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** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
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** USB - USB0_CTL1 was renamed to USB0_CTL register.
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** - rev. 1.5 (2014-09-05)
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** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
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**
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** ###################################################################
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*/
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#ifndef _SYSTEM_MKL43Z4_H_
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#define _SYSTEM_MKL43Z4_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#include <stdint.h>
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#ifndef DISABLE_WDOG
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#define DISABLE_WDOG 1
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#endif
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#define ACK_ISOLATION 1
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/* MCG_Lite mode constants */
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#define MCG_MODE_LIRC_8M 0U
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#define MCG_MODE_HIRC 1U
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#define MCG_MODE_LIRC_2M 2U
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#define MCG_MODE_EXT 3U
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/* Predefined clock setups
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0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
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Default part configuration.
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Core clock/Bus clock derived from the internal clock source 8 MHz
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Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
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derivatived with USB)
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1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
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Maximum achievable clock frequency configuration using internal clock.
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Core clock/Bus clock derived from the internal clock source 48MHz
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Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
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derivatived with USB)
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2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
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Core clock/Bus clock derived directly from the external crystal 32.768kHz
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The clock settings is ready for Very Low Power Run mode.
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Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable
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only for derivatived with USB)
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3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
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Core clock/Bus clock derived from the internal clock source 2 MHz
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The clock settings is ready for Very Low Power Run mode.
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Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
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derivatived with USB)
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4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
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USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
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Core clock/Bus clock derived from the internal clock source 48MHz
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Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
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5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
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Core clock/Bus clock derived directly from the external crystal 8 MHz
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Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
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derivatived with USB)
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*/
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/* Define clock source values */
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#define CPU_XTAL_CLK_HZ 32768u
/* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 48000000u
/* Value of the fast internal oscillator clock frequency in Hz */
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#define CPU_INT_IRC_CLK_HZ 48000000u
/* Value of the 48M internal oscillator clock frequency in Hz */
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/* Low power mode enable */
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/* SMC_PMPROT: AVLP=1,AVLLS=1 */
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#define SYSTEM_SMC_PMPROT_VALUE 0x2Au
/* SMC_PMPROT */
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#ifdef CLOCK_SETUP
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#if (CLOCK_SETUP == 0)
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#define DEFAULT_SYSTEM_CLOCK 4000000u
/* Default System clock value */
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#define CPU_INT_SLOW_CLK_HZ 8000000u
/* Value of the slow internal oscillator clock frequency in Hz */
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#define MCG_MODE MCG_MODE_LIRC_8M
/* Clock generator mode */
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/* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
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#define MCG_C1_VALUE 0x42u
/* MCG_C1 */
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/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
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#define MCG_C2_VALUE 0x01u
/* MCG_C2 */
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/* MCG_SC: FCRDIV=0 */
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#define MCG_SC_VALUE 0x00u
/* MCG_SC */
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/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
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#define MCG_MC_VALUE 0x00u
/* MCG_MC */
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/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define OSC0_CR_VALUE 0x00u
/* OSC0_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SMC_PMCTRL_VALUE 0x00u
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u
/* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u
/* SIM_SOPT1 */
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/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u
/* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 1)
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#define DEFAULT_SYSTEM_CLOCK 48000000u
/* Default System clock value */
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#define CPU_INT_SLOW_CLK_HZ 8000000u
/* Value of the slow internal oscillator clock frequency in Hz */
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#define MCG_MODE MCG_MODE_HIRC
/* Clock generator mode */
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/* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
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#define MCG_C1_VALUE 0x00u
/* MCG_C1 */
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/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
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#define MCG_C2_VALUE 0x01u
/* MCG_C2 */
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/* MCG_SC: FCRDIV=0 */
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#define MCG_SC_VALUE 0x00u
/* MCG_SC */
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/* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
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#define MCG_MC_VALUE 0x80u
/* MCG_MC */
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/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define OSC0_CR_VALUE 0x00u
/* OSC0_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SMC_PMCTRL_VALUE 0x00u
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u
/* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u
/* SIM_SOPT1 */
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/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x03000000U
/* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 2)
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#define DEFAULT_SYSTEM_CLOCK 32768u
/* Default System clock value */
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#define CPU_INT_SLOW_CLK_HZ 8000000u
/* Value of the slow internal oscillator clock frequency in Hz */
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#define MCG_MODE MCG_MODE_EXT
/* Clock generator mode */
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/* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
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#define MCG_C1_VALUE 0x82u
/* MCG_C1 */
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/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
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#define MCG_C2_VALUE 0x05u
/* MCG_C2 */
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/* MCG_SC: FCRDIV=0 */
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#define MCG_SC_VALUE 0x00u
/* MCG_SC */
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/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
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#define MCG_MC_VALUE 0x00u
/* MCG_MC */
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/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define OSC0_CR_VALUE 0x80u
/* OSC0_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SMC_PMCTRL_VALUE 0x00u
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x00u
/* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u
/* SIM_SOPT1 */
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/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x02000000u
/* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 3)
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#define DEFAULT_SYSTEM_CLOCK 2000000u
/* Default System clock value */
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#define CPU_INT_SLOW_CLK_HZ 2000000u
/* Value of the slow internal oscillator clock frequency in Hz */
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#define MCG_MODE MCG_MODE_LIRC_2M
/* Clock generator mode */
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/* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
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#define MCG_C1_VALUE 0x42u
/* MCG_C1 */
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/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
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#define MCG_C2_VALUE 0x00u
/* MCG_C2 */
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/* MCG_SC: FCRDIV=0 */
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#define MCG_SC_VALUE 0x00u
/* MCG_SC */
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/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
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#define MCG_MC_VALUE 0x00u
/* MCG_MC */
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/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define OSC0_CR_VALUE 0x00u
/* OSC0_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SMC_PMCTRL_VALUE 0x00u
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u
/* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u
/* SIM_SOPT1 */
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/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u
/* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 4)
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#define DEFAULT_SYSTEM_CLOCK 2000000u
/* Default System clock value */
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#define CPU_INT_SLOW_CLK_HZ 8000000u
/* Value of the slow internal oscillator clock frequency in Hz */
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#define MCG_MODE MCG_MODE_LIRC_2M
/* Clock generator mode */
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/* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
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#define MCG_C1_VALUE 0x02u
/* MCG_C1 */
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/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
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#define MCG_C2_VALUE 0x01u
/* MCG_C2 */
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/* MCG_SC: FCRDIV=0 */
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#define MCG_SC_VALUE 0x00u
/* MCG_SC */
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/* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
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#define MCG_MC_VALUE 0x80u
/* MCG_MC */
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/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define OSC0_CR_VALUE 0x00u
/* OSC0_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SMC_PMCTRL_VALUE 0x00u
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u
/* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u
/* SIM_SOPT1 */
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/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x03040000u
/* SIM_SOPT2 */
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#elif(CLOCK_SETUP == 5)
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#define DEFAULT_SYSTEM_CLOCK 2000000u
/* Default System clock value */
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#define CPU_INT_SLOW_CLK_HZ 2000000u
/* Value of the slow internal oscillator clock frequency in Hz */
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#define MCG_MODE MCG_MODE_LIRC_2M
/* Clock generator mode */
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/* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
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#define MCG_C1_VALUE 0x80u
/* MCG_C1 */
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/* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
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#define MCG_C2_VALUE 0x15u
/* MCG_C2 */
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/* MCG_SC: FCRDIV=0 */
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#define MCG_SC_VALUE 0x00u
/* MCG_SC */
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/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
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#define MCG_MC_VALUE 0x00u
/* MCG_MC */
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/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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#define OSC0_CR_VALUE 0x80u
/* OSC0_CR */
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/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
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#define SMC_PMCTRL_VALUE 0x00u
/* SMC_PMCTRL */
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
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#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u
/* SIM_CLKDIV1 */
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/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
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#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u
/* SIM_SOPT1 */
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/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
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#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u
/* SIM_SOPT2 */
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#else
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#error The selected clock setup is not supported.
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#endif
/* (CLOCK_SETUP == 5) */
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#else
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#define DEFAULT_SYSTEM_CLOCK 8000000u
/* Default System clock value */
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#define CPU_INT_SLOW_CLK_HZ 8000000u
/* Value of the slow internal oscillator clock frequency in Hz */
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#endif
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extern
uint32_t SystemCoreClock;
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327
void
SystemInit(
void
);
328
336
void
SystemCoreClockUpdate(
void
);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* #if !defined(_SYSTEM_MKL43Z4_H_) */
apps
flash_driver_api
MKL43Z4
src
startup
system_MKL43Z4.h
Generated on Mon Mar 7 2016 16:48:23 for Kinetis Bootloader by
1.8.11
1.8.11 
