Kinetis Bootloader  2.0.0
Common bootloader for Kinetis devices
system_MKL33Z644.h
1 /*
2 ** ###################################################################
3 ** Processors: MKL33Z64VFT4
4 ** MKL33Z32VFT4
5 ** MKL33Z64VLH4
6 ** MKL33Z32VLH4
7 ** MKL33Z64VLK4
8 ** MKL33Z32VLK4
9 ** MKL33Z64VMP4
10 ** MKL33Z32VMP4
11 **
12 ** Compilers: Keil ARM C/C++ Compiler
13 ** Freescale C/C++ for Embedded ARM
14 ** GNU C Compiler
15 ** GNU C Compiler - CodeSourcery Sourcery G++
16 ** IAR ANSI C/C++ Compiler for ARM
17 **
18 ** Reference manual: KL33P80M48SF3RM, Rev.2, March 2015
19 ** Version: rev. 1.1, 2015-03-11
20 ** Build: b150319
21 **
22 ** Abstract:
23 ** Provides a system configuration function and a global variable that
24 ** contains the system frequency. It configures the device and initializes
25 ** the oscillator (PLL) that is part of the microcontroller device.
26 **
27 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
28 ** All rights reserved.
29 **
30 ** Redistribution and use in source and binary forms, with or without modification,
31 ** are permitted provided that the following conditions are met:
32 **
33 ** o Redistributions of source code must retain the above copyright notice, this list
34 ** of conditions and the following disclaimer.
35 **
36 ** o Redistributions in binary form must reproduce the above copyright notice, this
37 ** list of conditions and the following disclaimer in the documentation and/or
38 ** other materials provided with the distribution.
39 **
40 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
41 ** contributors may be used to endorse or promote products derived from this
42 ** software without specific prior written permission.
43 **
44 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
45 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
46 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
47 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
48 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
51 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
53 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 **
55 ** http: www.freescale.com
56 ** mail: support@freescale.com
57 **
58 ** Revisions:
59 ** - rev. 1.0 (2014-09-24)
60 ** Initial version.
61 ** - rev. 1.1 (2015-03-11)
62 ** Update Reference Manual information and add part numbers.
63 **
64 ** ###################################################################
65 */
66 
78 #ifndef _SYSTEM_MKL33Z644_H_
79 #define _SYSTEM_MKL33Z644_H_
81 #ifdef __cplusplus
82 extern "C" {
83 #endif
84 
85 #include <stdint.h>
86 
87 #ifndef DISABLE_WDOG
88 #define DISABLE_WDOG 1
89 #endif
90 
91 #define ACK_ISOLATION 1
92 
93 #ifndef CLOCK_SETUP
94 #define CLOCK_SETUP 1
95 #endif
96 
97 /* MCG_Lite mode constants */
98 
99 #define MCG_MODE_LIRC_8M 0U
100 #define MCG_MODE_HIRC 1U
101 #define MCG_MODE_LIRC_2M 2U
102 #define MCG_MODE_EXT 3U
103 
104 /* Predefined clock setups
105  0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
106  Default part configuration.
107  Core clock/Bus clock derived from the internal clock source 8 MHz
108  Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
109  derivatived with USB)
110  1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
111  Maximum achievable clock frequency configuration using internal clock.
112  Core clock/Bus clock derived from the internal clock source 48MHz
113  Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
114  derivatived with USB)
115  2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
116  Core clock/Bus clock derived directly from the external crystal 32.768kHz
117  The clock settings is ready for Very Low Power Run mode.
118  Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable
119  only for derivatived with USB)
120  3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
121  Core clock/Bus clock derived from the internal clock source 2 MHz
122  The clock settings is ready for Very Low Power Run mode.
123  Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
124  derivatived with USB)
125  5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
126  Core clock/Bus clock derived directly from the external crystal 8 MHz
127  Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
128  derivatived with USB)
129 */
130 
131 /* Define clock source values */
132 
133 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
134 #define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */
135 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
136 
137 /* Low power mode enable */
138 /* SMC_PMPROT: AVLP=1,AVLLS=1 */
139 #define SMC_PMPROT_VALUE 0x2Au /* SMC_PMPROT */
140 
141 #if (CLOCK_SETUP == 0)
142 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
143 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
144 #define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */
145 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
146 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
147 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
148 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
149 /* MCG_SC: FCRDIV=0 */
150 #define MCG_SC_VALUE 0x00u /* MCG_SC */
151 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
152 #define MCG_MC_VALUE 0x00u /* MCG_MC */
153 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
154 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
155 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
156 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
157 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
158 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */
159 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
160 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
161 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
162 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
163 #elif(CLOCK_SETUP == 1)
164 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
165 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
166 #define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */
167 /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
168 #define MCG_C1_VALUE 0x00u /* MCG_C1 */
169 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
170 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
171 /* MCG_SC: FCRDIV=0 */
172 #define MCG_SC_VALUE 0x00u /* MCG_SC */
173 /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
174 #define MCG_MC_VALUE 0x80u /* MCG_MC */
175 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
176 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
177 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
178 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
179 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
180 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
181 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
182 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
183 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
184 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */
185 #elif(CLOCK_SETUP == 2)
186 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
187 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
188 #define MCG_MODE MCG_MODE_EXT /* Clock generator mode */
189 /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
190 #define MCG_C1_VALUE 0x82u /* MCG_C1 */
191 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
192 #define MCG_C2_VALUE 0x05u /* MCG_C2 */
193 /* MCG_SC: FCRDIV=0 */
194 #define MCG_SC_VALUE 0x00u /* MCG_SC */
195 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
196 #define MCG_MC_VALUE 0x00u /* MCG_MC */
197 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
198 #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
199 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
200 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
201 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
202 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */
203 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
204 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
205 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
206 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */
207 #elif(CLOCK_SETUP == 3)
208 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
209 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
210 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
211 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
212 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
213 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
214 #define MCG_C2_VALUE 0x00u /* MCG_C2 */
215 /* MCG_SC: FCRDIV=0 */
216 #define MCG_SC_VALUE 0x00u /* MCG_SC */
217 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
218 #define MCG_MC_VALUE 0x00u /* MCG_MC */
219 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
220 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
221 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
222 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
223 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
224 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
225 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
226 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
227 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
228 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
229 #elif(CLOCK_SETUP == 5)
230 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
231 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
232 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
233 /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
234 #define MCG_C1_VALUE 0x80u /* MCG_C1 */
235 /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
236 #define MCG_C2_VALUE 0x15u /* MCG_C2 */
237 /* MCG_SC: FCRDIV=0 */
238 #define MCG_SC_VALUE 0x00u /* MCG_SC */
239 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
240 #define MCG_MC_VALUE 0x00u /* MCG_MC */
241 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
242 #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
243 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
244 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
245 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
246 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
247 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
248 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
249 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
250 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
251 #else
252 #error The selected clock setup is not supported.
253 #endif /* (CLOCK_SETUP == 5) */
254 
264 extern uint32_t SystemCoreClock;
265 
273 void SystemInit(void);
274 
282 void SystemCoreClockUpdate(void);
283 
284 #ifdef __cplusplus
285 }
286 #endif
287 
288 #endif /* #if !defined(_SYSTEM_MKL33Z644_H_) */