Kinetis Bootloader  2.0.0
Common bootloader for Kinetis devices
system_MKL27Z644.h
1 /*
2 ** ###################################################################
3 ** Processors: MKL27Z64VDA4
4 ** MKL27Z32VDA4
5 ** MKL27Z64VFM4
6 ** MKL27Z32VFM4
7 ** MKL27Z64VFT4
8 ** MKL27Z32VFT4
9 ** MKL27Z64VLH4
10 ** MKL27Z32VLH4
11 ** MKL27Z64VMP4
12 ** MKL27Z32VMP4
13 **
14 ** Compilers: Keil ARM C/C++ Compiler
15 ** Freescale C/C++ for Embedded ARM
16 ** GNU C Compiler
17 ** GNU C Compiler - CodeSourcery Sourcery G++
18 ** IAR ANSI C/C++ Compiler for ARM
19 **
20 ** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014
21 ** Version: rev. 1.4, 2014-09-22
22 ** Build: b141218
23 **
24 ** Abstract:
25 ** Provides a system configuration function and a global variable that
26 ** contains the system frequency. It configures the device and initializes
27 ** the oscillator (PLL) that is part of the microcontroller device.
28 **
29 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
30 ** All rights reserved.
31 **
32 ** Redistribution and use in source and binary forms, with or without modification,
33 ** are permitted provided that the following conditions are met:
34 **
35 ** o Redistributions of source code must retain the above copyright notice, this list
36 ** of conditions and the following disclaimer.
37 **
38 ** o Redistributions in binary form must reproduce the above copyright notice, this
39 ** list of conditions and the following disclaimer in the documentation and/or
40 ** other materials provided with the distribution.
41 **
42 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
43 ** contributors may be used to endorse or promote products derived from this
44 ** software without specific prior written permission.
45 **
46 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
47 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
48 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
49 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
50 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
52 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
53 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
54 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
55 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 **
57 ** http: www.freescale.com
58 ** mail: support@freescale.com
59 **
60 ** Revisions:
61 ** - rev. 1.0 (2014-05-12)
62 ** Initial version.
63 ** - rev. 1.1 (2014-07-10)
64 ** UART0 - UART0 module renamed to UART2.
65 ** - rev. 1.2 (2014-08-12)
66 ** CRC - CRC register renamed to DATA.
67 ** - rev. 1.3 (2014-09-02)
68 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
69 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
70 ** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register.
71 ** - rev. 1.4 (2014-09-22)
72 ** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
73 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
74 ** SIM - Removed bitfield DIEID in SDID register.
75 ** UART2 - Removed ED register.
76 ** UART2 - Removed MODEM register.
77 ** UART2 - Removed IR register.
78 ** UART2 - Removed PFIFO register.
79 ** UART2 - Removed CFIFO register.
80 ** UART2 - Removed SFIFO register.
81 ** UART2 - Removed TWFIFO register.
82 ** UART2 - Removed TCFIFO register.
83 ** UART2 - Removed RWFIFO register.
84 ** UART2 - Removed RCFIFO register.
85 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
86 ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
87 **
88 ** ###################################################################
89 */
90 
102 #ifndef _SYSTEM_MKL27Z644_H_
103 #define _SYSTEM_MKL27Z644_H_
105 #ifdef __cplusplus
106 extern "C" {
107 #endif
108 
109 #include <stdint.h>
110 
111 #ifndef DISABLE_WDOG
112 #define DISABLE_WDOG 1
113 #endif
114 
115 #define ACK_ISOLATION 1
116 
117 /* MCG_Lite mode constants */
118 
119 #define MCG_MODE_LIRC_8M 0U
120 #define MCG_MODE_HIRC 1U
121 #define MCG_MODE_LIRC_2M 2U
122 #define MCG_MODE_EXT 3U
123 
124 /* Predefined clock setups
125  0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
126  Default part configuration.
127  Core clock/Bus clock derived from the internal clock source 8 MHz
128  Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
129  derivatived with USB)
130  1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
131  Maximum achievable clock frequency configuration using internal clock.
132  Core clock/Bus clock derived from the internal clock source 48MHz
133  Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
134  derivatived with USB)
135  2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
136  Core clock/Bus clock derived directly from the external crystal 32.768kHz
137  The clock settings is ready for Very Low Power Run mode.
138  Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable
139  only for derivatived with USB)
140  3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
141  Core clock/Bus clock derived from the internal clock source 2 MHz
142  The clock settings is ready for Very Low Power Run mode.
143  Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
144  derivatived with USB)
145  4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
146  USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
147  Core clock/Bus clock derived from the internal clock source 48MHz
148  Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
149  5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
150  Core clock/Bus clock derived directly from the external crystal 8 MHz
151  Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for
152  derivatived with USB)
153 */
154 
155 /* Define clock source values */
156 
157 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
158 #define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */
159 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
160 
161 /* Low power mode enable */
162 /* SMC_PMPROT: AVLP=1,AVLLS=1 */
163 #define SYSTEM_SMC_PMPROT_VALUE 0x2Au /* SMC_PMPROT */
164 
165 #ifdef CLOCK_SETUP
166 #if (CLOCK_SETUP == 0)
167 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
168 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
169 #define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */
170 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
171 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
172 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
173 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
174 /* MCG_SC: FCRDIV=0 */
175 #define MCG_SC_VALUE 0x00u /* MCG_SC */
176 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
177 #define MCG_MC_VALUE 0x00u /* MCG_MC */
178 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
179 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
180 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
181 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
182 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
183 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */
184 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
185 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
186 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
187 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
188 #elif(CLOCK_SETUP == 1)
189 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
190 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
191 #define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */
192 /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
193 #define MCG_C1_VALUE 0x00u /* MCG_C1 */
194 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
195 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
196 /* MCG_SC: FCRDIV=0 */
197 #define MCG_SC_VALUE 0x00u /* MCG_SC */
198 /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
199 #define MCG_MC_VALUE 0x80u /* MCG_MC */
200 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
201 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
202 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
203 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
204 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
205 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
206 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
207 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
208 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
209 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */
210 #elif(CLOCK_SETUP == 2)
211 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
212 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
213 #define MCG_MODE MCG_MODE_EXT /* Clock generator mode */
214 /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
215 #define MCG_C1_VALUE 0x82u /* MCG_C1 */
216 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
217 #define MCG_C2_VALUE 0x05u /* MCG_C2 */
218 /* MCG_SC: FCRDIV=0 */
219 #define MCG_SC_VALUE 0x00u /* MCG_SC */
220 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
221 #define MCG_MC_VALUE 0x00u /* MCG_MC */
222 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
223 #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
224 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
225 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
226 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
227 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */
228 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
229 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
230 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
231 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */
232 #elif(CLOCK_SETUP == 3)
233 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
234 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
235 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
236 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
237 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
238 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
239 #define MCG_C2_VALUE 0x00u /* MCG_C2 */
240 /* MCG_SC: FCRDIV=0 */
241 #define MCG_SC_VALUE 0x00u /* MCG_SC */
242 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
243 #define MCG_MC_VALUE 0x00u /* MCG_MC */
244 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
245 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
246 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
247 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
248 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
249 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
250 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
251 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
252 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
253 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
254 #elif(CLOCK_SETUP == 4)
255 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
256 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
257 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
258 /* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
259 #define MCG_C1_VALUE 0x02u /* MCG_C1 */
260 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
261 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
262 /* MCG_SC: FCRDIV=0 */
263 #define MCG_SC_VALUE 0x00u /* MCG_SC */
264 /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
265 #define MCG_MC_VALUE 0x80u /* MCG_MC */
266 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
267 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
268 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
269 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
270 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
271 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
272 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
273 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
274 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
275 #define SYSTEM_SIM_SOPT2_VALUE 0x03040000u /* SIM_SOPT2 */
276 #elif(CLOCK_SETUP == 5)
277 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
278 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
279 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
280 /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
281 #define MCG_C1_VALUE 0x80u /* MCG_C1 */
282 /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
283 #define MCG_C2_VALUE 0x15u /* MCG_C2 */
284 /* MCG_SC: FCRDIV=0 */
285 #define MCG_SC_VALUE 0x00u /* MCG_SC */
286 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
287 #define MCG_MC_VALUE 0x00u /* MCG_MC */
288 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
289 #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
290 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
291 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
292 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
293 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
294 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
295 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
296 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
297 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
298 #else
299 #error The selected clock setup is not supported.
300 #endif /* (CLOCK_SETUP == 5) */
301 #else
302 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
303 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
304 #endif
305 
315 extern uint32_t SystemCoreClock;
316 
324 void SystemInit(void);
325 
333 void SystemCoreClockUpdate(void);
334 
335 #ifdef __cplusplus
336 }
337 #endif
338 
339 #endif /* #if !defined(_SYSTEM_MKL27Z644_H_) */