Kinetis Bootloader  2.0.0
Common bootloader for Kinetis devices
system_MKL03Z4.h
1 /*
2 ** ###################################################################
3 ** Processors: MKL03Z32CAF4
4 ** MKL03Z32VFG4
5 ** MKL03Z16VFG4
6 ** MKL03Z8VFG4
7 ** MKL03Z32VFK4
8 ** MKL03Z16VFK4
9 ** MKL03Z8VFK4
10 **
11 ** Compilers: Keil ARM C/C++ Compiler
12 ** Freescale C/C++ for Embedded ARM
13 ** GNU C Compiler
14 ** GNU C Compiler - CodeSourcery Sourcery G++
15 ** IAR ANSI C/C++ Compiler for ARM
16 **
17 ** Reference manual: KL03P24M48SF0RM, Rev 2, Apr 2014
18 ** Version: rev. 1.4, 2014-08-28
19 ** Build: b150126
20 **
21 ** Abstract:
22 ** Provides a system configuration function and a global variable that
23 ** contains the system frequency. It configures the device and initializes
24 ** the oscillator (PLL) that is part of the microcontroller device.
25 **
26 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
27 ** All rights reserved.
28 **
29 ** Redistribution and use in source and binary forms, with or without modification,
30 ** are permitted provided that the following conditions are met:
31 **
32 ** o Redistributions of source code must retain the above copyright notice, this list
33 ** of conditions and the following disclaimer.
34 **
35 ** o Redistributions in binary form must reproduce the above copyright notice, this
36 ** list of conditions and the following disclaimer in the documentation and/or
37 ** other materials provided with the distribution.
38 **
39 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
40 ** contributors may be used to endorse or promote products derived from this
41 ** software without specific prior written permission.
42 **
43 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
44 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
45 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
47 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
49 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
50 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
52 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 **
54 ** http: www.freescale.com
55 ** mail: support@freescale.com
56 **
57 ** Revisions:
58 ** - rev. 1.0 (2013-12-11)
59 ** Initial version.
60 ** - rev. 1.1 (2014-04-16)
61 ** Update of the I2C module (SMBUS feature).
62 ** Update of the MCG_Light module.
63 ** Added register file system (RFSYS).
64 ** - rev. 1.2 (2014-04-30)
65 ** PEx compatibility macros has been added.
66 ** - rev. 1.3 (2014-06-27)
67 ** I2C_S1 register was renamed.
68 ** GPIO - Modules PTA,PTB renamed to GPIOA,GPIOB.
69 ** - rev. 1.4 (2014-08-28)
70 ** Update of system files - default clock configuration changed.
71 ** Update of startup files - possibility to override DefaultISR added.
72 **
73 ** ###################################################################
74 */
75 
87 #ifndef _SYSTEM_MKL03Z4_H_
88 #define _SYSTEM_MKL03Z4_H_
90 #ifdef __cplusplus
91 extern "C" {
92 #endif
93 
94 #include <stdint.h>
95 
96 #ifndef DISABLE_WDOG
97 #define DISABLE_WDOG 1
98 #endif
99 
100 #define ACK_ISOLATION 1
101 
102 /* MCG_Lite mode constants */
103 
104 #define MCG_MODE_LIRC_8M 0U
105 #define MCG_MODE_HIRC 1U
106 #define MCG_MODE_LIRC_2M 2U
107 #define MCG_MODE_EXT 3U
108 
109 /* Predefined clock setups
110  0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
111  Default part configuration.
112  Core clock/Bus clock derived from the internal clock source 8 MHz
113  Core clock = 4MHz, BusClock = 2MHz
114  1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
115  Maximum achievable clock frequency configuration using internal clock.
116  Core clock/Bus clock derived from the internal clock source 48MHz
117  Core clock = 48MHz, BusClock = 24MHz
118  2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
119  Core clock/Bus clock derived directly from the external crystal 32.768kHz
120  The clock settings is ready for Very Low Power Run mode.
121  Core clock = 32.768kHz, BusClock = 32.768kHz
122  3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
123  Core clock/Bus clock derived from the internal clock source 2 MHz
124  The clock settings is ready for Very Low Power Run mode.
125  Core clock = 2MHz, BusClock = 1MHz
126 */
127 
128 /* Define clock source values */
129 
130 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
131 #define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */
132 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
133 
134 /* Low power mode enable */
135 /* SMC_PMPROT: AVLP=1,AVLLS=1 */
136 #define SYSTEM_SMC_PMPROT_VALUE 0x22u /* SMC_PMPROT */
137 
138 #ifdef CLOCK_SETUP
139 #if (CLOCK_SETUP == 0)
140 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
141 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
142 #define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */
143 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
144 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
145 /* MCG_C2: EREFS0=0,IRCS=1 */
146 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
147 /* MCG_SC: FCRDIV=0 */
148 #define MCG_SC_VALUE 0x00u /* MCG_SC */
149 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
150 #define MCG_MC_VALUE 0x00u /* MCG_MC */
151 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
152 #define OSC_CR_VALUE 0x00u /* OSC_CR */
153 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
154 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
155 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
156 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */
157 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
158 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000U /* SIM_SOPT1 */
159 /* SIM_SOPT2: LPUART0SRC=0,TPMSRC=3,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
160 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
161 #elif(CLOCK_SETUP == 1)
162 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
163 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
164 #define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */
165 /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
166 #define MCG_C1_VALUE 0x00u /* MCG_C1 */
167 /* MCG_C2: EREFS0=0,IRCS=1 */
168 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
169 /* MCG_SC: FCRDIV=0 */
170 #define MCG_SC_VALUE 0x00u /* MCG_SC */
171 /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
172 #define MCG_MC_VALUE 0x80u /* MCG_MC */
173 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
174 #define OSC_CR_VALUE 0x00u /* OSC_CR */
175 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
176 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
177 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
178 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
179 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
180 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
181 /* SIM_SOPT2: LPUART0SRC=0,TPMSRC=3,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
182 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */
183 #elif(CLOCK_SETUP == 2)
184 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
185 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
186 #define MCG_MODE MCG_MODE_EXT /* Clock generator mode */
187 /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
188 #define MCG_C1_VALUE 0x82u /* MCG_C1 */
189 /* MCG_C2: EREFS0=1,IRCS=1 */
190 #define MCG_C2_VALUE 0x05u /* MCG_C2 */
191 /* MCG_SC: FCRDIV=0 */
192 #define MCG_SC_VALUE 0x00u /* MCG_SC */
193 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
194 #define MCG_MC_VALUE 0x00u /* MCG_MC */
195 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
196 #define OSC_CR_VALUE 0x80u /* OSC_CR */
197 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
198 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
199 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
200 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */
201 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
202 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
203 /* SIM_SOPT2: LPUART0SRC=0,TPMSRC=2,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
204 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */
205 #elif(CLOCK_SETUP == 3)
206 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
207 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
208 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
209 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
210 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
211 /* MCG_C2: EREFS0=0,IRCS=0 */
212 #define MCG_C2_VALUE 0x00u /* MCG_C2 */
213 /* MCG_SC: FCRDIV=0 */
214 #define MCG_SC_VALUE 0x00u /* MCG_SC */
215 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
216 #define MCG_MC_VALUE 0x00u /* MCG_MC */
217 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
218 #define OSC_CR_VALUE 0x00u /* OSC_CR */
219 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
220 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
221 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
222 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
223 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
224 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000U /* SIM_SOPT1 */
225 /* SIM_SOPT2: LPUART0SRC=0,TPMSRC=3,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
226 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
227 #else
228 #error The selected clock setup is not supported.
229 #endif
230 #else
231 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
232 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
233 #endif
234 
244 extern uint32_t SystemCoreClock;
245 
253 void SystemInit(void);
254 
262 void SystemCoreClockUpdate(void);
263 
264 #ifdef __cplusplus
265 }
266 #endif
267 
268 #endif /* #if !defined(_SYSTEM_MKL03Z4_H_) */