Kinetis Bootloader  2.0.0
Common bootloader for Kinetis devices
system_MK65F18.h
1 /*
2 ** ###################################################################
3 ** Processors: MK65FN2M0CAC18
4 ** MK65FX1M0CAC18
5 ** MK65FN2M0VMI18
6 ** MK65FX1M0VMI18
7 **
8 ** Compilers: Keil ARM C/C++ Compiler
9 ** Freescale C/C++ for Embedded ARM
10 ** GNU C Compiler
11 ** IAR ANSI C/C++ Compiler for ARM
12 **
13 ** Reference manual: K65P169M180SF5RMV2, Rev. 1, Mar 2015
14 ** Version: rev. 3.0, 2015-03-25
15 ** Build: b151215
16 **
17 ** Abstract:
18 ** Provides a system configuration function and a global variable that
19 ** contains the system frequency. It configures the device and initializes
20 ** the oscillator (PLL) that is part of the microcontroller device.
21 **
22 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
23 ** All rights reserved.
24 **
25 ** Redistribution and use in source and binary forms, with or without modification,
26 ** are permitted provided that the following conditions are met:
27 **
28 ** o Redistributions of source code must retain the above copyright notice, this list
29 ** of conditions and the following disclaimer.
30 **
31 ** o Redistributions in binary form must reproduce the above copyright notice, this
32 ** list of conditions and the following disclaimer in the documentation and/or
33 ** other materials provided with the distribution.
34 **
35 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
36 ** contributors may be used to endorse or promote products derived from this
37 ** software without specific prior written permission.
38 **
39 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
40 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
41 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
42 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
43 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
44 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
46 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
48 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 **
50 ** http: www.freescale.com
51 ** mail: support@freescale.com
52 **
53 ** Revisions:
54 ** - rev. 1.0 (2013-09-02)
55 ** Initial version.
56 ** - rev. 2.0 (2014-02-17)
57 ** Register accessor macros added to the memory map.
58 ** Symbols for Processor Expert memory map compatibility added to the memory map.
59 ** Startup file for gcc has been updated according to CMSIS 3.2.
60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
61 ** Update according to reference manual rev. 2
62 ** - rev. 2.1 (2014-04-16)
63 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
64 ** - rev. 2.2 (2014-10-14)
65 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
66 ** - rev. 2.3 (2014-11-20)
67 ** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
68 ** Update of SystemInit() to use 16MHz external crystal.
69 ** - rev. 2.4 (2015-02-19)
70 ** Renamed interrupt vector LLW to LLWU.
71 ** - rev. 3.0 (2015-03-25)
72 ** Registers updated according to the reference manual revision 1, March 2015
73 **
74 ** ###################################################################
75 */
76 
88 #ifndef _SYSTEM_MK65F18_H_
89 #define _SYSTEM_MK65F18_H_
91 #ifdef __cplusplus
92 extern "C" {
93 #endif
94 
95 #include <stdint.h>
96 
97 #ifndef DISABLE_WDOG
98 #define DISABLE_WDOG 1
99 #endif
100 
101 /* MCG mode constants */
102 
103 #define MCG_MODE_FEI 0U
104 #define MCG_MODE_FBI 1U
105 #define MCG_MODE_BLPI 2U
106 #define MCG_MODE_FEE 3U
107 #define MCG_MODE_FBE 4U
108 #define MCG_MODE_BLPE 5U
109 #define MCG_MODE_PBE 6U
110 #define MCG_MODE_PEE 7U
111 
112 /* Predefined clock setups
113  0 ... Default part configuration
114  Multipurpose Clock Generator (MCG) in FEI mode.
115  Reference clock source for MCG module: Slow internal reference clock
116  Core clock = 20.97152MHz
117  Bus clock = 20.97152MHz
118  1 ... Maximal speed configuration
119  Multipurpose Clock Generator (MCG) in PEE mode.
120  Reference clock source for MCG module: System oscillator 0 reference clock
121  Core clock = 180MHz
122  Bus clock = 60MHz
123  2 ... Chip internally clocked, ready for Very Low Power Run mode.
124  Multipurpose Clock Generator (MCG) in BLPI mode.
125  Reference clock source for MCG module: Fast internal reference clock
126  Core clock = 4MHz
127  Bus clock = 4MHz
128  3 ... Chip externally clocked, ready for Very Low Power Run mode.
129  Multipurpose Clock Generator (MCG) in BLPE mode.
130  Reference clock source for MCG module: System oscillator 0 reference clock
131  Core clock = 4MHz
132  Bus clock = 4MHz
133  4 ... USB clock setup
134  Multipurpose Clock Generator (MCG) in PEE mode.
135  Reference clock source for MCG module: System oscillator 0 reference clock
136  Core clock = 120MHz
137  Bus clock = 60MHz
138  5 ... Maximum achievable clock frequency configuration in RUN mode
139  Multipurpose Clock Generator (MCG) in PEE mode.
140  Reference clock source for MCG module: System oscillator 0 reference clock
141  Core clock = 120MHz
142  Bus clock = 60MHz
143 */
144 
145 /* Define clock source values */
146 
147 #define CPU_XTAL_CLK_HZ \
148  16000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
149 #define CPU_XTAL32k_CLK_HZ \
150  32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz \ \
151  */
152 #define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
153 #define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
154 #define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
155 
156 /* RTC oscillator setting */
157 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
158 #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
159 
160 /* Low power mode enable */
161 /* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
162 #define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
163 
164 /* Internal reference clock trim */
165 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
166 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
167 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
168 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
169 
170 #ifdef CLOCK_SETUP
171 #if (CLOCK_SETUP == 0)
172 #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
173 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
174 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
175 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
176 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
177 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
178 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
179 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
180 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
181 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
182 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
183 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
184 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
185 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
186 /* MCG_C7: OSCSEL=0 */
187 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
188 /* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
189 #define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
190 /* MCG_C11: PLLCS=0 */
191 #define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
192 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
193 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
194 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
195 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
196 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
197 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
198 /* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
199 #define SYSTEM_SIM_CLKDIV2_VALUE 0x02U /* SIM_CLKDIV2 */
200 /* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
201 #define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
202 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
203 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
204  /* SIM_SOPT2:
205  * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
206  */
207 #define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
208 #elif(CLOCK_SETUP == 1)
209 #define DEFAULT_SYSTEM_CLOCK 180000000U /* Default System clock value */
210 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
211 /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
212 #define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
213 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
214 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
215 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
216 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
217 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
218 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
219 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
220 #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
221 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x1D */
222 #define SYSTEM_MCG_C6_VALUE 0x5DU /* MCG_C6 */
223 /* MCG_C7: OSCSEL=0 */
224 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
225 /* MCG_C9: PLL_CME=1,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
226 #define SYSTEM_MCG_C9_VALUE 0x20U /* MCG_C9 */
227 /* MCG_C11: PLLCS=0 */
228 #define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
229 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
230 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
231 /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
232 #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
233 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=2,OUTDIV3=2,OUTDIV4=6 */
234 #define SYSTEM_SIM_CLKDIV1_VALUE 0x02260000U /* SIM_CLKDIV1 */
235 /* SIM_CLKDIV2: USBDIV=6,USBFRAC=0 */
236 #define SYSTEM_SIM_CLKDIV2_VALUE 0x0CU /* SIM_CLKDIV2 */
237 /* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
238 #define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
239 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
240 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
241 /* SIM_SOPT2:
242  * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
243  */
244 #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
245 #elif(CLOCK_SETUP == 2)
246 #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
247 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
248 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
249 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
250 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
251 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
252 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
253 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
254 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
255 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
256 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
257 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
258 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
259 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
260 /* MCG_C7: OSCSEL=0 */
261 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
262 /* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
263 #define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
264 /* MCG_C11: PLLCS=0 */
265 #define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
266 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
267 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
268 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
269 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
270 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
271 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
272 /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
273 #define SYSTEM_SIM_CLKDIV2_VALUE 0x00U /* SIM_CLKDIV2 */
274 /* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
275 #define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
276 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
277 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
278 /* SIM_SOPT2:
279  * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
280  */
281 #define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
282 #elif(CLOCK_SETUP == 3)
283 #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
284 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
285 /* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
286 #define SYSTEM_MCG_C1_VALUE 0xA2U /* MCG_C1 */
287 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
288 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
289 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
290 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
291 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
292 #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
293 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
294 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
295 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV=0 */
296 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
297 /* MCG_C7: OSCSEL=0 */
298 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
299 /* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
300 #define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
301 /* MCG_C11: PLLCS=0 */
302 #define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
303 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
304 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
305 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
306 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
307 /* SIM_CLKDIV1: OUTDIV1=3,OUTDIV2=3,OUTDIV3=3,OUTDIV4=0x0F */
308 #define SYSTEM_SIM_CLKDIV1_VALUE 0x333F0000U /* SIM_CLKDIV1 */
309 /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
310 #define SYSTEM_SIM_CLKDIV2_VALUE 0x00U /* SIM_CLKDIV2 */
311 /* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
312 #define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
313 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
314 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
315 /* SIM_SOPT2:
316  * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
317  */
318 #define SYSTEM_SIM_SOPT2_VALUE 0x01030000U /* SIM_SOPT2 */
319 #elif(CLOCK_SETUP == 4)
320 #define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
321 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
322 /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
323 #define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
324 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
325 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
326 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
327 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
328 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
329 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
330 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
331 #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
332 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x0E */
333 #define SYSTEM_MCG_C6_VALUE 0x4EU /* MCG_C6 */
334 /* MCG_C7: OSCSEL=0 */
335 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
336 /* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
337 #define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
338 /* MCG_C11: PLLCS=0 */
339 #define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
340 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
341 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
342 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
343 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
344 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
345 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
346 /* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
347 #define SYSTEM_SIM_CLKDIV2_VALUE 0x12U /* SIM_CLKDIV2 */
348 /* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
349 #define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
350 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
351 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
352 /* SIM_SOPT2:
353  * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
354  */
355 #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
356 #elif(CLOCK_SETUP == 5)
357 #define DEFAULT_SYSTEM_CLOCK 120000000U /* Default System clock value */
358 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
359 /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
360 #define SYSTEM_MCG_C1_VALUE 0x22U /* MCG_C1 */
361 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
362 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
363 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
364 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
365 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
366 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
367 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=1 */
368 #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
369 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV=0x0E */
370 #define SYSTEM_MCG_C6_VALUE 0x4EU /* MCG_C6 */
371 /* MCG_C7: OSCSEL=0 */
372 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
373 /* MCG_C9: PLL_CME=0,PLL_LOCRE=0,EXT_PLL_LOCS=0 */
374 #define SYSTEM_MCG_C9_VALUE 0x00U /* MCG_C9 */
375 /* MCG_C11: PLLCS=0 */
376 #define SYSTEM_MCG_C11_VALUE 0x00U /* MCG_C11 */
377 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
378 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
379 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
380 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
381 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
382 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
383 /* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
384 #define SYSTEM_SIM_CLKDIV2_VALUE 0x12U /* SIM_CLKDIV2 */
385 /* SIM_CLKDIV3: PLLFLLDIV=0,PLLFLLFRAC=0 */
386 #define SYSTEM_SIM_CLKDIV3_VALUE 0x00U /* SIM_CLKDIV3 */
387 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
388 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
389 /* SIM_SOPT2:
390  * SDHCSRC=0,LPUARTSRC=0,TPMSRC=1,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0,USBREGEN=0,USBSLSRC=0
391  */
392 #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
393 #else
394 #error The selected clock setup is not supported.
395 #endif
396 #else
397 #define DEFAULT_SYSTEM_CLOCK 20971520u
398 #endif
399 
409 extern uint32_t SystemCoreClock;
410 
418 void SystemInit(void);
419 
427 void SystemCoreClockUpdate(void);
428 
429 #ifdef __cplusplus
430 }
431 #endif
432 
433 #endif /* _SYSTEM_MK65F18_H_ */