fsl_spi.h

/*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * o Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
 *   contributors may be used tom  endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef _FSL_SPI_H_
#define _FSL_SPI_H_

#include "fsl_common.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/
#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 
#define SPI_DUMMYDATA (0xFFU)

enum _spi_status
{
    kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_SPI, 0), 
    kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_SPI, 1), 
    kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_SPI, 2) 
};

typedef enum _spi_clock_polarity
{
    kSPI_ClockPolarityActiveHigh = 0x0U, 
    kSPI_ClockPolarityActiveLow          
} spi_clock_polarity_t;

typedef enum _spi_clock_phase
{
    kSPI_ClockPhaseFirstEdge = 0x0U, 
    kSPI_ClockPhaseSecondEdge        
} spi_clock_phase_t;

typedef enum _spi_shift_direction
{
    kSPI_MsbFirst = 0x0U, 
    kSPI_LsbFirst         
} spi_shift_direction_t;

typedef enum _spi_ss_output_mode
{
    kSPI_SlaveSelectAsGpio = 0x0U,         
    kSPI_SlaveSelectFaultInput = 0x2U,     
    kSPI_SlaveSelectAutomaticOutput = 0x3U 
} spi_ss_output_mode_t;

typedef enum _spi_pin_mode
{
    kSPI_PinModeNormal = 0x0U, 
    kSPI_PinModeInput = 0x1U,  
    kSPI_PinModeOutput = 0x3U  
} spi_pin_mode_t;

typedef enum _spi_data_bitcount_mode
{
    kSPI_8BitMode = 0x0U, 
    kSPI_16BitMode        
} spi_data_bitcount_mode_t;

enum _spi_interrupt_enable
{
    kSPI_RxFullAndModfInterruptEnable = 0x1U, 
    kSPI_TxEmptyInterruptEnable = 0x2U,       
    kSPI_MatchInterruptEnable = 0x4U,         
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
    kSPI_RxFifoNearFullInterruptEnable = 0x8U,   
    kSPI_TxFifoNearEmptyInterruptEnable = 0x10U, 
#endif                                           /* FSL_FEATURE_SPI_HAS_FIFO */
};

enum _spi_flags
{
    kSPI_RxBufferFullFlag = SPI_S_SPRF_MASK,   
    kSPI_MatchFlag = SPI_S_SPMF_MASK,          
    kSPI_TxBufferEmptyFlag = SPI_S_SPTEF_MASK, 
    kSPI_ModeFaultFlag = SPI_S_MODF_MASK,      
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
    kSPI_RxFifoNearFullFlag = SPI_S_RNFULLF_MASK,  
    kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK, 
    kSPI_RxFifoFullFlag = SPI_S_TXFULLF_MASK,      
    kSPI_TxFifoEmptyFlag = SPI_S_RFIFOEF_MASK,     
    kSPI_TxFifoError = SPI_CI_TXFERR_MASK << 8U,   
    kSPI_RxFifoError = SPI_CI_RXFERR_MASK << 8U,   
    kSPI_TxOverflow = SPI_CI_TXFOF_MASK << 8U,     
    kSPI_RxOverflow = SPI_CI_RXFOF_MASK << 8U      
#endif                                             /* FSL_FEATURE_SPI_HAS_FIFO */
};

#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO

typedef enum _spi_w1c_interrupt
{
    kSPI_RxFifoFullClearInterrupt = SPI_CI_SPRFCI_MASK,    
    kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK,  
    kSPI_RxNearFullClearInterrupt = SPI_CI_RNFULLFCI_MASK, 
    kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK 
} spi_w1c_interrupt_t;

typedef enum _spi_txfifo_watermark
{
    kSPI_TxFifoOneFourthEmpty = 0, 
    kSPI_TxFifoOneHalfEmpty = 1    
} spi_txfifo_watermark_t;

typedef enum _spi_rxfifo_watermark
{
    kSPI_RxFifoThreeFourthsFull = 0, 
    kSPI_RxFifoOneHalfFull = 1       
} spi_rxfifo_watermark_t;
#endif /* FSL_FEATURE_SPI_HAS_FIFO */

#if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT

enum _spi_dma_enable_t
{
    kSPI_TxDmaEnable = SPI_C2_TXDMAE_MASK,                        
    kSPI_RxDmaEnable = SPI_C2_RXDMAE_MASK,                        
    kSPI_DmaAllEnable = (SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK) 
};
#endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */

typedef struct _spi_master_config
{
    bool enableMaster;               
    bool enableStopInWaitMode;       
    spi_clock_polarity_t polarity;   
    spi_clock_phase_t phase;         
    spi_shift_direction_t direction; 
#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
    spi_data_bitcount_mode_t dataMode; 
#endif                                 /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
    bool enableFifoInterruptClear;      
    spi_txfifo_watermark_t txWatermark; 
    spi_rxfifo_watermark_t rxWatermark; 
#endif                                  /* FSL_FEATURE_SPI_HAS_FIFO */
    spi_ss_output_mode_t outputMode;    
    spi_pin_mode_t pinMode;             
    uint32_t baudRate_Bps;              
} spi_master_config_t;

typedef struct _spi_slave_config
{
    bool enableSlave;                
    bool enableStopInWaitMode;       
    spi_clock_polarity_t polarity;   
    spi_clock_phase_t phase;         
    spi_shift_direction_t direction; 
#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
    spi_data_bitcount_mode_t dataMode; 
#endif                                 /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
    bool enableFifoInterruptClear;      
    spi_txfifo_watermark_t txWatermark; 
    spi_rxfifo_watermark_t rxWatermark; 
#endif                                  /* FSL_FEATURE_SPI_HAS_FIFO */
} spi_slave_config_t;

typedef struct _spi_transfer
{
    uint8_t *txData; 
    uint8_t *rxData; 
    size_t dataSize; 
    uint32_t flags;  
} spi_transfer_t;

typedef struct _spi_master_handle spi_master_handle_t;

typedef spi_master_handle_t spi_slave_handle_t;

typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);

typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);

struct _spi_master_handle
{
    uint8_t *volatile txData;         
    uint8_t *volatile rxData;         
    volatile size_t txRemainingBytes; 
    volatile size_t rxRemainingBytes; 
    volatile uint32_t state;          
    size_t transferSize;              
    uint8_t bytePerFrame;             
    uint8_t watermark;                
    spi_master_callback_t callback;   
    void *userData;                   
};

#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
 * APIs
 ******************************************************************************/
void SPI_MasterGetDefaultConfig(spi_master_config_t *config);

void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);

void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);

void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);

void SPI_Deinit(SPI_Type *base);

static inline void SPI_Enable(I2C_Type *base, bool enable)
{
    if (enable)
    {
        base->C1 |= SPI_C1_SPE_MASK;
    }
    else
    {
        base->C1 &= ~SPI_C1_SPE_MASK;
    }
}

uint32_t SPI_GetStatusFlags(SPI_Type *base);

#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO

static inline void SPI_ClearInterrupt(SPI_Type *base, uint32_t mask)
{
    base->CI |= mask;
}
#endif /* FSL_FEATURE_SPI_HAS_FIFO */

void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask);

void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask);

#if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT

static inline void SPI_EnableDMA(SPI_Type *base, uint32_t mask, bool enable)
{
    if (enable)
    {
        base->C2 |= mask;
    }
    else
    {
        base->C2 &= ~mask;
    }
}
#endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */

static inline uint32_t SPI_GetDataRegisterAddress(SPI_Type *base)
{
#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
    return (uint32_t)(&(base->DL));
#else
    return (uint32_t)(&(base->D));
#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
}

void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);

static inline void SPI_SetMatchData(SPI_Type *base, uint32_t matchData)
{
#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
    base->ML = matchData & 0xFFU;
    base->MH = (matchData >> 8U) & 0xFFU;
#else
    base->M = matchData;
#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
}

#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO

void SPI_EnableFIFO(SPI_Type *base, bool enable);
#endif

void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size);

void SPI_WriteData(SPI_Type *base, uint16_t data);

uint16_t SPI_ReadData(SPI_Type *base);

void SPI_MasterTransferCreateHandle(SPI_Type *base,
                                    spi_master_handle_t *handle,
                                    spi_master_callback_t callback,
                                    void *userData);

status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);

status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);

status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);

void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);

void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);

static inline void SPI_SlaveTransferCreateHandle(SPI_Type *base,
                                                 spi_slave_handle_t *handle,
                                                 spi_slave_callback_t callback,
                                                 void *userData)
{
    SPI_MasterTransferCreateHandle(base, handle, callback, userData);
}

static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
{
    return SPI_MasterTransferNonBlocking(base, handle, xfer);
}

static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
{
    return SPI_MasterTransferGetCount(base, handle, count);
}

static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
{
    SPI_MasterTransferAbort(base, handle);
}

static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
{
    SPI_MasterTransferHandleIRQ(base, handle);
}

#if defined(__cplusplus)
}
#endif

#endif /* _FSL_SPI_H_*/