fsl_lpspi.h

/*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * o Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef _FSL_LPSPI_H_
#define _FSL_LPSPI_H_

#include "fsl_common.h"

/**********************************************************************************************************************
 * Definitions
 *********************************************************************************************************************/

#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 
#define LPSPI_MASTER_DUMMY_DATA (0x00U) 
#define LPSPI_SLAVE_DUMMY_DATA (0x00U)  
enum _lpspi_status
{
    kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0),      
    kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1),     
    kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2),      
    kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) 
};

enum _lpspi_flags
{
    kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK,    
    kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK,      
    kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK,     
    kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK,    
    kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, 
    kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK,    
    kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK,     
    kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK,        
    kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK,       
    kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK |
                            LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK |
                            LPSPI_SR_MBF_MASK) 
};

enum _lpspi_interrupt_enable
{
    kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK,               
    kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK,               
    kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK,     
    kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK,    
    kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, 
    kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK,    
    kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK,     
    kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK,        
    kLPSPI_AllInterruptEnable =
        (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK |
         LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) 
};

enum _lpspi_dma_enable
{
    kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, 
    kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK  
};

typedef enum _lpspi_master_slave_mode
{
    kLPSPI_Master = 1U, 
    kLPSPI_Slave = 0U   
} lpspi_master_slave_mode_t;

typedef enum _lpspi_which_pcs_config
{
    kLPSPI_Pcs0 = 0U, 
    kLPSPI_Pcs1 = 1U, 
    kLPSPI_Pcs2 = 2U, 
    kLPSPI_Pcs3 = 3U  
} lpspi_which_pcs_t;

typedef enum _lpspi_pcs_polarity_config
{
    kLPSPI_PcsActiveHigh = 1U, 
    kLPSPI_PcsActiveLow = 0U   
} lpspi_pcs_polarity_config_t;

enum _lpspi_pcs_polarity
{
    kLPSPI_Pcs0ActiveLow = 1U << 0, 
    kLPSPI_Pcs1ActiveLow = 1U << 1, 
    kLPSPI_Pcs2ActiveLow = 1U << 2, 
    kLPSPI_Pcs3ActiveLow = 1U << 3, 
    kLPSPI_PcsAllActiveLow = 0xFU   
};

typedef enum _lpspi_clock_polarity
{
    kLPSPI_ClockPolarityActiveHigh = 0U, 
    kLPSPI_ClockPolarityActiveLow = 1U   
} lpspi_clock_polarity_t;

typedef enum _lpspi_clock_phase
{
    kLPSPI_ClockPhaseFirstEdge = 0U, 
    kLPSPI_ClockPhaseSecondEdge = 1U 
} lpspi_clock_phase_t;

typedef enum _lpspi_shift_direction
{
    kLPSPI_MsbFirst = 0U, 
    kLPSPI_LsbFirst = 1U  
} lpspi_shift_direction_t;

typedef enum _lpspi_host_request_select
{
    kLPSPI_HostReqExtPin = 0U,         
    kLPSPI_HostReqInternalTrigger = 1U 
} lpspi_host_request_select_t;

typedef enum _lpspi_match_config
{
    kLPSI_MatchDisabled = 0x0U,                     
    kLPSI_1stWordEqualsM0orM1 = 0x2U,               
    kLPSI_AnyWordEqualsM0orM1 = 0x3U,               
    kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, 
    kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, 
    kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U,         
    kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U,         
} lpspi_match_config_t;

typedef enum _lpspi_pin_config
{
    kLPSPI_SdiInSdoOut = 0U, 
    kLPSPI_SdoInSdoOut = 1U, 
    kLPSPI_SdiInSdiOut = 2U, 
    kLPSPI_SdoInSdiOut = 3U  
} lpspi_pin_config_t;

typedef enum _lpspi_data_out_config
{
    kLpspiDataOutRetained = 0U, 
    kLpspiDataOutTristate = 1U  
} lpspi_data_out_config_t;

typedef enum _lpspi_transfer_width
{
    kLPSPI_SingleBitXfer = 0U, 
    kLPSPI_TwoBitXfer = 1U,    
    kLPSPI_FourBitXfer = 2U    
} lpspi_transfer_width_t;

typedef enum _lpspi_delay_type
{
    kLPSPI_PcsToSck = 1U,  
    kLPSPI_LastSckToPcs,   
    kLPSPI_BetweenTransfer 
} lpspi_delay_type_t;

#define LPSPI_MASTER_PCS_SHIFT (4U)   
#define LPSPI_MASTER_PCS_MASK (0xF0U) 
enum _lpspi_transfer_config_flag_for_master
{
    kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, 
    kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, 
    kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, 
    kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, 
    kLPSPI_MasterPcsContinuous = 1U << 20, 
    kLPSPI_MasterByteSwap = 1U << 22 
};

#define LPSPI_SLAVE_PCS_SHIFT (4U)   
#define LPSPI_SLAVE_PCS_MASK (0xF0U) 
enum _lpspi_transfer_config_flag_for_slave
{
    kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, 
    kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, 
    kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, 
    kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, 
    kLPSPI_SlaveByteSwap = 1U << 22 
};

enum _lpspi_transfer_state
{
    kLPSPI_Idle = 0x0U, 
    kLPSPI_Busy,        
    kLPSPI_Error        
};

typedef struct _lpspi_master_config
{
    uint32_t baudRate;                 
    uint32_t bitsPerFrame;             
    lpspi_clock_polarity_t cpol;       
    lpspi_clock_phase_t cpha;          
    lpspi_shift_direction_t direction; 
    uint32_t pcsToSckDelayInNanoSec; 
    uint32_t lastSckToPcsDelayInNanoSec; 
    uint32_t betweenTransferDelayInNanoSec; 
    lpspi_which_pcs_t whichPcs;                     
    lpspi_pcs_polarity_config_t pcsActiveHighOrLow; 
    lpspi_pin_config_t pinCfg; 
    lpspi_data_out_config_t dataOutConfig; 
} lpspi_master_config_t;

typedef struct _lpspi_slave_config
{
    uint32_t bitsPerFrame;             
    lpspi_clock_polarity_t cpol;       
    lpspi_clock_phase_t cpha;          
    lpspi_shift_direction_t direction; 
    lpspi_which_pcs_t whichPcs;                     
    lpspi_pcs_polarity_config_t pcsActiveHighOrLow; 
    lpspi_pin_config_t pinCfg; 
    lpspi_data_out_config_t dataOutConfig; 
} lpspi_slave_config_t;

typedef struct _lpspi_master_handle lpspi_master_handle_t;

typedef struct _lpspi_slave_handle lpspi_slave_handle_t;

typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base,
                                                 lpspi_master_handle_t *handle,
                                                 status_t status,
                                                 void *userData);

typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
                                                lpspi_slave_handle_t *handle,
                                                status_t status,
                                                void *userData);

typedef struct _lpspi_transfer
{
    uint8_t *txData;          
    uint8_t *rxData;          
    volatile size_t dataSize; 
    uint32_t configFlags; 
} lpspi_transfer_t;

struct _lpspi_master_handle
{
    LPSPI_Type *base; 
    volatile bool isPcsContinuous; 
    volatile bool writeTcrInIsr;   
    volatile bool isByteSwap; 
    volatile uint8_t fifoSize; 
    volatile uint8_t rxWatermark; 
    volatile uint8_t bytesEachWrite; 
    volatile uint8_t bytesEachRead;  
    uint8_t *volatile txData;             
    uint8_t *volatile rxData;             
    volatile size_t txRemainingByteCount; 
    volatile size_t rxRemainingByteCount; 
    volatile uint32_t writeRegRemainingTimes; 
    volatile uint32_t readRegRemainingTimes;  
    uint32_t totalByteCount; 
    uint32_t txBuffIfNull; 
    volatile uint8_t state; 
    lpspi_master_transfer_callback_t callback; 
    void *userData;                            
};

struct _lpspi_slave_handle
{
    LPSPI_Type *base; 
    volatile bool isByteSwap; 
    volatile uint8_t fifoSize; 
    volatile uint8_t rxWatermark; 
    volatile uint8_t bytesEachWrite; 
    volatile uint8_t bytesEachRead;  
    uint8_t *volatile txData; 
    uint8_t *volatile rxData; 
    volatile size_t txRemainingByteCount; 
    volatile size_t rxRemainingByteCount; 
    volatile uint32_t writeRegRemainingTimes; 
    volatile uint32_t readRegRemainingTimes;  
    uint32_t totalByteCount; 
    volatile uint8_t state; 
    volatile uint32_t errorCount; 
    lpspi_slave_transfer_callback_t callback; 
    void *userData;                           
};

/**********************************************************************************************************************
 * API
 *********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /*_cplusplus*/

void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz);

void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig);

void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig);

void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig);

void LPSPI_Deinit(LPSPI_Type *base);

void LPSPI_Reset(LPSPI_Type *base);

static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
{
    if (enable)
    {
        base->CR |= LPSPI_CR_MEN_MASK;
    }
    else
    {
        base->CR &= ~LPSPI_CR_MEN_MASK;
    }
}

static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)
{
    return (base->SR);
}

static inline uint32_t LPSPI_GetTxFifoSize(LPSPI_Type *base)
{
    return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT));
}

static inline uint32_t LPSPI_GetRxFifoSize(LPSPI_Type *base)
{
    return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT));
}

static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)
{
    return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT);
}

static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)
{
    return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
}

static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)
{
    base->SR = statusFlags; 
}

static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)
{
    base->IER |= mask;
}

static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)
{
    base->IER &= ~mask;
}

static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)
{
    base->DER |= mask;
}

static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)
{
    base->DER &= ~mask;
}

static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)
{
    return (uint32_t) & (base->TDR);
}

static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
{
    return (uint32_t) & (base->RDR);
}

static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)
{
    base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode);
}

static inline bool LPSPI_IsMaster(LPSPI_Type *base)
{
    return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK);
}

static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)
{
    base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT);
}

static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)
{
    base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater);
}

static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)
{
    base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask);
}

static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)
{
    base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1);
}

uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
                                 uint32_t baudRate_Bps,
                                 uint32_t srcClock_Hz,
                                 uint32_t *tcrPrescaleValue);

void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay);

uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
                                   uint32_t delayTimeInNanoSec,
                                   lpspi_delay_type_t whichDelay,
                                   uint32_t srcClock_Hz);

static inline void LPSPI_WriteDataNonBlocking(LPSPI_Type *base, uint32_t data)
{
    base->TDR = data;
}

static inline uint32_t LPSPI_ReadDataNonBlocking(LPSPI_Type *base)
{
    return (base->RDR);
}

status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer);

/*Transactional APIs*/

void LPSPI_MasterCreateHandle(LPSPI_Type *base,
                              lpspi_master_handle_t *handle,
                              lpspi_master_transfer_callback_t callback,
                              void *userData);

status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer);

status_t LPSPI_MasterGetTransferCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count);

void LPSPI_MasterAbortTransfer(LPSPI_Type *base, lpspi_master_handle_t *handle);

void LPSPI_MasterHandleInterrupt(LPSPI_Type *base, lpspi_master_handle_t *handle);

void LPSPI_SlaveCreateHandle(LPSPI_Type *base,
                             lpspi_slave_handle_t *handle,
                             lpspi_slave_transfer_callback_t callback,
                             void *userData);

status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer);

status_t LPSPI_SlaveGetTransferCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count);

void LPSPI_SlaveAbortTransfer(LPSPI_Type *base, lpspi_slave_handle_t *handle);

void LPSPI_SlaveHandleInterrupt(LPSPI_Type *base, lpspi_slave_handle_t *handle);

#if defined(__cplusplus)
}
#endif /*_cplusplus*/

#endif /*_FSL_LPSPI_H_*/