fsl_dspi.h

/*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * o Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef _FSL_DSPI_H_
#define _FSL_DSPI_H_

#include "fsl_common.h"

/**********************************************************************************************************************
 * Definitions
 *********************************************************************************************************************/

#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 
#define DSPI_MASTER_DUMMY_DATA (0x00U) 
#define DSPI_SLAVE_DUMMY_DATA (0x00U)  
enum _dspi_status
{
    kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0),      
    kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1),     
    kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2),      
    kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) 
};

enum _dspi_flags
{
    kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK,          
    kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK,         
    kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK,    
    kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK,  
    kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK,     
    kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, 
    kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK,     
    kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK |
                          SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK 
};

enum _dspi_interrupt_enable
{
    kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK,          
    kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK,         
    kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK,    
    kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK,  
    kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK,     
    kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, 
    kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK |
                               SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK
};

enum _dspi_dma_enable
{
    kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), 
    kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK)  
};

typedef enum _dspi_master_slave_mode
{
    kDSPI_Master = 1U, 
    kDSPI_Slave = 0U   
} dspi_master_slave_mode_t;

typedef enum _dspi_master_sample_point
{
    kDSPI_SckToSin0Clock = 0U, 
    kDSPI_SckToSin1Clock = 1U, 
    kDSPI_SckToSin2Clock = 2U  
} dspi_master_sample_point_t;

typedef enum _dspi_which_pcs_config
{
    kDSPI_Pcs0 = 1U << 0, 
    kDSPI_Pcs1 = 1U << 1, 
    kDSPI_Pcs2 = 1U << 2, 
    kDSPI_Pcs3 = 1U << 3, 
    kDSPI_Pcs4 = 1U << 4, 
    kDSPI_Pcs5 = 1U << 5  
} dspi_which_pcs_t;

typedef enum _dspi_pcs_polarity_config
{
    kDSPI_PcsActiveHigh = 0U, 
    kDSPI_PcsActiveLow = 1U   
} dspi_pcs_polarity_config_t;

enum _dspi_pcs_polarity
{
    kDSPI_Pcs0ActiveLow = 1U << 0, 
    kDSPI_Pcs1ActiveLow = 1U << 1, 
    kDSPI_Pcs2ActiveLow = 1U << 2, 
    kDSPI_Pcs3ActiveLow = 1U << 3, 
    kDSPI_Pcs4ActiveLow = 1U << 4, 
    kDSPI_Pcs5ActiveLow = 1U << 5, 
    kDSPI_PcsAllActiveLow = 0xFFU  
};

typedef enum _dspi_clock_polarity
{
    kDSPI_ClockPolarityActiveHigh = 0U, 
    kDSPI_ClockPolarityActiveLow = 1U   
} dspi_clock_polarity_t;

typedef enum _dspi_clock_phase
{
    kDSPI_ClockPhaseFirstEdge = 0U, 
    kDSPI_ClockPhaseSecondEdge = 1U 
} dspi_clock_phase_t;

typedef enum _dspi_shift_direction
{
    kDSPI_MsbFirst = 0U, 
    kDSPI_LsbFirst = 1U  
} dspi_shift_direction_t;

typedef enum _dspi_delay_type
{
    kDSPI_PcsToSck = 1U,  
    kDSPI_LastSckToPcs,   
    kDSPI_BetweenTransfer 
} dspi_delay_type_t;

typedef enum _dspi_ctar_selection
{
    kDSPI_Ctar0 = 0U, 
    kDSPI_Ctar1 = 1U, 
    kDSPI_Ctar2 = 2U, 
    kDSPI_Ctar3 = 3U, 
    kDSPI_Ctar4 = 4U, 
    kDSPI_Ctar5 = 5U, 
    kDSPI_Ctar6 = 6U, 
    kDSPI_Ctar7 = 7U  
} dspi_ctar_selection_t;

#define DSPI_MASTER_CTAR_SHIFT (0U)   
#define DSPI_MASTER_CTAR_MASK (0x0FU) 
#define DSPI_MASTER_PCS_SHIFT (4U)    
#define DSPI_MASTER_PCS_MASK (0xF0U)  
enum _dspi_transfer_config_flag_for_master
{
    kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, 
    kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, 
    kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, 
    kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, 
    kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, 
    kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, 
    kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, 
    kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, 
    kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, 
    kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, 
    kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, 
    kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, 
    kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, 
    kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, 
    kDSPI_MasterPcsContinuous = 1U << 20,       
    kDSPI_MasterActiveAfterTransfer = 1U << 21, 
};

#define DSPI_SLAVE_CTAR_SHIFT (0U)   
#define DSPI_SLAVE_CTAR_MASK (0x07U) 
enum _dspi_transfer_config_flag_for_slave
{
    kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, 
};

enum _dspi_transfer_state
{
    kDSPI_Idle = 0x0U, 
    kDSPI_Busy,        
    kDSPI_Error        
};

typedef struct _dspi_command_data_config
{
    bool isPcsContinuous;            
    dspi_ctar_selection_t whichCtar; 
    dspi_which_pcs_t whichPcs;       
    bool isEndOfQueue;               
    bool clearTransferCount;         
} dspi_command_data_config_t;

typedef struct _dspi_master_ctar_config
{
    uint32_t baudRate;                
    uint32_t bitsPerFrame;            
    dspi_clock_polarity_t cpol;       
    dspi_clock_phase_t cpha;          
    dspi_shift_direction_t direction; 
    uint32_t pcsToSckDelayInNanoSec;        
    uint32_t lastSckToPcsDelayInNanoSec;    
    uint32_t betweenTransferDelayInNanoSec; 
} dspi_master_ctar_config_t;

typedef struct _dspi_master_config
{
    dspi_ctar_selection_t whichCtar;      
    dspi_master_ctar_config_t ctarConfig; 
    dspi_which_pcs_t whichPcs;                     
    dspi_pcs_polarity_config_t pcsActiveHighOrLow; 
    bool enableContinuousSCK;   
    bool enableRxFifoOverWrite; 
    bool enableModifiedTimingFormat;        
    dspi_master_sample_point_t samplePoint; 
} dspi_master_config_t;

typedef struct _dspi_slave_ctar_config
{
    uint32_t bitsPerFrame;      
    dspi_clock_polarity_t cpol; 
    dspi_clock_phase_t cpha;    
} dspi_slave_ctar_config_t;

typedef struct _dspi_slave_config
{
    dspi_ctar_selection_t whichCtar;     
    dspi_slave_ctar_config_t ctarConfig; 
    bool enableContinuousSCK;               
    bool enableRxFifoOverWrite;             
    bool enableModifiedTimingFormat;        
    dspi_master_sample_point_t samplePoint; 
} dspi_slave_config_t;

typedef struct _dspi_master_handle dspi_master_handle_t;

typedef struct _dspi_slave_handle dspi_slave_handle_t;

typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base,
                                                dspi_master_handle_t *handle,
                                                status_t status,
                                                void *userData);
typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base,
                                               dspi_slave_handle_t *handle,
                                               status_t status,
                                               void *userData);

typedef struct _dspi_transfer
{
    uint8_t *txData;          
    uint8_t *rxData;          
    volatile size_t dataSize; 
    uint32_t
        configFlags; 
} dspi_transfer_t;

struct _dspi_master_handle
{
    uint32_t bitsPerFrame;         
    volatile uint32_t command;     
    volatile uint32_t lastCommand; 
    uint8_t fifoSize; 
    volatile bool isPcsActiveAfterTransfer; 
    volatile bool isThereExtraByte;         
    uint8_t *volatile txData;                  
    uint8_t *volatile rxData;                  
    volatile size_t remainingSendByteCount;    
    volatile size_t remainingReceiveByteCount; 
    size_t totalByteCount;                     
    volatile uint8_t state; 
    dspi_master_transfer_callback_t callback; 
    void *userData;                           
};

struct _dspi_slave_handle
{
    uint32_t bitsPerFrame;          
    volatile bool isThereExtraByte; 
    uint8_t *volatile txData;                  
    uint8_t *volatile rxData;                  
    volatile size_t remainingSendByteCount;    
    volatile size_t remainingReceiveByteCount; 
    size_t totalByteCount;                     
    volatile uint8_t state; 
    volatile uint32_t errorCount; 
    dspi_slave_transfer_callback_t callback; 
    void *userData;                          
};

/**********************************************************************************************************************
 * API
 *********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /*_cplusplus*/

void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz);

void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);

void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig);

void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);

void DSPI_Deinit(SPI_Type *base);

static inline void DSPI_Enable(SPI_Type *base, bool enable)
{
    if (enable)
    {
        base->MCR &= ~SPI_MCR_MDIS_MASK;
    }
    else
    {
        base->MCR |= SPI_MCR_MDIS_MASK;
    }
}

static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
{
    return (base->SR);
}

static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
{
    base->SR = statusFlags; 
}

void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);

static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
{
    base->RSER &= ~mask;
}

static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
{
    base->RSER |= mask;
}

static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
{
    base->RSER &= ~mask;
}

static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
{
    return (uint32_t) & (base->PUSHR);
}

static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
{
    return (uint32_t) & (base->PUSHR_SLAVE);
}

static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
{
    return (uint32_t) & (base->POPR);
}

static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
{
    base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode);
}

static inline bool DSPI_IsMaster(SPI_Type *base)
{
    return (bool)((base->MCR) & SPI_MCR_MSTR_MASK);
}
static inline void DSPI_StartTransfer(SPI_Type *base)
{
    base->MCR &= ~SPI_MCR_HALT_MASK;
}
static inline void DSPI_StopTransfer(SPI_Type *base)
{
    base->MCR |= SPI_MCR_HALT_MASK;
}

static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
{
    base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) |
                SPI_MCR_DIS_RXF(!enableRxFifo);
}

static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
{
    base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) |
                SPI_MCR_CLR_RXF(flushRxFifo);
}

static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
{
    base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask);
}

uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
                                dspi_ctar_selection_t whichCtar,
                                uint32_t baudRate_Bps,
                                uint32_t srcClock_Hz);

void DSPI_MasterSetDelayScaler(
    SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);

uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
                                  dspi_ctar_selection_t whichCtar,
                                  dspi_delay_type_t whichDelay,
                                  uint32_t srcClock_Hz,
                                  uint32_t delayTimeInNanoSec);

static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
{
    base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
                  SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
                  SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data);
}

void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);

void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data);

static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
{
    /* Format the 16-bit command word according to the PUSHR data register bit field*/
    return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
                      SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
                      SPI_PUSHR_CTCNT(command->clearTransferCount));
}

void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);

static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
{
    base->PUSHR_SLAVE = data;
}

void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data);

static inline uint32_t DSPI_ReadData(SPI_Type *base)
{
    return (base->POPR);
}

/*Transactional APIs*/

void DSPI_MasterTransferCreateHandle(SPI_Type *base,
                                     dspi_master_handle_t *handle,
                                     dspi_master_transfer_callback_t callback,
                                     void *userData);

status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);

status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);

status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count);

void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);

void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);

void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
                                    dspi_slave_handle_t *handle,
                                    dspi_slave_transfer_callback_t callback,
                                    void *userData);

status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer);

status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count);

void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);

void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle);

#if defined(__cplusplus)
}
#endif /*_cplusplus*/

#endif /*_FSL_DSPI_H_*/