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<a href="#nested-classes">Data Structures</a> |
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<a href="#enum-members">Enumerations</a> </div>
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<div class="headertitle">
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<div class="title">DSPI Driver<div class="ingroups"><a class="el" href="group__dspi.html">DSPI: Serial Peripheral Interface Driver</a></div></div> </div>
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</div><!--header-->
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<div class="contents">
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
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<p>This section describes the programming interface of the DSPI Peripheral driver. The DSPI driver configures the DSPI module and provides the functional and transactional interfaces to build the DSPI application.</p>
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<h1><a class="anchor" id="DSPITpyUC"></a>
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Typical use case</h1>
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<h2><a class="anchor" id="DSPIMasterOps"></a>
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Master Operation</h2>
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<div class="fragment"><div class="line">dspi_master_handle_t g_m_handle; <span class="comment">//global variable</span></div>
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<div class="line"><a class="code" href="group__dspi__driver.html#structdspi__master__config__t">dspi_master_config_t</a> masterConfig;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a822cafb9ccbaac368bdd456f004dd7f1">whichCtar</a> = <a class="code" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfadb2a4c8c9b722c6a1b8cbb03b17a6519">kDSPI_Ctar0</a>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#abc9dde7dd3b924290ecd6180f7a7e0cb">baudRate</a> = baudrate;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a935cc12276a643aac250e07b6fd26841">bitsPerFrame</a> = 8;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a87112137c6b8b714d1700756557c86c9">cpol</a> = <a class="code" href="group__dspi__driver.html#gga1e0a9074742794ef89f597d220296651ab5279f36f0c6b1617aa937824806d71d">kDSPI_ClockPolarityActiveHigh</a>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a3649f0e62d8f5421366afb76792e957b">cpha</a> = <a class="code" href="group__dspi__driver.html#gga4269ec144334dd60666a92e6fd2c1476a996e921abbf325ee9978a42681aee0d5">kDSPI_ClockPhaseFirstEdge</a>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#aafbec5b2cc4cdec420381f29b32a04e8">direction</a> = <a class="code" href="group__dspi__driver.html#gga06fad8ae17b680f6dddfd798c9d3b30da8885a916a15d0b97ffd0f28d81242f6f">kDSPI_MsbFirst</a>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a32c83fc580640a66049071dd9b672a1a">pcsToSckDelayInNanoSec</a> = 1000000000 / baudrate ;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#af6e22013a735cf762e671973afbed487">lastSckToPcsDelayInNanoSec</a> = 1000000000 / baudrate ;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a8d900155157617487c5089a91c41c638">betweenTransferDelayInNanoSec</a> = 1000000000 / baudrate ;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a01111111bd757122f7874576e3b859e7">whichPcs</a> = <a class="code" href="group__dspi__driver.html#gga36d77cff6cfa202e0ff3a05ab4c2a632a5c6297be9586ee874fa1a84a16d810b7">kDSPI_Pcs0</a>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a70b19520cae538f1860d355bacc4abca">pcsActiveHighOrLow</a> = <a class="code" href="group__dspi__driver.html#ggab466e73cb54b2c023459d43918c4197daa678a5937bbb9975e3c014592c3d542c">kDSPI_PcsActiveLow</a>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a9fd922242d41c151599c4906c4d8d7f2">enableContinuousSCK</a> = <span class="keyword">false</span>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#aa9a8bb9487711b83566ae0e04b386905">enableRxFifoOverWrite</a> = <span class="keyword">false</span>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a86656569461eb376c1a7db424efb8916">enableModifiedTimingFormat</a> = <span class="keyword">false</span>;</div>
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<div class="line">masterConfig.<a class="code" href="group__dspi__driver.html#a1827b5d3bf3ff28b7ce940bbae1a6d35">samplePoint</a> = <a class="code" href="group__dspi__driver.html#ggae783895e2917abe07adbe27a253510a2abbcf84bafbd94a63a9600647162b8d86">kDSPI_SckToSin0Clock</a>;</div>
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<div class="line"><a class="code" href="group__dspi__driver.html#gaadf23f732f4c1b61d6634bd17b1a36d7">DSPI_MasterInit</a>(base, &masterConfig, srcClock_Hz);</div>
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<div class="line"></div>
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<div class="line"><span class="comment">//srcClock_Hz = CLOCK_GetFreq(xxx);</span></div>
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<div class="line"><a class="code" href="group__dspi__driver.html#gaadf23f732f4c1b61d6634bd17b1a36d7">DSPI_MasterInit</a>(base, &masterConfig, srcClock_Hz);</div>
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<div class="line"></div>
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<div class="line"><a class="code" href="group__dspi__driver.html#ga63e04b92d99d795cf84df62379765a91">DSPI_MasterTransferCreateHandle</a>(base, &g_m_handle, NULL, NULL);</div>
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<div class="line"></div>
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<div class="line">masterXfer.txData = masterSendBuffer;</div>
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<div class="line">masterXfer.rxData = masterReceiveBuffer;</div>
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<div class="line">masterXfer.dataSize = transfer_dataSize;</div>
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<div class="line">masterXfer.configFlags = <a class="code" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792faf7ddf42278af30a1b81f10c4058ecddd">kDSPI_MasterCtar0</a> | <a class="code" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fad51bd34d51062d900b07801e0fd193cc">kDSPI_MasterPcs0</a> ;</div>
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<div class="line"><a class="code" href="group__dspi__driver.html#gab2d0aa3acb2acc3cc5413314d758628b">DSPI_MasterTransferBlocking</a>(base, &g_m_handle, &masterXfer);</div>
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</div><!-- fragment --><h2><a class="anchor" id="DSPISlaveOps"></a>
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Slave Operation</h2>
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<div class="fragment"><div class="line">dspi_slave_handle_t g_s_handle;<span class="comment">//global variable</span></div>
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<div class="line"><span class="comment">/*Slave config*/</span></div>
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<div class="line">slaveConfig.whichCtar = <a class="code" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfadb2a4c8c9b722c6a1b8cbb03b17a6519">kDSPI_Ctar0</a>;</div>
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<div class="line">slaveConfig.ctarConfig.bitsPerFrame = 8;</div>
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<div class="line">slaveConfig.ctarConfig.cpol = <a class="code" href="group__dspi__driver.html#gga1e0a9074742794ef89f597d220296651ab5279f36f0c6b1617aa937824806d71d">kDSPI_ClockPolarityActiveHigh</a>;</div>
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<div class="line">slaveConfig.ctarConfig.cpha = <a class="code" href="group__dspi__driver.html#gga4269ec144334dd60666a92e6fd2c1476a996e921abbf325ee9978a42681aee0d5">kDSPI_ClockPhaseFirstEdge</a>;</div>
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<div class="line">slaveConfig.enableContinuousSCK = <span class="keyword">false</span>;</div>
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<div class="line">slaveConfig.enableRxFifoOverWrite = <span class="keyword">false</span>;</div>
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<div class="line">slaveConfig.enableModifiedTimingFormat = <span class="keyword">false</span>;</div>
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<div class="line">slaveConfig.samplePoint = <a class="code" href="group__dspi__driver.html#ggae783895e2917abe07adbe27a253510a2abbcf84bafbd94a63a9600647162b8d86">kDSPI_SckToSin0Clock</a>;</div>
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<div class="line"><a class="code" href="group__dspi__driver.html#gacf6cecb6b73f02eaa448634a8d705851">DSPI_SlaveInit</a>(base, &slaveConfig);</div>
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<div class="line"></div>
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<div class="line">slaveXfer.txData = slaveSendBuffer0;</div>
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<div class="line">slaveXfer.rxData = slaveReceiveBuffer0;</div>
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<div class="line">slaveXfer.dataSize = transfer_dataSize;</div>
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<div class="line">slaveXfer.configFlags = <a class="code" href="group__dspi__driver.html#gga5070a73633ee72428adda72058f7fb5fa6e63c217f9b392f78fb96ee039c991c8">kDSPI_SlaveCtar0</a>;</div>
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<div class="line"></div>
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<div class="line"><span class="keywordtype">bool</span> isTransferCompleted = <span class="keyword">false</span>;</div>
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<div class="line"><a class="code" href="group__dspi__driver.html#gadc23691aa2c06ae9076a5f0b16f33a8c">DSPI_SlaveTransferCreateHandle</a>(base, &g_s_handle, DSPI_SlaveUserCallback, &isTransferCompleted);</div>
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<div class="line"></div>
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<div class="line"><a class="code" href="group__dspi__driver.html#ga81f85324750f75b8e7248846c88d99e7">DSPI_SlaveTransferNonBlocking</a>(&g_s_handle, &slaveXfer);</div>
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<div class="line"></div>
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<div class="line"></div>
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<div class="line"><span class="comment">//void DSPI_SlaveUserCallback(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *isTransferCompleted)</span></div>
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<div class="line"><span class="comment">//{</span></div>
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<div class="line"><span class="comment">// if (status == kStatus_Success)</span></div>
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<div class="line"><span class="comment">// {</span></div>
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<div class="line"><span class="comment">// __NOP();</span></div>
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<div class="line"><span class="comment">// }</span></div>
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<div class="line"><span class="comment">// else if (status == kStatus_DSPI_Error)</span></div>
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<div class="line"><span class="comment">// {</span></div>
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<div class="line"><span class="comment">// __NOP();</span></div>
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<div class="line"><span class="comment">// }</span></div>
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<div class="line"><span class="comment">//</span></div>
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<div class="line"><span class="comment">// *((bool *)isTransferCompleted) = true;</span></div>
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<div class="line"><span class="comment">//</span></div>
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<div class="line"><span class="comment">// PRINTF("This is DSPI slave call back . \r\n");</span></div>
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<div class="line"><span class="comment">//}</span></div>
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</div><!-- fragment --> <table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
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Data Structures</h2></td></tr>
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<tr class="memitem:structdspi__command__data__config__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a></td></tr>
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<tr class="memdesc:structdspi__command__data__config__t"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master command date configuration used for SPIx_PUSHR. <a href="group__dspi__driver.html#structdspi__command__data__config__t">More...</a><br/></td></tr>
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<tr class="separator:structdspi__command__data__config__t"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structdspi__master__ctar__config__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#structdspi__master__ctar__config__t">dspi_master_ctar_config_t</a></td></tr>
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<tr class="memdesc:structdspi__master__ctar__config__t"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master ctar configuration structure. <a href="group__dspi__driver.html#structdspi__master__ctar__config__t">More...</a><br/></td></tr>
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<tr class="separator:structdspi__master__ctar__config__t"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structdspi__master__config__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#structdspi__master__config__t">dspi_master_config_t</a></td></tr>
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<tr class="memdesc:structdspi__master__config__t"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master configuration structure. <a href="group__dspi__driver.html#structdspi__master__config__t">More...</a><br/></td></tr>
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<tr class="separator:structdspi__master__config__t"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structdspi__slave__ctar__config__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#structdspi__slave__ctar__config__t">dspi_slave_ctar_config_t</a></td></tr>
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<tr class="memdesc:structdspi__slave__ctar__config__t"><td class="mdescLeft"> </td><td class="mdescRight">DSPI slave ctar configuration structure. <a href="group__dspi__driver.html#structdspi__slave__ctar__config__t">More...</a><br/></td></tr>
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<tr class="separator:structdspi__slave__ctar__config__t"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structdspi__slave__config__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#structdspi__slave__config__t">dspi_slave_config_t</a></td></tr>
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<tr class="memdesc:structdspi__slave__config__t"><td class="mdescLeft"> </td><td class="mdescRight">DSPI slave configuration structure. <a href="group__dspi__driver.html#structdspi__slave__config__t">More...</a><br/></td></tr>
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<tr class="separator:structdspi__slave__config__t"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structdspi__transfer__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#structdspi__transfer__t">dspi_transfer_t</a></td></tr>
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<tr class="memdesc:structdspi__transfer__t"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master/slave transfer structure. <a href="group__dspi__driver.html#structdspi__transfer__t">More...</a><br/></td></tr>
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<tr class="separator:structdspi__transfer__t"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:struct__dspi__master__handle"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#struct__dspi__master__handle">dspi_master_handle_t</a></td></tr>
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<tr class="memdesc:struct__dspi__master__handle"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master transfer handle structure used for transactional API. <a href="group__dspi__driver.html#struct__dspi__master__handle">More...</a><br/></td></tr>
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<tr class="separator:struct__dspi__master__handle"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:struct__dspi__slave__handle"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#struct__dspi__slave__handle">dspi_slave_handle_t</a></td></tr>
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<tr class="memdesc:struct__dspi__slave__handle"><td class="mdescLeft"> </td><td class="mdescRight">DSPI slave transfer handle structure used for transactional API. <a href="group__dspi__driver.html#struct__dspi__slave__handle">More...</a><br/></td></tr>
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<tr class="separator:struct__dspi__slave__handle"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:gae3af6268fdc846d553d23c82fd8c8668"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gae3af6268fdc846d553d23c82fd8c8668">DSPI_DUMMY_DATA</a>   (0x00U)</td></tr>
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<tr class="memdesc:gae3af6268fdc846d553d23c82fd8c8668"><td class="mdescLeft"> </td><td class="mdescRight">DSPI dummy data if no Tx data. <a href="#gae3af6268fdc846d553d23c82fd8c8668">More...</a><br/></td></tr>
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<tr class="separator:gae3af6268fdc846d553d23c82fd8c8668"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac4a272cf2546e7d51aa45d76b10dc174"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gac4a272cf2546e7d51aa45d76b10dc174">DSPI_MASTER_CTAR_SHIFT</a>   (0U)</td></tr>
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<tr class="memdesc:gac4a272cf2546e7d51aa45d76b10dc174"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master CTAR shift macro , internal used. <a href="#gac4a272cf2546e7d51aa45d76b10dc174">More...</a><br/></td></tr>
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<tr class="separator:gac4a272cf2546e7d51aa45d76b10dc174"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15e4a446e06e9964a77d20c00b7d3397"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga15e4a446e06e9964a77d20c00b7d3397">DSPI_MASTER_CTAR_MASK</a>   (0x0FU)</td></tr>
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<tr class="memdesc:ga15e4a446e06e9964a77d20c00b7d3397"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master CTAR mask macro , internal used. <a href="#ga15e4a446e06e9964a77d20c00b7d3397">More...</a><br/></td></tr>
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<tr class="separator:ga15e4a446e06e9964a77d20c00b7d3397"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga082f0377ee21656002efecaeaf77034c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga082f0377ee21656002efecaeaf77034c">DSPI_MASTER_PCS_SHIFT</a>   (4U)</td></tr>
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<tr class="memdesc:ga082f0377ee21656002efecaeaf77034c"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master PCS shift macro , internal used. <a href="#ga082f0377ee21656002efecaeaf77034c">More...</a><br/></td></tr>
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<tr class="separator:ga082f0377ee21656002efecaeaf77034c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga213b335dc840f0c1637ca37b0cf3f4f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga213b335dc840f0c1637ca37b0cf3f4f4">DSPI_MASTER_PCS_MASK</a>   (0xF0U)</td></tr>
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<tr class="memdesc:ga213b335dc840f0c1637ca37b0cf3f4f4"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master PCS mask macro , internal used. <a href="#ga213b335dc840f0c1637ca37b0cf3f4f4">More...</a><br/></td></tr>
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<tr class="separator:ga213b335dc840f0c1637ca37b0cf3f4f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d0819629aecb560192865e1850bff07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga5d0819629aecb560192865e1850bff07">DSPI_SLAVE_CTAR_SHIFT</a>   (0U)</td></tr>
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<tr class="memdesc:ga5d0819629aecb560192865e1850bff07"><td class="mdescLeft"> </td><td class="mdescRight">DSPI slave CTAR shift macro , internal used. <a href="#ga5d0819629aecb560192865e1850bff07">More...</a><br/></td></tr>
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<tr class="separator:ga5d0819629aecb560192865e1850bff07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf41a736795e34277fdb594a75754ab69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gaf41a736795e34277fdb594a75754ab69">DSPI_SLAVE_CTAR_MASK</a>   (0x07U)</td></tr>
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<tr class="memdesc:gaf41a736795e34277fdb594a75754ab69"><td class="mdescLeft"> </td><td class="mdescRight">DSPI slave CTAR mask macro , internal used. <a href="#gaf41a736795e34277fdb594a75754ab69">More...</a><br/></td></tr>
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<tr class="separator:gaf41a736795e34277fdb594a75754ab69"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
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Typedefs</h2></td></tr>
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<tr class="memitem:gad191922bda6ac07f95f241a67eb52f48"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad191922bda6ac07f95f241a67eb52f48">dspi_master_transfer_callback_t</a> )(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)</td></tr>
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<tr class="memdesc:gad191922bda6ac07f95f241a67eb52f48"><td class="mdescLeft"> </td><td class="mdescRight">Completion callback function pointer type. <a href="#gad191922bda6ac07f95f241a67eb52f48">More...</a><br/></td></tr>
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<tr class="separator:gad191922bda6ac07f95f241a67eb52f48"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c9ef1b6a6d8034b5e47b8310f2d52dc"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga0c9ef1b6a6d8034b5e47b8310f2d52dc">dspi_slave_transfer_callback_t</a> )(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)</td></tr>
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<tr class="memdesc:ga0c9ef1b6a6d8034b5e47b8310f2d52dc"><td class="mdescLeft"> </td><td class="mdescRight">Completion callback function pointer type. <a href="#ga0c9ef1b6a6d8034b5e47b8310f2d52dc">More...</a><br/></td></tr>
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<tr class="separator:ga0c9ef1b6a6d8034b5e47b8310f2d52dc"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
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Enumerations</h2></td></tr>
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<tr class="memitem:ga06b41ab984bc03e6f1eb07988edcb3ea"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga06b41ab984bc03e6f1eb07988edcb3ea">_dspi_status</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga06b41ab984bc03e6f1eb07988edcb3eaad5ecc8346da4119b8609c6bcb4c57e40">kStatus_DSPI_Busy</a> = MAKE_STATUS(kStatusGroup_DSPI, 0),
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga06b41ab984bc03e6f1eb07988edcb3eaaaae2ba17a6a622142816b0ffec7b9f7a">kStatus_DSPI_Error</a> = MAKE_STATUS(kStatusGroup_DSPI, 1),
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga06b41ab984bc03e6f1eb07988edcb3eaa638dc0d050e7660225a46cc7cd6e38c7">kStatus_DSPI_Idle</a> = MAKE_STATUS(kStatusGroup_DSPI, 2),
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga06b41ab984bc03e6f1eb07988edcb3eaac1713712f0410e28da008d714734a6bd">kStatus_DSPI_OutOfRange</a> = MAKE_STATUS(kStatusGroup_DSPI, 3)
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<br/>
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}</td></tr>
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<tr class="memdesc:ga06b41ab984bc03e6f1eb07988edcb3ea"><td class="mdescLeft"> </td><td class="mdescRight">Status for the DSPI driver. <a href="group__dspi__driver.html#ga06b41ab984bc03e6f1eb07988edcb3ea">More...</a><br/></td></tr>
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<tr class="separator:ga06b41ab984bc03e6f1eb07988edcb3ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2bfefaf6ba65ba464e764d1c918c904f"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga2bfefaf6ba65ba464e764d1c918c904f">_dspi_flags</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904faffc8e8711d9083470cddb0db647b75b0">kDSPI_TxCompleteFlag</a> = SPI_SR_TCF_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904fae91c7a5cc2a90fa051c89f13bbb6d8ed">kDSPI_EndOfQueueFlag</a> = SPI_SR_EOQF_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904fae36215137d8ce7cf215349199db877b7">kDSPI_TxFifoUnderflowFlag</a> = SPI_SR_TFUF_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904fae9704d53b57758969f8ea5ea6c86f7f0">kDSPI_TxFifoFillRequestFlag</a> = SPI_SR_TFFF_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904fa30f039adca01f89dbbd02f70dff725ee">kDSPI_RxFifoOverflowFlag</a> = SPI_SR_RFOF_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904fa092b7f39357ce8cb82ec825e93536605">kDSPI_RxFifoDrainRequestFlag</a> = SPI_SR_RFDF_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904fa58771b3977aef221dab6a67a6739f8d6">kDSPI_TxAndRxStatusFlag</a> = SPI_SR_TXRXS_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904fa4a742818251256d8fc35ab63a6af9c9e">kDSPI_AllStatusFlag</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga2bfefaf6ba65ba464e764d1c918c904f"><td class="mdescLeft"> </td><td class="mdescRight">DSPI status flags in SPIx_SR register. <a href="group__dspi__driver.html#ga2bfefaf6ba65ba464e764d1c918c904f">More...</a><br/></td></tr>
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<tr class="separator:ga2bfefaf6ba65ba464e764d1c918c904f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb57298690a2f1a09d94d696c893c4b2"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gaeb57298690a2f1a09d94d696c893c4b2">_dspi_interrupt_enable</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2ab2b1ba228fd75de23a2de7e56c1ee438">kDSPI_TxCompleteInterruptEnable</a> = SPI_RSER_TCF_RE_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2a069483b28469fcbfa5890b04cd6439b3">kDSPI_EndOfQueueInterruptEnable</a> = SPI_RSER_EOQF_RE_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2aa430e623e0bb240752381eaddda1a973">kDSPI_TxFifoUnderflowInterruptEnable</a> = SPI_RSER_TFUF_RE_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2ada57830661d523d12e49892060fde201">kDSPI_TxFifoFillRequestInterruptEnable</a> = SPI_RSER_TFFF_RE_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2a190746a0aeaa61db32c6c1a7b850d0ee">kDSPI_RxFifoOverflowInterruptEnable</a> = SPI_RSER_RFOF_RE_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2aa7d99e6ac31bd6c7d835d89f36cec1a6">kDSPI_RxFifoDrainRequestInterruptEnable</a> = SPI_RSER_RFDF_RE_MASK,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2a530d972d6cd16ab6e929d7ddaaf09b30">kDSPI_AllInterruptEnable</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:gaeb57298690a2f1a09d94d696c893c4b2"><td class="mdescLeft"> </td><td class="mdescRight">DSPI interrupt source. <a href="group__dspi__driver.html#gaeb57298690a2f1a09d94d696c893c4b2">More...</a><br/></td></tr>
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<tr class="separator:gaeb57298690a2f1a09d94d696c893c4b2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae3359796dc0680797b1f74b83fc0c0d9"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gae3359796dc0680797b1f74b83fc0c0d9">_dspi_dma_enable</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#ggae3359796dc0680797b1f74b83fc0c0d9ae772dc49e5a28df00b817f9c6dab0749">kDSPI_TxDmaEnable</a> = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK),
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggae3359796dc0680797b1f74b83fc0c0d9a15ec9c9897199d53a1b354ccce6d0445">kDSPI_RxDmaEnable</a> = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK)
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<br/>
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}</td></tr>
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<tr class="memdesc:gae3359796dc0680797b1f74b83fc0c0d9"><td class="mdescLeft"> </td><td class="mdescRight">DSPI DMA source. <a href="group__dspi__driver.html#gae3359796dc0680797b1f74b83fc0c0d9">More...</a><br/></td></tr>
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<tr class="separator:gae3359796dc0680797b1f74b83fc0c0d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7f974015f32db057dafada8b95641aa"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad7f974015f32db057dafada8b95641aa">dspi_master_slave_mode_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#ggad7f974015f32db057dafada8b95641aaa8330c6ad827da3c783df5805244fa7d9">kDSPI_Master</a> = 1U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggad7f974015f32db057dafada8b95641aaa2e075745386fd71bee2535606f29dd87">kDSPI_Slave</a> = 0U
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<br/>
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}</td></tr>
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<tr class="memdesc:gad7f974015f32db057dafada8b95641aa"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master or slave mode configuration. <a href="group__dspi__driver.html#gad7f974015f32db057dafada8b95641aa">More...</a><br/></td></tr>
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<tr class="separator:gad7f974015f32db057dafada8b95641aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae783895e2917abe07adbe27a253510a2"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gae783895e2917abe07adbe27a253510a2">dspi_master_sample_point_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#ggae783895e2917abe07adbe27a253510a2abbcf84bafbd94a63a9600647162b8d86">kDSPI_SckToSin0Clock</a> = 0U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggae783895e2917abe07adbe27a253510a2a61e5f5d7122c849c737513ae7c5c4c50">kDSPI_SckToSin1Clock</a> = 1U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggae783895e2917abe07adbe27a253510a2a305d68c9446ca0866da7a2ace743ae4d">kDSPI_SckToSin2Clock</a> = 2U
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<br/>
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}</td></tr>
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<tr class="memdesc:gae783895e2917abe07adbe27a253510a2"><td class="mdescLeft"> </td><td class="mdescRight">DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format. <a href="group__dspi__driver.html#gae783895e2917abe07adbe27a253510a2">More...</a><br/></td></tr>
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<tr class="separator:gae783895e2917abe07adbe27a253510a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36d77cff6cfa202e0ff3a05ab4c2a632"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga36d77cff6cfa202e0ff3a05ab4c2a632">dspi_which_pcs_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga36d77cff6cfa202e0ff3a05ab4c2a632a5c6297be9586ee874fa1a84a16d810b7">kDSPI_Pcs0</a> = 1U << 0,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga36d77cff6cfa202e0ff3a05ab4c2a632a62d3c43292cebeed478a36bff2cd033a">kDSPI_Pcs1</a> = 1U << 1,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga36d77cff6cfa202e0ff3a05ab4c2a632a625c90d5151e8458be6f89ace68f2fe2">kDSPI_Pcs2</a> = 1U << 2,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga36d77cff6cfa202e0ff3a05ab4c2a632a7fae848c0f775a86562b90ecfd171cc8">kDSPI_Pcs3</a> = 1U << 3,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga36d77cff6cfa202e0ff3a05ab4c2a632a0fd968cdbfd2e088987e309f49cb20f2">kDSPI_Pcs4</a> = 1U << 4,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga36d77cff6cfa202e0ff3a05ab4c2a632a67653d39cbd675c9141bb014d4576a0b">kDSPI_Pcs5</a> = 1U << 5
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<br/>
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}</td></tr>
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<tr class="memdesc:ga36d77cff6cfa202e0ff3a05ab4c2a632"><td class="mdescLeft"> </td><td class="mdescRight">DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure). <a href="group__dspi__driver.html#ga36d77cff6cfa202e0ff3a05ab4c2a632">More...</a><br/></td></tr>
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<tr class="separator:ga36d77cff6cfa202e0ff3a05ab4c2a632"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab466e73cb54b2c023459d43918c4197d"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gab466e73cb54b2c023459d43918c4197d">dspi_pcs_polarity_config_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#ggab466e73cb54b2c023459d43918c4197da79a6807edd30a1230477ab26068060fd">kDSPI_PcsActiveHigh</a> = 0U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggab466e73cb54b2c023459d43918c4197daa678a5937bbb9975e3c014592c3d542c">kDSPI_PcsActiveLow</a> = 1U
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<br/>
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}</td></tr>
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<tr class="memdesc:gab466e73cb54b2c023459d43918c4197d"><td class="mdescLeft"> </td><td class="mdescRight">DSPI Peripheral Chip Select (Pcs) Polarity configuration. <a href="group__dspi__driver.html#gab466e73cb54b2c023459d43918c4197d">More...</a><br/></td></tr>
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<tr class="separator:gab466e73cb54b2c023459d43918c4197d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad23a66cefb04826de83504ad485f19a9"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad23a66cefb04826de83504ad485f19a9">_dspi_pcs_polarity</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9ac731b21eefcc16342d2c606a12a00547">kDSPI_Pcs0ActiveLow</a> = 1U << 0,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9aa6ee5dca40cbe9bf03623cf986adbadd">kDSPI_Pcs1ActiveLow</a> = 1U << 1,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9a6fd76d22cb6c8f943ae397bb91ba68f4">kDSPI_Pcs2ActiveLow</a> = 1U << 2,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9a57e33d7e4195864f89db11d2f5e6cc4b">kDSPI_Pcs3ActiveLow</a> = 1U << 3,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9a15c201d8e7bd0bab1dd7117b73a111ec">kDSPI_Pcs4ActiveLow</a> = 1U << 4,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9a88e1e00a5a7755561358f004a5a1b1d4">kDSPI_Pcs5ActiveLow</a> = 1U << 5,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9adb2bef5058b4bf00533cc89f1928e2d1">kDSPI_PcsAllActiveLow</a> = 0xFFU
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<br/>
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}</td></tr>
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<tr class="memdesc:gad23a66cefb04826de83504ad485f19a9"><td class="mdescLeft"> </td><td class="mdescRight">DSPI Peripheral Chip Select (Pcs) Polarity. <a href="group__dspi__driver.html#gad23a66cefb04826de83504ad485f19a9">More...</a><br/></td></tr>
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<tr class="separator:gad23a66cefb04826de83504ad485f19a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1e0a9074742794ef89f597d220296651"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga1e0a9074742794ef89f597d220296651">dspi_clock_polarity_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga1e0a9074742794ef89f597d220296651ab5279f36f0c6b1617aa937824806d71d">kDSPI_ClockPolarityActiveHigh</a> = 0U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga1e0a9074742794ef89f597d220296651abcde58b8834e5cd1181b8b98aa4a10ef">kDSPI_ClockPolarityActiveLow</a> = 1U
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<br/>
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}</td></tr>
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<tr class="memdesc:ga1e0a9074742794ef89f597d220296651"><td class="mdescLeft"> </td><td class="mdescRight">DSPI clock polarity configuration for a given CTAR. <a href="group__dspi__driver.html#ga1e0a9074742794ef89f597d220296651">More...</a><br/></td></tr>
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<tr class="separator:ga1e0a9074742794ef89f597d220296651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4269ec144334dd60666a92e6fd2c1476"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga4269ec144334dd60666a92e6fd2c1476">dspi_clock_phase_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga4269ec144334dd60666a92e6fd2c1476a996e921abbf325ee9978a42681aee0d5">kDSPI_ClockPhaseFirstEdge</a> = 0U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga4269ec144334dd60666a92e6fd2c1476a43ee643e847b3118e38da0a9811d97f9">kDSPI_ClockPhaseSecondEdge</a> = 1U
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<br/>
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}</td></tr>
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<tr class="memdesc:ga4269ec144334dd60666a92e6fd2c1476"><td class="mdescLeft"> </td><td class="mdescRight">DSPI clock phase configuration for a given CTAR. <a href="group__dspi__driver.html#ga4269ec144334dd60666a92e6fd2c1476">More...</a><br/></td></tr>
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<tr class="separator:ga4269ec144334dd60666a92e6fd2c1476"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga06fad8ae17b680f6dddfd798c9d3b30d"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga06fad8ae17b680f6dddfd798c9d3b30d">dspi_shift_direction_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga06fad8ae17b680f6dddfd798c9d3b30da8885a916a15d0b97ffd0f28d81242f6f">kDSPI_MsbFirst</a> = 0U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga06fad8ae17b680f6dddfd798c9d3b30da76701314fa7dbd70e4011feb326b9050">kDSPI_LsbFirst</a> = 1U
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<br/>
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}</td></tr>
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<tr class="memdesc:ga06fad8ae17b680f6dddfd798c9d3b30d"><td class="mdescLeft"> </td><td class="mdescRight">DSPI data shifter direction options for a given CTAR. <a href="group__dspi__driver.html#ga06fad8ae17b680f6dddfd798c9d3b30d">More...</a><br/></td></tr>
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<tr class="separator:ga06fad8ae17b680f6dddfd798c9d3b30d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ca2fbee37b3cb046c075a7e765d64ed"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga1ca2fbee37b3cb046c075a7e765d64ed">dspi_delay_type_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga1ca2fbee37b3cb046c075a7e765d64eda71185ae0d4d9dd61acbc69bce93f33f5">kDSPI_PcsToSck</a> = 1U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga1ca2fbee37b3cb046c075a7e765d64edaa2ce775b9575a3870ce82b8444b9d56c">kDSPI_LastSckToPcs</a>,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga1ca2fbee37b3cb046c075a7e765d64eda83ed3f05b8a61f94c0da066c1ded7a1e">kDSPI_BetweenTransfer</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga1ca2fbee37b3cb046c075a7e765d64ed"><td class="mdescLeft"> </td><td class="mdescRight">DSPI delay type selection. <a href="group__dspi__driver.html#ga1ca2fbee37b3cb046c075a7e765d64ed">More...</a><br/></td></tr>
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<tr class="separator:ga1ca2fbee37b3cb046c075a7e765d64ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga992d5562af4cf4c45371feb8c5c1a1bf"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfadb2a4c8c9b722c6a1b8cbb03b17a6519">kDSPI_Ctar0</a> = 0U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfad6db3f5779fd74fdfa9bda2375573227">kDSPI_Ctar1</a> = 1U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfa406d09f42f5e009617a40f4c30cc10d9">kDSPI_Ctar2</a> = 2U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfaf1df973bc8d89efbfb8d7bff51af0265">kDSPI_Ctar3</a> = 3U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfa13960000166ae1cc18b19f5c4c9405ff">kDSPI_Ctar4</a> = 4U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfad0b231829a94051ce913cd367135c1f2">kDSPI_Ctar5</a> = 5U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfaa7bb6aaabeb65811e58af0460c38e373">kDSPI_Ctar6</a> = 6U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfa6ae1a9c5243a507f36c3db1ef14c216e">kDSPI_Ctar7</a> = 7U
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<br/>
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}</td></tr>
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<tr class="memdesc:ga992d5562af4cf4c45371feb8c5c1a1bf"><td class="mdescLeft"> </td><td class="mdescRight">DSPI Clock and Transfer Attributes Register (CTAR) selection. <a href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">More...</a><br/></td></tr>
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<tr class="separator:ga992d5562af4cf4c45371feb8c5c1a1bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac74dfe19c844271a393314a4fd13792f"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gac74dfe19c844271a393314a4fd13792f">_dspi_transfer_config_flag_for_master</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792faf7ddf42278af30a1b81f10c4058ecddd">kDSPI_MasterCtar0</a> = 0U << DSPI_MASTER_CTAR_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa57508605f5d5fb0a2fb7eddfcdb89f12">kDSPI_MasterCtar1</a> = 1U << DSPI_MASTER_CTAR_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa6cf50df8fd75f5be1347efcaec8a68f4">kDSPI_MasterCtar2</a> = 2U << DSPI_MASTER_CTAR_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa70471fdf900dba881f4e742d303d307c">kDSPI_MasterCtar3</a> = 3U << DSPI_MASTER_CTAR_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792faad989e96bfed1f2fbb0fcc3adb99d04b">kDSPI_MasterCtar4</a> = 4U << DSPI_MASTER_CTAR_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa5c3dbe0ddb8e9f3f67496592ef3ec902">kDSPI_MasterCtar5</a> = 5U << DSPI_MASTER_CTAR_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa5e898da1cd4e093f048f947bc751b7fa">kDSPI_MasterCtar6</a> = 6U << DSPI_MASTER_CTAR_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa90cf553b9933d1e3d692469e0fa5ddc3">kDSPI_MasterCtar7</a> = 7U << DSPI_MASTER_CTAR_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fad51bd34d51062d900b07801e0fd193cc">kDSPI_MasterPcs0</a> = 0U << DSPI_MASTER_PCS_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fad07c95fafd30869cb6110d4ea3ed7ca1">kDSPI_MasterPcs1</a> = 1U << DSPI_MASTER_PCS_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa116fef8c0a72727a80e72e1d1d0d0ffc">kDSPI_MasterPcs2</a> = 2U << DSPI_MASTER_PCS_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa2266cc2ddbf05da3164fa6ad680facd9">kDSPI_MasterPcs3</a> = 3U << DSPI_MASTER_PCS_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa3b32f4a57a5aaaaf0064d7ec1373a154">kDSPI_MasterPcs4</a> = 4U << DSPI_MASTER_PCS_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa8047faff72926a57c0659f4147787353">kDSPI_MasterPcs5</a> = 5U << DSPI_MASTER_PCS_SHIFT,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa8309b1b52bbaa930bbcc3e2407f1a6f5">kDSPI_MasterPcsContinuous</a> = 1U << 20,
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<br/>
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  <a class="el" href="group__dspi__driver.html#ggac74dfe19c844271a393314a4fd13792fa458df11cc493759474f31873cfa8d4c1">kDSPI_MasterActiveAfterTransfer</a> = 1U << 21
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<br/>
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}</td></tr>
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<tr class="memdesc:gac74dfe19c844271a393314a4fd13792f"><td class="mdescLeft"> </td><td class="mdescRight">Can use this enumeration for DSPI master transfer configFlags. <a href="group__dspi__driver.html#gac74dfe19c844271a393314a4fd13792f">More...</a><br/></td></tr>
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<tr class="separator:gac74dfe19c844271a393314a4fd13792f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5070a73633ee72428adda72058f7fb5f"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga5070a73633ee72428adda72058f7fb5f">_dspi_transfer_config_flag_for_slave</a> { <a class="el" href="group__dspi__driver.html#gga5070a73633ee72428adda72058f7fb5fa6e63c217f9b392f78fb96ee039c991c8">kDSPI_SlaveCtar0</a> = 0U << DSPI_SLAVE_CTAR_SHIFT
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}</td></tr>
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<tr class="memdesc:ga5070a73633ee72428adda72058f7fb5f"><td class="mdescLeft"> </td><td class="mdescRight">Can use this enum for DSPI slave transfer configFlags. <a href="group__dspi__driver.html#ga5070a73633ee72428adda72058f7fb5f">More...</a><br/></td></tr>
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<tr class="separator:ga5070a73633ee72428adda72058f7fb5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga97c65523863f89cddbf06691c678a7f9"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga97c65523863f89cddbf06691c678a7f9">_dspi_transfer_state</a> { <br/>
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  <a class="el" href="group__dspi__driver.html#gga97c65523863f89cddbf06691c678a7f9ae739fb0dabff3a7cb72c39eef943a373">kDSPI_Idle</a> = 0x0U,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga97c65523863f89cddbf06691c678a7f9a4b636d65ab83d136e81ed31e30de4429">kDSPI_Busy</a>,
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<br/>
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  <a class="el" href="group__dspi__driver.html#gga97c65523863f89cddbf06691c678a7f9a6d94f11a50f542371683efe9ea22efb9">kDSPI_Error</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga97c65523863f89cddbf06691c678a7f9"><td class="mdescLeft"> </td><td class="mdescRight">DSPI transfer state, which is used for DSPI transactional API state machine. <a href="group__dspi__driver.html#ga97c65523863f89cddbf06691c678a7f9">More...</a><br/></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Driver version</h2></td></tr>
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<tr class="memitem:ga9ed59b934c560c5d88000b17b8171a01"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga9ed59b934c560c5d88000b17b8171a01">FSL_DSPI_DRIVER_VERSION</a>   (<a class="el" href="group__flash__driver.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 1, 1))</td></tr>
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<tr class="memdesc:ga9ed59b934c560c5d88000b17b8171a01"><td class="mdescLeft"> </td><td class="mdescRight">DSPI driver version 2.1.1. <a href="#ga9ed59b934c560c5d88000b17b8171a01">More...</a><br/></td></tr>
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<tr class="separator:ga9ed59b934c560c5d88000b17b8171a01"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Initialization and deinitialization</h2></td></tr>
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<tr class="memitem:gaadf23f732f4c1b61d6634bd17b1a36d7"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gaadf23f732f4c1b61d6634bd17b1a36d7">DSPI_MasterInit</a> (SPI_Type *base, const <a class="el" href="group__dspi__driver.html#structdspi__master__config__t">dspi_master_config_t</a> *masterConfig, uint32_t srcClock_Hz)</td></tr>
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<tr class="memdesc:gaadf23f732f4c1b61d6634bd17b1a36d7"><td class="mdescLeft"> </td><td class="mdescRight">Initializes the DSPI master. <a href="#gaadf23f732f4c1b61d6634bd17b1a36d7">More...</a><br/></td></tr>
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<tr class="separator:gaadf23f732f4c1b61d6634bd17b1a36d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0061c90bc787dc1faffde79cb256e8a4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga0061c90bc787dc1faffde79cb256e8a4">DSPI_MasterGetDefaultConfig</a> (<a class="el" href="group__dspi__driver.html#structdspi__master__config__t">dspi_master_config_t</a> *masterConfig)</td></tr>
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<tr class="memdesc:ga0061c90bc787dc1faffde79cb256e8a4"><td class="mdescLeft"> </td><td class="mdescRight">Sets the <a class="el" href="group__dspi__driver.html#structdspi__master__config__t" title="DSPI master configuration structure. ">dspi_master_config_t</a> structure to default values. <a href="#ga0061c90bc787dc1faffde79cb256e8a4">More...</a><br/></td></tr>
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<tr class="separator:ga0061c90bc787dc1faffde79cb256e8a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacf6cecb6b73f02eaa448634a8d705851"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gacf6cecb6b73f02eaa448634a8d705851">DSPI_SlaveInit</a> (SPI_Type *base, const <a class="el" href="group__dspi__driver.html#structdspi__slave__config__t">dspi_slave_config_t</a> *slaveConfig)</td></tr>
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<tr class="memdesc:gacf6cecb6b73f02eaa448634a8d705851"><td class="mdescLeft"> </td><td class="mdescRight">DSPI slave configuration. <a href="#gacf6cecb6b73f02eaa448634a8d705851">More...</a><br/></td></tr>
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<tr class="separator:gacf6cecb6b73f02eaa448634a8d705851"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad85a8d4e7bd2747103691a63ef9a67e1"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad85a8d4e7bd2747103691a63ef9a67e1">DSPI_SlaveGetDefaultConfig</a> (<a class="el" href="group__dspi__driver.html#structdspi__slave__config__t">dspi_slave_config_t</a> *slaveConfig)</td></tr>
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<tr class="memdesc:gad85a8d4e7bd2747103691a63ef9a67e1"><td class="mdescLeft"> </td><td class="mdescRight">Sets the <a class="el" href="group__dspi__driver.html#structdspi__slave__config__t" title="DSPI slave configuration structure. ">dspi_slave_config_t</a> structure to default values. <a href="#gad85a8d4e7bd2747103691a63ef9a67e1">More...</a><br/></td></tr>
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<tr class="separator:gad85a8d4e7bd2747103691a63ef9a67e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa669bb8f6438b1d4f7ec38ba180653fa"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gaa669bb8f6438b1d4f7ec38ba180653fa">DSPI_Deinit</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:gaa669bb8f6438b1d4f7ec38ba180653fa"><td class="mdescLeft"> </td><td class="mdescRight">De-initializes the DSPI peripheral. <a href="#gaa669bb8f6438b1d4f7ec38ba180653fa">More...</a><br/></td></tr>
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<tr class="separator:gaa669bb8f6438b1d4f7ec38ba180653fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38a2ee1ed351246ebbdc4b242b835164"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga38a2ee1ed351246ebbdc4b242b835164">DSPI_Enable</a> (SPI_Type *base, bool enable)</td></tr>
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<tr class="memdesc:ga38a2ee1ed351246ebbdc4b242b835164"><td class="mdescLeft"> </td><td class="mdescRight">Enables the DSPI peripheral and sets the MCR MDIS to 0. <a href="#ga38a2ee1ed351246ebbdc4b242b835164">More...</a><br/></td></tr>
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<tr class="separator:ga38a2ee1ed351246ebbdc4b242b835164"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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Status</h2></td></tr>
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<tr class="memitem:ga11005216bf792c91894d9e670b0323f8"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga11005216bf792c91894d9e670b0323f8">DSPI_GetStatusFlags</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:ga11005216bf792c91894d9e670b0323f8"><td class="mdescLeft"> </td><td class="mdescRight">Gets the DSPI status flag state. <a href="#ga11005216bf792c91894d9e670b0323f8">More...</a><br/></td></tr>
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<tr class="separator:ga11005216bf792c91894d9e670b0323f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga11454768ad4c96b65b298cccf1f0401c"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga11454768ad4c96b65b298cccf1f0401c">DSPI_ClearStatusFlags</a> (SPI_Type *base, uint32_t statusFlags)</td></tr>
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<tr class="memdesc:ga11454768ad4c96b65b298cccf1f0401c"><td class="mdescLeft"> </td><td class="mdescRight">Clears the DSPI status flag. <a href="#ga11454768ad4c96b65b298cccf1f0401c">More...</a><br/></td></tr>
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<tr class="separator:ga11454768ad4c96b65b298cccf1f0401c"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Interrupts</h2></td></tr>
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<tr class="memitem:ga9b9e4c8ae54ea108952c80940e11b3a8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga9b9e4c8ae54ea108952c80940e11b3a8">DSPI_EnableInterrupts</a> (SPI_Type *base, uint32_t mask)</td></tr>
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<tr class="memdesc:ga9b9e4c8ae54ea108952c80940e11b3a8"><td class="mdescLeft"> </td><td class="mdescRight">Enables the DSPI interrupts. <a href="#ga9b9e4c8ae54ea108952c80940e11b3a8">More...</a><br/></td></tr>
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<tr class="separator:ga9b9e4c8ae54ea108952c80940e11b3a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabf5c4ec1216387b8c476853e45a9bfeb"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gabf5c4ec1216387b8c476853e45a9bfeb">DSPI_DisableInterrupts</a> (SPI_Type *base, uint32_t mask)</td></tr>
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<tr class="memdesc:gabf5c4ec1216387b8c476853e45a9bfeb"><td class="mdescLeft"> </td><td class="mdescRight">Disables the DSPI interrupts. <a href="#gabf5c4ec1216387b8c476853e45a9bfeb">More...</a><br/></td></tr>
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<tr class="separator:gabf5c4ec1216387b8c476853e45a9bfeb"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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DMA Control</h2></td></tr>
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<tr class="memitem:ga313d41fd54ca75781bb7596b319d4849"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga313d41fd54ca75781bb7596b319d4849">DSPI_EnableDMA</a> (SPI_Type *base, uint32_t mask)</td></tr>
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<tr class="memdesc:ga313d41fd54ca75781bb7596b319d4849"><td class="mdescLeft"> </td><td class="mdescRight">Enables the DSPI DMA request. <a href="#ga313d41fd54ca75781bb7596b319d4849">More...</a><br/></td></tr>
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<tr class="separator:ga313d41fd54ca75781bb7596b319d4849"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga543b12952cb5ac404ebbdaa572628c8e"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga543b12952cb5ac404ebbdaa572628c8e">DSPI_DisableDMA</a> (SPI_Type *base, uint32_t mask)</td></tr>
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<tr class="memdesc:ga543b12952cb5ac404ebbdaa572628c8e"><td class="mdescLeft"> </td><td class="mdescRight">Disables the DSPI DMA request. <a href="#ga543b12952cb5ac404ebbdaa572628c8e">More...</a><br/></td></tr>
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<tr class="separator:ga543b12952cb5ac404ebbdaa572628c8e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3e8a8107cfda29dbae45fc5166d63f3"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad3e8a8107cfda29dbae45fc5166d63f3">DSPI_MasterGetTxRegisterAddress</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:gad3e8a8107cfda29dbae45fc5166d63f3"><td class="mdescLeft"> </td><td class="mdescRight">Gets the DSPI master PUSHR data register address for the DMA operation. <a href="#gad3e8a8107cfda29dbae45fc5166d63f3">More...</a><br/></td></tr>
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<tr class="separator:gad3e8a8107cfda29dbae45fc5166d63f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8912754715dfadde5473a419f7b8ff93"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga8912754715dfadde5473a419f7b8ff93">DSPI_SlaveGetTxRegisterAddress</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:ga8912754715dfadde5473a419f7b8ff93"><td class="mdescLeft"> </td><td class="mdescRight">Gets the DSPI slave PUSHR data register address for the DMA operation. <a href="#ga8912754715dfadde5473a419f7b8ff93">More...</a><br/></td></tr>
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<tr class="separator:ga8912754715dfadde5473a419f7b8ff93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0d2bcb0a744852ab2701466a7fd974f6"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga0d2bcb0a744852ab2701466a7fd974f6">DSPI_GetRxRegisterAddress</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:ga0d2bcb0a744852ab2701466a7fd974f6"><td class="mdescLeft"> </td><td class="mdescRight">Gets the DSPI POPR data register address for the DMA operation. <a href="#ga0d2bcb0a744852ab2701466a7fd974f6">More...</a><br/></td></tr>
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<tr class="separator:ga0d2bcb0a744852ab2701466a7fd974f6"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Bus Operations</h2></td></tr>
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<tr class="memitem:gac3e11f3876e81d7636a77fb268c2365a"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gac3e11f3876e81d7636a77fb268c2365a">DSPI_SetMasterSlaveMode</a> (SPI_Type *base, <a class="el" href="group__dspi__driver.html#gad7f974015f32db057dafada8b95641aa">dspi_master_slave_mode_t</a> mode)</td></tr>
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<tr class="memdesc:gac3e11f3876e81d7636a77fb268c2365a"><td class="mdescLeft"> </td><td class="mdescRight">Configures the DSPI for master or slave. <a href="#gac3e11f3876e81d7636a77fb268c2365a">More...</a><br/></td></tr>
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<tr class="separator:gac3e11f3876e81d7636a77fb268c2365a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae606c91960692b493d17d067c38d67b3"><td class="memItemLeft" align="right" valign="top">static bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gae606c91960692b493d17d067c38d67b3">DSPI_IsMaster</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:gae606c91960692b493d17d067c38d67b3"><td class="mdescLeft"> </td><td class="mdescRight">Returns whether the DSPI module is in master mode. <a href="#gae606c91960692b493d17d067c38d67b3">More...</a><br/></td></tr>
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<tr class="separator:gae606c91960692b493d17d067c38d67b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3fb40ea05b407f5b335c0a47330e3a8"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gac3fb40ea05b407f5b335c0a47330e3a8">DSPI_StartTransfer</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:gac3fb40ea05b407f5b335c0a47330e3a8"><td class="mdescLeft"> </td><td class="mdescRight">Starts the DSPI transfers and clears HALT bit in MCR. <a href="#gac3fb40ea05b407f5b335c0a47330e3a8">More...</a><br/></td></tr>
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<tr class="separator:gac3fb40ea05b407f5b335c0a47330e3a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09021ebd27d4ccf5d85398b5bbf12045"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga09021ebd27d4ccf5d85398b5bbf12045">DSPI_StopTransfer</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:ga09021ebd27d4ccf5d85398b5bbf12045"><td class="mdescLeft"> </td><td class="mdescRight">Stops (halts) DSPI transfers and sets HALT bit in MCR. <a href="#ga09021ebd27d4ccf5d85398b5bbf12045">More...</a><br/></td></tr>
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<tr class="separator:ga09021ebd27d4ccf5d85398b5bbf12045"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9112153c575eeeb6af747d9e6396514"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad9112153c575eeeb6af747d9e6396514">DSPI_SetFifoEnable</a> (SPI_Type *base, bool enableTxFifo, bool enableRxFifo)</td></tr>
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<tr class="memdesc:gad9112153c575eeeb6af747d9e6396514"><td class="mdescLeft"> </td><td class="mdescRight">Enables (or disables) the DSPI FIFOs. <a href="#gad9112153c575eeeb6af747d9e6396514">More...</a><br/></td></tr>
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<tr class="separator:gad9112153c575eeeb6af747d9e6396514"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3cbb532b5bd6981f5cc0115f49a9ee9a"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga3cbb532b5bd6981f5cc0115f49a9ee9a">DSPI_FlushFifo</a> (SPI_Type *base, bool flushTxFifo, bool flushRxFifo)</td></tr>
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<tr class="memdesc:ga3cbb532b5bd6981f5cc0115f49a9ee9a"><td class="mdescLeft"> </td><td class="mdescRight">Flushes the DSPI FIFOs. <a href="#ga3cbb532b5bd6981f5cc0115f49a9ee9a">More...</a><br/></td></tr>
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<tr class="separator:ga3cbb532b5bd6981f5cc0115f49a9ee9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1c42d5efc75982041f4a66f4f1fc71a4"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga1c42d5efc75982041f4a66f4f1fc71a4">DSPI_SetAllPcsPolarity</a> (SPI_Type *base, uint32_t mask)</td></tr>
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<tr class="memdesc:ga1c42d5efc75982041f4a66f4f1fc71a4"><td class="mdescLeft"> </td><td class="mdescRight">Configures the DSPI peripheral chip select polarity simultaneously. <a href="#ga1c42d5efc75982041f4a66f4f1fc71a4">More...</a><br/></td></tr>
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<tr class="separator:ga1c42d5efc75982041f4a66f4f1fc71a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac76cf793dd837dd0b502770913058592"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gac76cf793dd837dd0b502770913058592">DSPI_MasterSetBaudRate</a> (SPI_Type *base, <a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> whichCtar, uint32_t baudRate_Bps, uint32_t srcClock_Hz)</td></tr>
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<tr class="memdesc:gac76cf793dd837dd0b502770913058592"><td class="mdescLeft"> </td><td class="mdescRight">Sets the DSPI baud rate in bits per second. <a href="#gac76cf793dd837dd0b502770913058592">More...</a><br/></td></tr>
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<tr class="separator:gac76cf793dd837dd0b502770913058592"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56d5b87114e56507c0ec2d631ffefaa2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga56d5b87114e56507c0ec2d631ffefaa2">DSPI_MasterSetDelayScaler</a> (SPI_Type *base, <a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> whichCtar, uint32_t prescaler, uint32_t scaler, <a class="el" href="group__dspi__driver.html#ga1ca2fbee37b3cb046c075a7e765d64ed">dspi_delay_type_t</a> whichDelay)</td></tr>
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<tr class="memdesc:ga56d5b87114e56507c0ec2d631ffefaa2"><td class="mdescLeft"> </td><td class="mdescRight">Manually configures the delay prescaler and scaler for a particular CTAR. <a href="#ga56d5b87114e56507c0ec2d631ffefaa2">More...</a><br/></td></tr>
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<tr class="separator:ga56d5b87114e56507c0ec2d631ffefaa2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac60f64fd410404ebab553ee878b464c2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gac60f64fd410404ebab553ee878b464c2">DSPI_MasterSetDelayTimes</a> (SPI_Type *base, <a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> whichCtar, <a class="el" href="group__dspi__driver.html#ga1ca2fbee37b3cb046c075a7e765d64ed">dspi_delay_type_t</a> whichDelay, uint32_t srcClock_Hz, uint32_t delayTimeInNanoSec)</td></tr>
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<tr class="memdesc:gac60f64fd410404ebab553ee878b464c2"><td class="mdescLeft"> </td><td class="mdescRight">Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. <a href="#gac60f64fd410404ebab553ee878b464c2">More...</a><br/></td></tr>
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<tr class="separator:gac60f64fd410404ebab553ee878b464c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabe0d615b273c4cb0eaf26d9679b73ad6"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gabe0d615b273c4cb0eaf26d9679b73ad6">DSPI_MasterWriteData</a> (SPI_Type *base, <a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> *command, uint16_t data)</td></tr>
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<tr class="memdesc:gabe0d615b273c4cb0eaf26d9679b73ad6"><td class="mdescLeft"> </td><td class="mdescRight">Writes data into the data buffer for master mode. <a href="#gabe0d615b273c4cb0eaf26d9679b73ad6">More...</a><br/></td></tr>
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<tr class="separator:gabe0d615b273c4cb0eaf26d9679b73ad6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad9f3df616e7284696af57cce8f49899e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad9f3df616e7284696af57cce8f49899e">DSPI_GetDefaultDataCommandConfig</a> (<a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> *command)</td></tr>
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<tr class="memdesc:gad9f3df616e7284696af57cce8f49899e"><td class="mdescLeft"> </td><td class="mdescRight">Sets the <a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t" title="DSPI master command date configuration used for SPIx_PUSHR. ">dspi_command_data_config_t</a> structure to default values. <a href="#gad9f3df616e7284696af57cce8f49899e">More...</a><br/></td></tr>
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<tr class="separator:gad9f3df616e7284696af57cce8f49899e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga70a0f7d7fe2fbce7993bbcc8c427b2b0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga70a0f7d7fe2fbce7993bbcc8c427b2b0">DSPI_MasterWriteDataBlocking</a> (SPI_Type *base, <a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> *command, uint16_t data)</td></tr>
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<tr class="memdesc:ga70a0f7d7fe2fbce7993bbcc8c427b2b0"><td class="mdescLeft"> </td><td class="mdescRight">Writes data into the data buffer master mode and waits till complete to return. <a href="#ga70a0f7d7fe2fbce7993bbcc8c427b2b0">More...</a><br/></td></tr>
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<tr class="separator:ga70a0f7d7fe2fbce7993bbcc8c427b2b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4068b27da40c419a700badf2070fc5e4"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga4068b27da40c419a700badf2070fc5e4">DSPI_MasterGetFormattedCommand</a> (<a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> *command)</td></tr>
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<tr class="memdesc:ga4068b27da40c419a700badf2070fc5e4"><td class="mdescLeft"> </td><td class="mdescRight">Returns the DSPI command word formatted to the PUSHR data register bit field. <a href="#ga4068b27da40c419a700badf2070fc5e4">More...</a><br/></td></tr>
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<tr class="separator:ga4068b27da40c419a700badf2070fc5e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0718581088422b572cb4494f26aad1f9"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga0718581088422b572cb4494f26aad1f9">DSPI_MasterWriteCommandDataBlocking</a> (SPI_Type *base, uint32_t data)</td></tr>
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<tr class="memdesc:ga0718581088422b572cb4494f26aad1f9"><td class="mdescLeft"> </td><td class="mdescRight">Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data buffer, master mode and waits till complete to return. <a href="#ga0718581088422b572cb4494f26aad1f9">More...</a><br/></td></tr>
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<tr class="separator:ga0718581088422b572cb4494f26aad1f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga952c2bfcb7e3ac7d3608ec16add273dc"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga952c2bfcb7e3ac7d3608ec16add273dc">DSPI_SlaveWriteData</a> (SPI_Type *base, uint32_t data)</td></tr>
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<tr class="memdesc:ga952c2bfcb7e3ac7d3608ec16add273dc"><td class="mdescLeft"> </td><td class="mdescRight">Writes data into the data buffer in slave mode. <a href="#ga952c2bfcb7e3ac7d3608ec16add273dc">More...</a><br/></td></tr>
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<tr class="separator:ga952c2bfcb7e3ac7d3608ec16add273dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad7a98ccdb5dcd3ea9c282893b79cee79"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad7a98ccdb5dcd3ea9c282893b79cee79">DSPI_SlaveWriteDataBlocking</a> (SPI_Type *base, uint32_t data)</td></tr>
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<tr class="memdesc:gad7a98ccdb5dcd3ea9c282893b79cee79"><td class="mdescLeft"> </td><td class="mdescRight">Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. <a href="#gad7a98ccdb5dcd3ea9c282893b79cee79">More...</a><br/></td></tr>
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<tr class="separator:gad7a98ccdb5dcd3ea9c282893b79cee79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee93673062a6fb105dcf1e0541dd8b52"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gaee93673062a6fb105dcf1e0541dd8b52">DSPI_ReadData</a> (SPI_Type *base)</td></tr>
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<tr class="memdesc:gaee93673062a6fb105dcf1e0541dd8b52"><td class="mdescLeft"> </td><td class="mdescRight">Reads data from the data buffer. <a href="#gaee93673062a6fb105dcf1e0541dd8b52">More...</a><br/></td></tr>
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<tr class="separator:gaee93673062a6fb105dcf1e0541dd8b52"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Transactional</h2></td></tr>
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<tr class="memitem:ga63e04b92d99d795cf84df62379765a91"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga63e04b92d99d795cf84df62379765a91">DSPI_MasterTransferCreateHandle</a> (SPI_Type *base, dspi_master_handle_t *handle, <a class="el" href="group__dspi__driver.html#gad191922bda6ac07f95f241a67eb52f48">dspi_master_transfer_callback_t</a> callback, void *userData)</td></tr>
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<tr class="memdesc:ga63e04b92d99d795cf84df62379765a91"><td class="mdescLeft"> </td><td class="mdescRight">Initializes the DSPI master handle. <a href="#ga63e04b92d99d795cf84df62379765a91">More...</a><br/></td></tr>
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<tr class="separator:ga63e04b92d99d795cf84df62379765a91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2d0aa3acb2acc3cc5413314d758628b"><td class="memItemLeft" align="right" valign="top">status_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gab2d0aa3acb2acc3cc5413314d758628b">DSPI_MasterTransferBlocking</a> (SPI_Type *base, <a class="el" href="group__dspi__driver.html#structdspi__transfer__t">dspi_transfer_t</a> *transfer)</td></tr>
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<tr class="memdesc:gab2d0aa3acb2acc3cc5413314d758628b"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master transfer data using polling. <a href="#gab2d0aa3acb2acc3cc5413314d758628b">More...</a><br/></td></tr>
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<tr class="separator:gab2d0aa3acb2acc3cc5413314d758628b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad3dc7b85b448ce6e16e227d7bf3769d6"><td class="memItemLeft" align="right" valign="top">status_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gad3dc7b85b448ce6e16e227d7bf3769d6">DSPI_MasterTransferNonBlocking</a> (SPI_Type *base, dspi_master_handle_t *handle, <a class="el" href="group__dspi__driver.html#structdspi__transfer__t">dspi_transfer_t</a> *transfer)</td></tr>
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<tr class="memdesc:gad3dc7b85b448ce6e16e227d7bf3769d6"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master transfer data using interrupts. <a href="#gad3dc7b85b448ce6e16e227d7bf3769d6">More...</a><br/></td></tr>
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<tr class="separator:gad3dc7b85b448ce6e16e227d7bf3769d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadaf98a7213c03f10d5820d363e827a73"><td class="memItemLeft" align="right" valign="top">status_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gadaf98a7213c03f10d5820d363e827a73">DSPI_MasterTransferGetCount</a> (SPI_Type *base, dspi_master_handle_t *handle, size_t *count)</td></tr>
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<tr class="memdesc:gadaf98a7213c03f10d5820d363e827a73"><td class="mdescLeft"> </td><td class="mdescRight">Gets the master transfer count. <a href="#gadaf98a7213c03f10d5820d363e827a73">More...</a><br/></td></tr>
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<tr class="separator:gadaf98a7213c03f10d5820d363e827a73"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80633e998c10cb83685d6c64ecd33a55"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga80633e998c10cb83685d6c64ecd33a55">DSPI_MasterTransferAbort</a> (SPI_Type *base, dspi_master_handle_t *handle)</td></tr>
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<tr class="memdesc:ga80633e998c10cb83685d6c64ecd33a55"><td class="mdescLeft"> </td><td class="mdescRight">DSPI master aborts transfer using an interrupt. <a href="#ga80633e998c10cb83685d6c64ecd33a55">More...</a><br/></td></tr>
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<tr class="separator:ga80633e998c10cb83685d6c64ecd33a55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga195eed1bfdc0d21e7adb76a5d6d247dc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga195eed1bfdc0d21e7adb76a5d6d247dc">DSPI_MasterTransferHandleIRQ</a> (SPI_Type *base, dspi_master_handle_t *handle)</td></tr>
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<tr class="memdesc:ga195eed1bfdc0d21e7adb76a5d6d247dc"><td class="mdescLeft"> </td><td class="mdescRight">DSPI Master IRQ handler function. <a href="#ga195eed1bfdc0d21e7adb76a5d6d247dc">More...</a><br/></td></tr>
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<tr class="separator:ga195eed1bfdc0d21e7adb76a5d6d247dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc23691aa2c06ae9076a5f0b16f33a8c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gadc23691aa2c06ae9076a5f0b16f33a8c">DSPI_SlaveTransferCreateHandle</a> (SPI_Type *base, dspi_slave_handle_t *handle, <a class="el" href="group__dspi__driver.html#ga0c9ef1b6a6d8034b5e47b8310f2d52dc">dspi_slave_transfer_callback_t</a> callback, void *userData)</td></tr>
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<tr class="memdesc:gadc23691aa2c06ae9076a5f0b16f33a8c"><td class="mdescLeft"> </td><td class="mdescRight">Initializes the DSPI slave handle. <a href="#gadc23691aa2c06ae9076a5f0b16f33a8c">More...</a><br/></td></tr>
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<tr class="separator:gadc23691aa2c06ae9076a5f0b16f33a8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81f85324750f75b8e7248846c88d99e7"><td class="memItemLeft" align="right" valign="top">status_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga81f85324750f75b8e7248846c88d99e7">DSPI_SlaveTransferNonBlocking</a> (SPI_Type *base, dspi_slave_handle_t *handle, <a class="el" href="group__dspi__driver.html#structdspi__transfer__t">dspi_transfer_t</a> *transfer)</td></tr>
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<tr class="memdesc:ga81f85324750f75b8e7248846c88d99e7"><td class="mdescLeft"> </td><td class="mdescRight">DSPI slave transfers data using an interrupt. <a href="#ga81f85324750f75b8e7248846c88d99e7">More...</a><br/></td></tr>
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<tr class="separator:ga81f85324750f75b8e7248846c88d99e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4134bb536420951e8ecbe8edb987d199"><td class="memItemLeft" align="right" valign="top">status_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga4134bb536420951e8ecbe8edb987d199">DSPI_SlaveTransferGetCount</a> (SPI_Type *base, dspi_slave_handle_t *handle, size_t *count)</td></tr>
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<tr class="memdesc:ga4134bb536420951e8ecbe8edb987d199"><td class="mdescLeft"> </td><td class="mdescRight">Gets the slave transfer count. <a href="#ga4134bb536420951e8ecbe8edb987d199">More...</a><br/></td></tr>
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<tr class="separator:ga4134bb536420951e8ecbe8edb987d199"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7e1be1f74fd8d372ce1af52c960d1361"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ga7e1be1f74fd8d372ce1af52c960d1361">DSPI_SlaveTransferAbort</a> (SPI_Type *base, dspi_slave_handle_t *handle)</td></tr>
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<tr class="memdesc:ga7e1be1f74fd8d372ce1af52c960d1361"><td class="mdescLeft"> </td><td class="mdescRight">DSPI slave aborts a transfer using an interrupt. <a href="#ga7e1be1f74fd8d372ce1af52c960d1361">More...</a><br/></td></tr>
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<tr class="separator:ga7e1be1f74fd8d372ce1af52c960d1361"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade8288c503cc6c7af542cdc86947ecd3"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#gade8288c503cc6c7af542cdc86947ecd3">DSPI_SlaveTransferHandleIRQ</a> (SPI_Type *base, dspi_slave_handle_t *handle)</td></tr>
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<tr class="memdesc:gade8288c503cc6c7af542cdc86947ecd3"><td class="mdescLeft"> </td><td class="mdescRight">DSPI Master IRQ handler function. <a href="#gade8288c503cc6c7af542cdc86947ecd3">More...</a><br/></td></tr>
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<tr class="separator:gade8288c503cc6c7af542cdc86947ecd3"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<hr/><h2 class="groupheader">Data Structure Documentation</h2>
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<a name="structdspi__command__data__config__t" id="structdspi__command__data__config__t"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname">struct dspi_command_data_config_t</td>
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</tr>
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</table>
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</div><div class="memdoc">
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<div class="textblock"></div><table class="memberdecls">
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:a1b7521543b11fe504f32d7beb728c14d"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a1b7521543b11fe504f32d7beb728c14d">isPcsContinuous</a></td></tr>
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<tr class="memdesc:a1b7521543b11fe504f32d7beb728c14d"><td class="mdescLeft"> </td><td class="mdescRight">Option to enable the continuous assertion of chip select between transfers. <a href="#a1b7521543b11fe504f32d7beb728c14d">More...</a><br/></td></tr>
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<tr class="separator:a1b7521543b11fe504f32d7beb728c14d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4cf94a2dd0b6fbab04b32349b68363b5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a4cf94a2dd0b6fbab04b32349b68363b5">whichCtar</a></td></tr>
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<tr class="memdesc:a4cf94a2dd0b6fbab04b32349b68363b5"><td class="mdescLeft"> </td><td class="mdescRight">The desired Clock and Transfer Attributes Register (CTAR) to use for CTAS. <a href="#a4cf94a2dd0b6fbab04b32349b68363b5">More...</a><br/></td></tr>
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<tr class="separator:a4cf94a2dd0b6fbab04b32349b68363b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aedc892927ff6ec53266a60b413684ace"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga36d77cff6cfa202e0ff3a05ab4c2a632">dspi_which_pcs_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aedc892927ff6ec53266a60b413684ace">whichPcs</a></td></tr>
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<tr class="memdesc:aedc892927ff6ec53266a60b413684ace"><td class="mdescLeft"> </td><td class="mdescRight">The desired PCS signal to use for the data transfer. <a href="#aedc892927ff6ec53266a60b413684ace">More...</a><br/></td></tr>
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<tr class="separator:aedc892927ff6ec53266a60b413684ace"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a378b8b8a618355869de07b435ad52f82"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a378b8b8a618355869de07b435ad52f82">isEndOfQueue</a></td></tr>
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<tr class="memdesc:a378b8b8a618355869de07b435ad52f82"><td class="mdescLeft"> </td><td class="mdescRight">Signals that the current transfer is the last in the queue. <a href="#a378b8b8a618355869de07b435ad52f82">More...</a><br/></td></tr>
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<tr class="separator:a378b8b8a618355869de07b435ad52f82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf4b200e2ca05a92686ff5e158e3a61f"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aaf4b200e2ca05a92686ff5e158e3a61f">clearTransferCount</a></td></tr>
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<tr class="memdesc:aaf4b200e2ca05a92686ff5e158e3a61f"><td class="mdescLeft"> </td><td class="mdescRight">Clears SPI Transfer Counter (SPI_TCNT) before transmission starts. <a href="#aaf4b200e2ca05a92686ff5e158e3a61f">More...</a><br/></td></tr>
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<h4 class="groupheader">Field Documentation</h4>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> dspi_command_data_config_t::whichCtar</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga36d77cff6cfa202e0ff3a05ab4c2a632">dspi_which_pcs_t</a> dspi_command_data_config_t::whichPcs</td>
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<td class="memname">bool dspi_command_data_config_t::isEndOfQueue</td>
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<td class="memname">bool dspi_command_data_config_t::clearTransferCount</td>
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<a name="structdspi__master__ctar__config__t" id="structdspi__master__ctar__config__t"></a>
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<td class="memname">struct dspi_master_ctar_config_t</td>
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:abc9dde7dd3b924290ecd6180f7a7e0cb"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#abc9dde7dd3b924290ecd6180f7a7e0cb">baudRate</a></td></tr>
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<tr class="memdesc:abc9dde7dd3b924290ecd6180f7a7e0cb"><td class="mdescLeft"> </td><td class="mdescRight">Baud Rate for DSPI. <a href="#abc9dde7dd3b924290ecd6180f7a7e0cb">More...</a><br/></td></tr>
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<tr class="memitem:a935cc12276a643aac250e07b6fd26841"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a935cc12276a643aac250e07b6fd26841">bitsPerFrame</a></td></tr>
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<tr class="memdesc:a935cc12276a643aac250e07b6fd26841"><td class="mdescLeft"> </td><td class="mdescRight">Bits per frame, minimum 4, maximum 16. <a href="#a935cc12276a643aac250e07b6fd26841">More...</a><br/></td></tr>
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<tr class="memitem:a87112137c6b8b714d1700756557c86c9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga1e0a9074742794ef89f597d220296651">dspi_clock_polarity_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a87112137c6b8b714d1700756557c86c9">cpol</a></td></tr>
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<tr class="memdesc:a87112137c6b8b714d1700756557c86c9"><td class="mdescLeft"> </td><td class="mdescRight">Clock polarity. <a href="#a87112137c6b8b714d1700756557c86c9">More...</a><br/></td></tr>
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<tr class="memitem:a3649f0e62d8f5421366afb76792e957b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga4269ec144334dd60666a92e6fd2c1476">dspi_clock_phase_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a3649f0e62d8f5421366afb76792e957b">cpha</a></td></tr>
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<tr class="memdesc:a3649f0e62d8f5421366afb76792e957b"><td class="mdescLeft"> </td><td class="mdescRight">Clock phase. <a href="#a3649f0e62d8f5421366afb76792e957b">More...</a><br/></td></tr>
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<tr class="memitem:aafbec5b2cc4cdec420381f29b32a04e8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga06fad8ae17b680f6dddfd798c9d3b30d">dspi_shift_direction_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aafbec5b2cc4cdec420381f29b32a04e8">direction</a></td></tr>
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<tr class="memdesc:aafbec5b2cc4cdec420381f29b32a04e8"><td class="mdescLeft"> </td><td class="mdescRight">MSB or LSB data shift direction. <a href="#aafbec5b2cc4cdec420381f29b32a04e8">More...</a><br/></td></tr>
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<tr class="memitem:a32c83fc580640a66049071dd9b672a1a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a32c83fc580640a66049071dd9b672a1a">pcsToSckDelayInNanoSec</a></td></tr>
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<tr class="memdesc:a32c83fc580640a66049071dd9b672a1a"><td class="mdescLeft"> </td><td class="mdescRight">PCS to SCK delay time with nanosecond , set to 0 sets the minimum delay. <a href="#a32c83fc580640a66049071dd9b672a1a">More...</a><br/></td></tr>
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<tr class="memitem:af6e22013a735cf762e671973afbed487"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#af6e22013a735cf762e671973afbed487">lastSckToPcsDelayInNanoSec</a></td></tr>
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<tr class="memdesc:af6e22013a735cf762e671973afbed487"><td class="mdescLeft"> </td><td class="mdescRight">Last SCK to PCS delay time with nanosecond , set to 0 sets the minimum delay.It sets the boundary value if out of range that can be set. <a href="#af6e22013a735cf762e671973afbed487">More...</a><br/></td></tr>
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<tr class="memitem:a8d900155157617487c5089a91c41c638"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a8d900155157617487c5089a91c41c638">betweenTransferDelayInNanoSec</a></td></tr>
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<tr class="memdesc:a8d900155157617487c5089a91c41c638"><td class="mdescLeft"> </td><td class="mdescRight"><pre class="fragment">After SCK delay time with nanosecond , set to 0 sets the minimum
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</pre><p> delay.It sets the boundary value if out of range that can be set. <a href="#a8d900155157617487c5089a91c41c638">More...</a><br/></td></tr>
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<h4 class="groupheader">Field Documentation</h4>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga1e0a9074742794ef89f597d220296651">dspi_clock_polarity_t</a> dspi_master_ctar_config_t::cpol</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga4269ec144334dd60666a92e6fd2c1476">dspi_clock_phase_t</a> dspi_master_ctar_config_t::cpha</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga06fad8ae17b680f6dddfd798c9d3b30d">dspi_shift_direction_t</a> dspi_master_ctar_config_t::direction</td>
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<td class="memname">uint32_t dspi_master_ctar_config_t::pcsToSckDelayInNanoSec</td>
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<p>It sets the boundary value if out of range that can be set. </p>
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<a name="structdspi__master__config__t" id="structdspi__master__config__t"></a>
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<td class="memname">struct dspi_master_config_t</td>
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:a822cafb9ccbaac368bdd456f004dd7f1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a822cafb9ccbaac368bdd456f004dd7f1">whichCtar</a></td></tr>
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<tr class="memdesc:a822cafb9ccbaac368bdd456f004dd7f1"><td class="mdescLeft"> </td><td class="mdescRight">Desired CTAR to use. <a href="#a822cafb9ccbaac368bdd456f004dd7f1">More...</a><br/></td></tr>
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<tr class="memitem:a31ffb9db13f0b3b9ac1cd6272674047b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#structdspi__master__ctar__config__t">dspi_master_ctar_config_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a></td></tr>
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<tr class="memdesc:a31ffb9db13f0b3b9ac1cd6272674047b"><td class="mdescLeft"> </td><td class="mdescRight">Set the ctarConfig to the desired CTAR. <a href="#a31ffb9db13f0b3b9ac1cd6272674047b">More...</a><br/></td></tr>
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<tr class="memitem:a01111111bd757122f7874576e3b859e7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga36d77cff6cfa202e0ff3a05ab4c2a632">dspi_which_pcs_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a01111111bd757122f7874576e3b859e7">whichPcs</a></td></tr>
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<tr class="memdesc:a01111111bd757122f7874576e3b859e7"><td class="mdescLeft"> </td><td class="mdescRight">Desired Peripheral Chip Select (pcs). <a href="#a01111111bd757122f7874576e3b859e7">More...</a><br/></td></tr>
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<tr class="memitem:a70b19520cae538f1860d355bacc4abca"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#gab466e73cb54b2c023459d43918c4197d">dspi_pcs_polarity_config_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a70b19520cae538f1860d355bacc4abca">pcsActiveHighOrLow</a></td></tr>
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<tr class="memdesc:a70b19520cae538f1860d355bacc4abca"><td class="mdescLeft"> </td><td class="mdescRight">Desired PCS active high or low. <a href="#a70b19520cae538f1860d355bacc4abca">More...</a><br/></td></tr>
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<tr class="memitem:a9fd922242d41c151599c4906c4d8d7f2"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a9fd922242d41c151599c4906c4d8d7f2">enableContinuousSCK</a></td></tr>
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<tr class="memdesc:a9fd922242d41c151599c4906c4d8d7f2"><td class="mdescLeft"> </td><td class="mdescRight">CONT_SCKE, continuous SCK enable . <a href="#a9fd922242d41c151599c4906c4d8d7f2">More...</a><br/></td></tr>
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<tr class="memitem:aa9a8bb9487711b83566ae0e04b386905"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aa9a8bb9487711b83566ae0e04b386905">enableRxFifoOverWrite</a></td></tr>
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<tr class="memdesc:aa9a8bb9487711b83566ae0e04b386905"><td class="mdescLeft"> </td><td class="mdescRight">ROOE, Receive FIFO overflow overwrite enable. <a href="#aa9a8bb9487711b83566ae0e04b386905">More...</a><br/></td></tr>
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<tr class="memitem:a86656569461eb376c1a7db424efb8916"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a86656569461eb376c1a7db424efb8916">enableModifiedTimingFormat</a></td></tr>
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<tr class="memdesc:a86656569461eb376c1a7db424efb8916"><td class="mdescLeft"> </td><td class="mdescRight">Enables a modified transfer format to be used if it's true. <a href="#a86656569461eb376c1a7db424efb8916">More...</a><br/></td></tr>
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<tr class="memitem:a1827b5d3bf3ff28b7ce940bbae1a6d35"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#gae783895e2917abe07adbe27a253510a2">dspi_master_sample_point_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a1827b5d3bf3ff28b7ce940bbae1a6d35">samplePoint</a></td></tr>
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<tr class="memdesc:a1827b5d3bf3ff28b7ce940bbae1a6d35"><td class="mdescLeft"> </td><td class="mdescRight">Controls when the module master samples SIN in Modified Transfer Format. <a href="#a1827b5d3bf3ff28b7ce940bbae1a6d35">More...</a><br/></td></tr>
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<h4 class="groupheader">Field Documentation</h4>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> dspi_master_config_t::whichCtar</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#structdspi__master__ctar__config__t">dspi_master_ctar_config_t</a> dspi_master_config_t::ctarConfig</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga36d77cff6cfa202e0ff3a05ab4c2a632">dspi_which_pcs_t</a> dspi_master_config_t::whichPcs</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#gab466e73cb54b2c023459d43918c4197d">dspi_pcs_polarity_config_t</a> dspi_master_config_t::pcsActiveHighOrLow</td>
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<td class="memname">bool dspi_master_config_t::enableContinuousSCK</td>
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<p>Note that continuous SCK is only supported for CPHA = 1. </p>
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<td class="memname">bool dspi_master_config_t::enableRxFifoOverWrite</td>
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<p>ROOE = 0, the incoming data is ignored, the data from the transfer that generated the overflow is either ignored. ROOE = 1, the incoming data is shifted in to the shift to the shift register. </p>
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<td class="memname">bool dspi_master_config_t::enableModifiedTimingFormat</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#gae783895e2917abe07adbe27a253510a2">dspi_master_sample_point_t</a> dspi_master_config_t::samplePoint</td>
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<p>It's valid only when CPHA=0. </p>
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<a name="structdspi__slave__ctar__config__t" id="structdspi__slave__ctar__config__t"></a>
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<td class="memname">struct dspi_slave_ctar_config_t</td>
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:a3ddbe384d7b4c256ced99ea6671ed73d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a3ddbe384d7b4c256ced99ea6671ed73d">bitsPerFrame</a></td></tr>
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<tr class="memdesc:a3ddbe384d7b4c256ced99ea6671ed73d"><td class="mdescLeft"> </td><td class="mdescRight">Bits per frame, minimum 4, maximum 16. <a href="#a3ddbe384d7b4c256ced99ea6671ed73d">More...</a><br/></td></tr>
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<tr class="separator:a3ddbe384d7b4c256ced99ea6671ed73d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc3449874392a507f8ca15263119001e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga1e0a9074742794ef89f597d220296651">dspi_clock_polarity_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#abc3449874392a507f8ca15263119001e">cpol</a></td></tr>
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<tr class="memdesc:abc3449874392a507f8ca15263119001e"><td class="mdescLeft"> </td><td class="mdescRight">Clock polarity. <a href="#abc3449874392a507f8ca15263119001e">More...</a><br/></td></tr>
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<tr class="separator:abc3449874392a507f8ca15263119001e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a80127ee24970efe8ea1c8760bb647ce5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga4269ec144334dd60666a92e6fd2c1476">dspi_clock_phase_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a80127ee24970efe8ea1c8760bb647ce5">cpha</a></td></tr>
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<tr class="memdesc:a80127ee24970efe8ea1c8760bb647ce5"><td class="mdescLeft"> </td><td class="mdescRight">Clock phase. <a href="#a80127ee24970efe8ea1c8760bb647ce5">More...</a><br/></td></tr>
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<h4 class="groupheader">Field Documentation</h4>
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<a class="anchor" id="a3ddbe384d7b4c256ced99ea6671ed73d"></a>
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<td class="memname">uint32_t dspi_slave_ctar_config_t::bitsPerFrame</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga1e0a9074742794ef89f597d220296651">dspi_clock_polarity_t</a> dspi_slave_ctar_config_t::cpol</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga4269ec144334dd60666a92e6fd2c1476">dspi_clock_phase_t</a> dspi_slave_ctar_config_t::cpha</td>
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<p>Slave only supports MSB , does not support LSB. </p>
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<a name="structdspi__slave__config__t" id="structdspi__slave__config__t"></a>
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<td class="memname">struct dspi_slave_config_t</td>
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:a7b488cbe0d44e605c74341b241aba6e8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a7b488cbe0d44e605c74341b241aba6e8">whichCtar</a></td></tr>
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<tr class="memdesc:a7b488cbe0d44e605c74341b241aba6e8"><td class="mdescLeft"> </td><td class="mdescRight">Desired CTAR to use. <a href="#a7b488cbe0d44e605c74341b241aba6e8">More...</a><br/></td></tr>
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<tr class="separator:a7b488cbe0d44e605c74341b241aba6e8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa69a2a4dab7a6e026ee1e568418b18f7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#structdspi__slave__ctar__config__t">dspi_slave_ctar_config_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aa69a2a4dab7a6e026ee1e568418b18f7">ctarConfig</a></td></tr>
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<tr class="memdesc:aa69a2a4dab7a6e026ee1e568418b18f7"><td class="mdescLeft"> </td><td class="mdescRight">Set the ctarConfig to the desired CTAR. <a href="#aa69a2a4dab7a6e026ee1e568418b18f7">More...</a><br/></td></tr>
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<tr class="separator:aa69a2a4dab7a6e026ee1e568418b18f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abd2c9b108ae18e0abd71fbb457d17d70"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#abd2c9b108ae18e0abd71fbb457d17d70">enableContinuousSCK</a></td></tr>
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<tr class="memdesc:abd2c9b108ae18e0abd71fbb457d17d70"><td class="mdescLeft"> </td><td class="mdescRight">CONT_SCKE, continuous SCK enable. <a href="#abd2c9b108ae18e0abd71fbb457d17d70">More...</a><br/></td></tr>
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<tr class="separator:abd2c9b108ae18e0abd71fbb457d17d70"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad1db8c46797dbc50d5a3b2a915b8ce58"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ad1db8c46797dbc50d5a3b2a915b8ce58">enableRxFifoOverWrite</a></td></tr>
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<tr class="memdesc:ad1db8c46797dbc50d5a3b2a915b8ce58"><td class="mdescLeft"> </td><td class="mdescRight">ROOE, Receive FIFO overflow overwrite enable. <a href="#ad1db8c46797dbc50d5a3b2a915b8ce58">More...</a><br/></td></tr>
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<tr class="separator:ad1db8c46797dbc50d5a3b2a915b8ce58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9a8cd1afddd8edca36c217d1f4e440ad"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a9a8cd1afddd8edca36c217d1f4e440ad">enableModifiedTimingFormat</a></td></tr>
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<tr class="memdesc:a9a8cd1afddd8edca36c217d1f4e440ad"><td class="mdescLeft"> </td><td class="mdescRight">Enables a modified transfer format to be used if it's true. <a href="#a9a8cd1afddd8edca36c217d1f4e440ad">More...</a><br/></td></tr>
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<tr class="separator:a9a8cd1afddd8edca36c217d1f4e440ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7771f990c0f85360232e144cb0f467f2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#gae783895e2917abe07adbe27a253510a2">dspi_master_sample_point_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a7771f990c0f85360232e144cb0f467f2">samplePoint</a></td></tr>
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<tr class="memdesc:a7771f990c0f85360232e144cb0f467f2"><td class="mdescLeft"> </td><td class="mdescRight">Controls when the module master samples SIN in Modified Transfer Format. <a href="#a7771f990c0f85360232e144cb0f467f2">More...</a><br/></td></tr>
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<h4 class="groupheader">Field Documentation</h4>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> dspi_slave_config_t::whichCtar</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#structdspi__slave__ctar__config__t">dspi_slave_ctar_config_t</a> dspi_slave_config_t::ctarConfig</td>
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<td class="memname">bool dspi_slave_config_t::enableContinuousSCK</td>
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<p>Note that continuous SCK is only supported for CPHA = 1. </p>
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<td class="memname">bool dspi_slave_config_t::enableRxFifoOverWrite</td>
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<p>ROOE = 0, the incoming data is ignored, the data from the transfer that generated the overflow is either ignored. ROOE = 1, the incoming data is shifted in to the shift to the shift register. </p>
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<td class="memname">bool dspi_slave_config_t::enableModifiedTimingFormat</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#gae783895e2917abe07adbe27a253510a2">dspi_master_sample_point_t</a> dspi_slave_config_t::samplePoint</td>
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<p>It's valid only when CPHA=0. </p>
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<a name="structdspi__transfer__t" id="structdspi__transfer__t"></a>
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<td class="memname">struct dspi_transfer_t</td>
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:a90810cbdeac26cc69fef68d1b964ef12"><td class="memItemLeft" align="right" valign="top">uint8_t * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a90810cbdeac26cc69fef68d1b964ef12">txData</a></td></tr>
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<tr class="memdesc:a90810cbdeac26cc69fef68d1b964ef12"><td class="mdescLeft"> </td><td class="mdescRight">Send buffer. <a href="#a90810cbdeac26cc69fef68d1b964ef12">More...</a><br/></td></tr>
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<tr class="separator:a90810cbdeac26cc69fef68d1b964ef12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac922665b229d98d1bf2123eaa33d1457"><td class="memItemLeft" align="right" valign="top">uint8_t * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ac922665b229d98d1bf2123eaa33d1457">rxData</a></td></tr>
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<tr class="memdesc:ac922665b229d98d1bf2123eaa33d1457"><td class="mdescLeft"> </td><td class="mdescRight">Receive buffer. <a href="#ac922665b229d98d1bf2123eaa33d1457">More...</a><br/></td></tr>
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<tr class="memitem:a9e9f9810b6206130faa670b41a5f0f47"><td class="memItemLeft" align="right" valign="top">volatile size_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a9e9f9810b6206130faa670b41a5f0f47">dataSize</a></td></tr>
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<tr class="memdesc:a9e9f9810b6206130faa670b41a5f0f47"><td class="mdescLeft"> </td><td class="mdescRight">Transfer bytes. <a href="#a9e9f9810b6206130faa670b41a5f0f47">More...</a><br/></td></tr>
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<tr class="separator:a9e9f9810b6206130faa670b41a5f0f47"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a15da053c55c0fe080aa6895a6deda4e2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a15da053c55c0fe080aa6895a6deda4e2">configFlags</a></td></tr>
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<tr class="memdesc:a15da053c55c0fe080aa6895a6deda4e2"><td class="mdescLeft"> </td><td class="mdescRight">Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave. <a href="#a15da053c55c0fe080aa6895a6deda4e2">More...</a><br/></td></tr>
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<tr class="separator:a15da053c55c0fe080aa6895a6deda4e2"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<h4 class="groupheader">Field Documentation</h4>
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<a class="anchor" id="a90810cbdeac26cc69fef68d1b964ef12"></a>
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<td class="memname">uint8_t* dspi_transfer_t::txData</td>
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</div><div class="memdoc">
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</div>
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<a class="anchor" id="ac922665b229d98d1bf2123eaa33d1457"></a>
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<td class="memname">uint8_t* dspi_transfer_t::rxData</td>
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</div><div class="memdoc">
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</div>
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<a class="anchor" id="a9e9f9810b6206130faa670b41a5f0f47"></a>
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<td class="memname">volatile size_t dspi_transfer_t::dataSize</td>
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</div><div class="memdoc">
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</div>
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<a class="anchor" id="a15da053c55c0fe080aa6895a6deda4e2"></a>
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<td class="memname">uint32_t dspi_transfer_t::configFlags</td>
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</div><div class="memdoc">
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</div>
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<a name="struct__dspi__master__handle" id="struct__dspi__master__handle"></a>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">struct _dspi_master_handle</td>
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</div><div class="memdoc">
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<div class="textblock"><p>Forward declaration of the <a class="el" href="group__dspi__driver.html#struct__dspi__master__handle" title="DSPI master transfer handle structure used for transactional API. ">_dspi_master_handle</a> typedefs.</p>
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</div><table class="memberdecls">
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:ae40ea7aebf40ae6a0ef39a2bc0c11979"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ae40ea7aebf40ae6a0ef39a2bc0c11979">bitsPerFrame</a></td></tr>
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<tr class="memdesc:ae40ea7aebf40ae6a0ef39a2bc0c11979"><td class="mdescLeft"> </td><td class="mdescRight">Desired number of bits per frame. <a href="#ae40ea7aebf40ae6a0ef39a2bc0c11979">More...</a><br/></td></tr>
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<tr class="separator:ae40ea7aebf40ae6a0ef39a2bc0c11979"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad1c69d203233d76b5952e475d053f84"><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aad1c69d203233d76b5952e475d053f84">command</a></td></tr>
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<tr class="memdesc:aad1c69d203233d76b5952e475d053f84"><td class="mdescLeft"> </td><td class="mdescRight">Desired data command. <a href="#aad1c69d203233d76b5952e475d053f84">More...</a><br/></td></tr>
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<tr class="separator:aad1c69d203233d76b5952e475d053f84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a606dff7a7dd4d18f4be97656f0102d59"><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a606dff7a7dd4d18f4be97656f0102d59">lastCommand</a></td></tr>
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<tr class="memdesc:a606dff7a7dd4d18f4be97656f0102d59"><td class="mdescLeft"> </td><td class="mdescRight">Desired last data command. <a href="#a606dff7a7dd4d18f4be97656f0102d59">More...</a><br/></td></tr>
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<tr class="separator:a606dff7a7dd4d18f4be97656f0102d59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9ba5d93da2d5aeb52da12560ee919c23"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a9ba5d93da2d5aeb52da12560ee919c23">fifoSize</a></td></tr>
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<tr class="memdesc:a9ba5d93da2d5aeb52da12560ee919c23"><td class="mdescLeft"> </td><td class="mdescRight">FIFO dataSize. <a href="#a9ba5d93da2d5aeb52da12560ee919c23">More...</a><br/></td></tr>
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<tr class="separator:a9ba5d93da2d5aeb52da12560ee919c23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa9da46d9cb79356658db575799d5bc83"><td class="memItemLeft" align="right" valign="top">volatile bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aa9da46d9cb79356658db575799d5bc83">isPcsActiveAfterTransfer</a></td></tr>
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<tr class="memdesc:aa9da46d9cb79356658db575799d5bc83"><td class="mdescLeft"> </td><td class="mdescRight">Is PCS signal keep active after the last frame transfer. <a href="#aa9da46d9cb79356658db575799d5bc83">More...</a><br/></td></tr>
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<tr class="separator:aa9da46d9cb79356658db575799d5bc83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa486cbc9a515a7eab48bffc835cbcd00"><td class="memItemLeft" align="right" valign="top">volatile bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aa486cbc9a515a7eab48bffc835cbcd00">isThereExtraByte</a></td></tr>
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<tr class="memdesc:aa486cbc9a515a7eab48bffc835cbcd00"><td class="mdescLeft"> </td><td class="mdescRight">Is there extra byte. <a href="#aa486cbc9a515a7eab48bffc835cbcd00">More...</a><br/></td></tr>
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<tr class="separator:aa486cbc9a515a7eab48bffc835cbcd00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaaa4534d6baf59254e805b08f1bf7dad"><td class="memItemLeft" align="right" valign="top">uint8_t *volatile </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#aaaa4534d6baf59254e805b08f1bf7dad">txData</a></td></tr>
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<tr class="memdesc:aaaa4534d6baf59254e805b08f1bf7dad"><td class="mdescLeft"> </td><td class="mdescRight">Send buffer. <a href="#aaaa4534d6baf59254e805b08f1bf7dad">More...</a><br/></td></tr>
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<tr class="separator:aaaa4534d6baf59254e805b08f1bf7dad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a40f937c1bd502db19cc9e8ed2eda0949"><td class="memItemLeft" align="right" valign="top">uint8_t *volatile </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a40f937c1bd502db19cc9e8ed2eda0949">rxData</a></td></tr>
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<tr class="memdesc:a40f937c1bd502db19cc9e8ed2eda0949"><td class="mdescLeft"> </td><td class="mdescRight">Receive buffer. <a href="#a40f937c1bd502db19cc9e8ed2eda0949">More...</a><br/></td></tr>
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<tr class="separator:a40f937c1bd502db19cc9e8ed2eda0949"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d2239362d3da9fca02747c04209e004"><td class="memItemLeft" align="right" valign="top">volatile size_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a8d2239362d3da9fca02747c04209e004">remainingSendByteCount</a></td></tr>
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<tr class="memdesc:a8d2239362d3da9fca02747c04209e004"><td class="mdescLeft"> </td><td class="mdescRight">Number of bytes remaining to send. <a href="#a8d2239362d3da9fca02747c04209e004">More...</a><br/></td></tr>
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<tr class="separator:a8d2239362d3da9fca02747c04209e004"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b874ce3772b6d421a2c987032d47852"><td class="memItemLeft" align="right" valign="top">volatile size_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a0b874ce3772b6d421a2c987032d47852">remainingReceiveByteCount</a></td></tr>
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<tr class="memdesc:a0b874ce3772b6d421a2c987032d47852"><td class="mdescLeft"> </td><td class="mdescRight">Number of bytes remaining to receive. <a href="#a0b874ce3772b6d421a2c987032d47852">More...</a><br/></td></tr>
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<tr class="separator:a0b874ce3772b6d421a2c987032d47852"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e7587734f97a75b1eed4d790abfa596"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4e7587734f97a75b1eed4d790abfa596"></a>
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size_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a4e7587734f97a75b1eed4d790abfa596">totalByteCount</a></td></tr>
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<tr class="memdesc:a4e7587734f97a75b1eed4d790abfa596"><td class="mdescLeft"> </td><td class="mdescRight">Number of transfer bytes. <br/></td></tr>
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<tr class="separator:a4e7587734f97a75b1eed4d790abfa596"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a782ff1c918a8aa3491bf29aa6d9a1027"><td class="memItemLeft" align="right" valign="top">volatile uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a782ff1c918a8aa3491bf29aa6d9a1027">state</a></td></tr>
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<tr class="memdesc:a782ff1c918a8aa3491bf29aa6d9a1027"><td class="mdescLeft"> </td><td class="mdescRight">DSPI transfer state , _dspi_transfer_state. <a href="#a782ff1c918a8aa3491bf29aa6d9a1027">More...</a><br/></td></tr>
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<tr class="separator:a782ff1c918a8aa3491bf29aa6d9a1027"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab08248997b9c6250932742abd64d842f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#gad191922bda6ac07f95f241a67eb52f48">dspi_master_transfer_callback_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ab08248997b9c6250932742abd64d842f">callback</a></td></tr>
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<tr class="memdesc:ab08248997b9c6250932742abd64d842f"><td class="mdescLeft"> </td><td class="mdescRight">Completion callback. <a href="#ab08248997b9c6250932742abd64d842f">More...</a><br/></td></tr>
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<tr class="separator:ab08248997b9c6250932742abd64d842f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab603f42c0b22ed2cad93bd176fdd863c"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ab603f42c0b22ed2cad93bd176fdd863c">userData</a></td></tr>
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<tr class="memdesc:ab603f42c0b22ed2cad93bd176fdd863c"><td class="mdescLeft"> </td><td class="mdescRight">Callback user data. <a href="#ab603f42c0b22ed2cad93bd176fdd863c">More...</a><br/></td></tr>
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<tr class="separator:ab603f42c0b22ed2cad93bd176fdd863c"><td class="memSeparator" colspan="2"> </td></tr>
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<h4 class="groupheader">Field Documentation</h4>
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<a class="anchor" id="ae40ea7aebf40ae6a0ef39a2bc0c11979"></a>
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<td class="memname">uint32_t dspi_master_handle_t::bitsPerFrame</td>
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<td class="memname">volatile uint32_t dspi_master_handle_t::command</td>
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<td class="memname">volatile uint32_t dspi_master_handle_t::lastCommand</td>
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<td class="memname">uint8_t dspi_master_handle_t::fifoSize</td>
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<a class="anchor" id="aa9da46d9cb79356658db575799d5bc83"></a>
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<td class="memname">volatile bool dspi_master_handle_t::isPcsActiveAfterTransfer</td>
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<td class="memname">volatile bool dspi_master_handle_t::isThereExtraByte</td>
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<td class="memname">uint8_t* volatile dspi_master_handle_t::txData</td>
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<td class="memname">uint8_t* volatile dspi_master_handle_t::rxData</td>
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<td class="memname">volatile size_t dspi_master_handle_t::remainingSendByteCount</td>
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<td class="memname">volatile size_t dspi_master_handle_t::remainingReceiveByteCount</td>
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<td class="memname">volatile uint8_t dspi_master_handle_t::state</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#gad191922bda6ac07f95f241a67eb52f48">dspi_master_transfer_callback_t</a> dspi_master_handle_t::callback</td>
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<a class="anchor" id="ab603f42c0b22ed2cad93bd176fdd863c"></a>
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<td class="memname">void* dspi_master_handle_t::userData</td>
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<a name="struct__dspi__slave__handle" id="struct__dspi__slave__handle"></a>
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<td class="memname">struct _dspi_slave_handle</td>
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</table>
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<div class="textblock"><p>Forward declaration of the <a class="el" href="group__dspi__driver.html#struct__dspi__slave__handle" title="DSPI slave transfer handle structure used for transactional API. ">_dspi_slave_handle</a> typedefs.</p>
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:af17a0af7a2f6dfa4483302425ee26284"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#af17a0af7a2f6dfa4483302425ee26284">bitsPerFrame</a></td></tr>
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<tr class="memdesc:af17a0af7a2f6dfa4483302425ee26284"><td class="mdescLeft"> </td><td class="mdescRight">Desired number of bits per frame. <a href="#af17a0af7a2f6dfa4483302425ee26284">More...</a><br/></td></tr>
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<tr class="separator:af17a0af7a2f6dfa4483302425ee26284"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a066e7025eeeb49fc66390eb62efbd935"><td class="memItemLeft" align="right" valign="top">volatile bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a066e7025eeeb49fc66390eb62efbd935">isThereExtraByte</a></td></tr>
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<tr class="memdesc:a066e7025eeeb49fc66390eb62efbd935"><td class="mdescLeft"> </td><td class="mdescRight">Is there extra byte. <a href="#a066e7025eeeb49fc66390eb62efbd935">More...</a><br/></td></tr>
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<tr class="separator:a066e7025eeeb49fc66390eb62efbd935"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a043d3f013f1a34161036b90549c55546"><td class="memItemLeft" align="right" valign="top">uint8_t *volatile </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a043d3f013f1a34161036b90549c55546">txData</a></td></tr>
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<tr class="memdesc:a043d3f013f1a34161036b90549c55546"><td class="mdescLeft"> </td><td class="mdescRight">Send buffer. <a href="#a043d3f013f1a34161036b90549c55546">More...</a><br/></td></tr>
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<tr class="separator:a043d3f013f1a34161036b90549c55546"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab51f36fcc1194017f0890f002d45e85f"><td class="memItemLeft" align="right" valign="top">uint8_t *volatile </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#ab51f36fcc1194017f0890f002d45e85f">rxData</a></td></tr>
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<tr class="memdesc:ab51f36fcc1194017f0890f002d45e85f"><td class="mdescLeft"> </td><td class="mdescRight">Receive buffer. <a href="#ab51f36fcc1194017f0890f002d45e85f">More...</a><br/></td></tr>
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<tr class="separator:ab51f36fcc1194017f0890f002d45e85f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4cf577cf53d51d5341b5abeb036116fa"><td class="memItemLeft" align="right" valign="top">volatile size_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a4cf577cf53d51d5341b5abeb036116fa">remainingSendByteCount</a></td></tr>
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<tr class="memdesc:a4cf577cf53d51d5341b5abeb036116fa"><td class="mdescLeft"> </td><td class="mdescRight">Number of bytes remaining to send. <a href="#a4cf577cf53d51d5341b5abeb036116fa">More...</a><br/></td></tr>
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<tr class="separator:a4cf577cf53d51d5341b5abeb036116fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2cb76e44a835d9df89e523646e33282f"><td class="memItemLeft" align="right" valign="top">volatile size_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a2cb76e44a835d9df89e523646e33282f">remainingReceiveByteCount</a></td></tr>
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<tr class="memdesc:a2cb76e44a835d9df89e523646e33282f"><td class="mdescLeft"> </td><td class="mdescRight">Number of bytes remaining to receive. <a href="#a2cb76e44a835d9df89e523646e33282f">More...</a><br/></td></tr>
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<tr class="separator:a2cb76e44a835d9df89e523646e33282f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a432ae812101804ba12e00f7e557f895f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a432ae812101804ba12e00f7e557f895f"></a>
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size_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a432ae812101804ba12e00f7e557f895f">totalByteCount</a></td></tr>
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<tr class="memdesc:a432ae812101804ba12e00f7e557f895f"><td class="mdescLeft"> </td><td class="mdescRight">Number of transfer bytes. <br/></td></tr>
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<tr class="separator:a432ae812101804ba12e00f7e557f895f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a003e7d2ad9226e5459b7534e6fea7355"><td class="memItemLeft" align="right" valign="top">volatile uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a003e7d2ad9226e5459b7534e6fea7355">state</a></td></tr>
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<tr class="memdesc:a003e7d2ad9226e5459b7534e6fea7355"><td class="mdescLeft"> </td><td class="mdescRight">DSPI transfer state. <a href="#a003e7d2ad9226e5459b7534e6fea7355">More...</a><br/></td></tr>
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<tr class="separator:a003e7d2ad9226e5459b7534e6fea7355"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af76902a142c73721cd36a477771855b5"><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#af76902a142c73721cd36a477771855b5">errorCount</a></td></tr>
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<tr class="memdesc:af76902a142c73721cd36a477771855b5"><td class="mdescLeft"> </td><td class="mdescRight">Error count for slave transfer. <a href="#af76902a142c73721cd36a477771855b5">More...</a><br/></td></tr>
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<tr class="separator:af76902a142c73721cd36a477771855b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af72dca24f829b41eef262acf362f9f93"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__dspi__driver.html#ga0c9ef1b6a6d8034b5e47b8310f2d52dc">dspi_slave_transfer_callback_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#af72dca24f829b41eef262acf362f9f93">callback</a></td></tr>
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<tr class="memdesc:af72dca24f829b41eef262acf362f9f93"><td class="mdescLeft"> </td><td class="mdescRight">Completion callback. <a href="#af72dca24f829b41eef262acf362f9f93">More...</a><br/></td></tr>
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<tr class="separator:af72dca24f829b41eef262acf362f9f93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39ee6975cb1628b49b045227a6bf1710"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__dspi__driver.html#a39ee6975cb1628b49b045227a6bf1710">userData</a></td></tr>
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<tr class="memdesc:a39ee6975cb1628b49b045227a6bf1710"><td class="mdescLeft"> </td><td class="mdescRight">Callback user data. <a href="#a39ee6975cb1628b49b045227a6bf1710">More...</a><br/></td></tr>
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<tr class="separator:a39ee6975cb1628b49b045227a6bf1710"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<h4 class="groupheader">Field Documentation</h4>
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<a class="anchor" id="af17a0af7a2f6dfa4483302425ee26284"></a>
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<td class="memname">uint32_t dspi_slave_handle_t::bitsPerFrame</td>
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</div><div class="memdoc">
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<a class="anchor" id="a066e7025eeeb49fc66390eb62efbd935"></a>
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<td class="memname">volatile bool dspi_slave_handle_t::isThereExtraByte</td>
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</div><div class="memdoc">
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<td class="memname">uint8_t* volatile dspi_slave_handle_t::txData</td>
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</div><div class="memdoc">
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<td class="memname">uint8_t* volatile dspi_slave_handle_t::rxData</td>
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</div><div class="memdoc">
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<a class="anchor" id="a4cf577cf53d51d5341b5abeb036116fa"></a>
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<td class="memname">volatile size_t dspi_slave_handle_t::remainingSendByteCount</td>
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</div><div class="memdoc">
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</div>
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<a class="anchor" id="a2cb76e44a835d9df89e523646e33282f"></a>
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<td class="memname">volatile size_t dspi_slave_handle_t::remainingReceiveByteCount</td>
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<a class="anchor" id="a003e7d2ad9226e5459b7534e6fea7355"></a>
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<td class="memname">volatile uint8_t dspi_slave_handle_t::state</td>
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</div><div class="memdoc">
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<a class="anchor" id="af76902a142c73721cd36a477771855b5"></a>
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<td class="memname">volatile uint32_t dspi_slave_handle_t::errorCount</td>
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<td class="memname"><a class="el" href="group__dspi__driver.html#ga0c9ef1b6a6d8034b5e47b8310f2d52dc">dspi_slave_transfer_callback_t</a> dspi_slave_handle_t::callback</td>
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</div><div class="memdoc">
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<td class="memname">void* dspi_slave_handle_t::userData</td>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<a class="anchor" id="ga9ed59b934c560c5d88000b17b8171a01"></a>
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<td class="memname">#define FSL_DSPI_DRIVER_VERSION   (<a class="el" href="group__flash__driver.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 1, 1))</td>
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</table>
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</div><div class="memdoc">
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<a class="anchor" id="gae3af6268fdc846d553d23c82fd8c8668"></a>
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<td class="memname">#define DSPI_DUMMY_DATA   (0x00U)</td>
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<p>Dummy data used for tx if there is not txData. </p>
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<td class="memname">#define DSPI_MASTER_CTAR_SHIFT   (0U)</td>
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<td class="memname">#define DSPI_MASTER_CTAR_MASK   (0x0FU)</td>
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<td class="memname">#define DSPI_MASTER_PCS_SHIFT   (4U)</td>
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<td class="memname">#define DSPI_MASTER_PCS_MASK   (0xF0U)</td>
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<td class="memname">#define DSPI_SLAVE_CTAR_SHIFT   (0U)</td>
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<td class="memname">#define DSPI_SLAVE_CTAR_MASK   (0x07U)</td>
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<h2 class="groupheader">Typedef Documentation</h2>
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<td class="memname">typedef void(* dspi_master_transfer_callback_t)(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">handle</td><td>Pointer to the handle for the DSPI master. </td></tr>
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<tr><td class="paramname">status</td><td>Success or error code describing whether the transfer completed. </td></tr>
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<tr><td class="paramname">userData</td><td>Arbitrary pointer-dataSized value passed from the application. </td></tr>
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</dl>
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<td class="memname">typedef void(* dspi_slave_transfer_callback_t)(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">handle</td><td>Pointer to the handle for the DSPI slave. </td></tr>
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<tr><td class="paramname">status</td><td>Success or error code describing whether the transfer completed. </td></tr>
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<tr><td class="paramname">userData</td><td>Arbitrary pointer-dataSized value passed from the application. </td></tr>
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</dd>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga06b41ab984bc03e6f1eb07988edcb3ea">_dspi_status</a></td>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga06b41ab984bc03e6f1eb07988edcb3eaad5ecc8346da4119b8609c6bcb4c57e40"></a>kStatus_DSPI_Busy</em> </td><td class="fielddoc">
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<p>DSPI transfer is busy. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga06b41ab984bc03e6f1eb07988edcb3eaaaae2ba17a6a622142816b0ffec7b9f7a"></a>kStatus_DSPI_Error</em> </td><td class="fielddoc">
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<p>DSPI driver error. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga06b41ab984bc03e6f1eb07988edcb3eaa638dc0d050e7660225a46cc7cd6e38c7"></a>kStatus_DSPI_Idle</em> </td><td class="fielddoc">
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<p>DSPI is idle. </p>
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</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga06b41ab984bc03e6f1eb07988edcb3eaac1713712f0410e28da008d714734a6bd"></a>kStatus_DSPI_OutOfRange</em> </td><td class="fielddoc">
|
|
<p>DSPI transfer out Of range. </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="ga2bfefaf6ba65ba464e764d1c918c904f"></a>
|
|
<div class="memitem">
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<div class="memproto">
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<table class="memname">
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|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga2bfefaf6ba65ba464e764d1c918c904f">_dspi_flags</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga2bfefaf6ba65ba464e764d1c918c904faffc8e8711d9083470cddb0db647b75b0"></a>kDSPI_TxCompleteFlag</em> </td><td class="fielddoc">
|
|
<p>Transfer Complete Flag. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga2bfefaf6ba65ba464e764d1c918c904fae91c7a5cc2a90fa051c89f13bbb6d8ed"></a>kDSPI_EndOfQueueFlag</em> </td><td class="fielddoc">
|
|
<p>End of Queue Flag. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga2bfefaf6ba65ba464e764d1c918c904fae36215137d8ce7cf215349199db877b7"></a>kDSPI_TxFifoUnderflowFlag</em> </td><td class="fielddoc">
|
|
<p>Transmit FIFO Underflow Flag. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga2bfefaf6ba65ba464e764d1c918c904fae9704d53b57758969f8ea5ea6c86f7f0"></a>kDSPI_TxFifoFillRequestFlag</em> </td><td class="fielddoc">
|
|
<p>Transmit FIFO Fill Flag. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga2bfefaf6ba65ba464e764d1c918c904fa30f039adca01f89dbbd02f70dff725ee"></a>kDSPI_RxFifoOverflowFlag</em> </td><td class="fielddoc">
|
|
<p>Receive FIFO Overflow Flag. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga2bfefaf6ba65ba464e764d1c918c904fa092b7f39357ce8cb82ec825e93536605"></a>kDSPI_RxFifoDrainRequestFlag</em> </td><td class="fielddoc">
|
|
<p>Receive FIFO Drain Flag. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga2bfefaf6ba65ba464e764d1c918c904fa58771b3977aef221dab6a67a6739f8d6"></a>kDSPI_TxAndRxStatusFlag</em> </td><td class="fielddoc">
|
|
<p>The module is in Stopped/Running state. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga2bfefaf6ba65ba464e764d1c918c904fa4a742818251256d8fc35ab63a6af9c9e"></a>kDSPI_AllStatusFlag</em> </td><td class="fielddoc">
|
|
<p>All status above. </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="gaeb57298690a2f1a09d94d696c893c4b2"></a>
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|
<div class="memitem">
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<div class="memproto">
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<table class="memname">
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|
<tr>
|
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<td class="memname">enum <a class="el" href="group__dspi__driver.html#gaeb57298690a2f1a09d94d696c893c4b2">_dspi_interrupt_enable</a></td>
|
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</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggaeb57298690a2f1a09d94d696c893c4b2ab2b1ba228fd75de23a2de7e56c1ee438"></a>kDSPI_TxCompleteInterruptEnable</em> </td><td class="fielddoc">
|
|
<p>TCF interrupt enable. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggaeb57298690a2f1a09d94d696c893c4b2a069483b28469fcbfa5890b04cd6439b3"></a>kDSPI_EndOfQueueInterruptEnable</em> </td><td class="fielddoc">
|
|
<p>EOQF interrupt enable. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggaeb57298690a2f1a09d94d696c893c4b2aa430e623e0bb240752381eaddda1a973"></a>kDSPI_TxFifoUnderflowInterruptEnable</em> </td><td class="fielddoc">
|
|
<p>TFUF interrupt enable. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggaeb57298690a2f1a09d94d696c893c4b2ada57830661d523d12e49892060fde201"></a>kDSPI_TxFifoFillRequestInterruptEnable</em> </td><td class="fielddoc">
|
|
<p>TFFF interrupt enable, DMA disable. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggaeb57298690a2f1a09d94d696c893c4b2a190746a0aeaa61db32c6c1a7b850d0ee"></a>kDSPI_RxFifoOverflowInterruptEnable</em> </td><td class="fielddoc">
|
|
<p>RFOF interrupt enable. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggaeb57298690a2f1a09d94d696c893c4b2aa7d99e6ac31bd6c7d835d89f36cec1a6"></a>kDSPI_RxFifoDrainRequestInterruptEnable</em> </td><td class="fielddoc">
|
|
<p>RFDF interrupt enable, DMA disable. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggaeb57298690a2f1a09d94d696c893c4b2a530d972d6cd16ab6e929d7ddaaf09b30"></a>kDSPI_AllInterruptEnable</em> </td><td class="fielddoc">
|
|
<p>All above interrupts enable. </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="gae3359796dc0680797b1f74b83fc0c0d9"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#gae3359796dc0680797b1f74b83fc0c0d9">_dspi_dma_enable</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggae3359796dc0680797b1f74b83fc0c0d9ae772dc49e5a28df00b817f9c6dab0749"></a>kDSPI_TxDmaEnable</em> </td><td class="fielddoc">
|
|
<p>TFFF flag generates DMA requests. </p>
|
|
<p>No Tx interrupt request. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggae3359796dc0680797b1f74b83fc0c0d9a15ec9c9897199d53a1b354ccce6d0445"></a>kDSPI_RxDmaEnable</em> </td><td class="fielddoc">
|
|
<p>RFDF flag generates DMA requests. </p>
|
|
<p>No Rx interrupt request. </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="gad7f974015f32db057dafada8b95641aa"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#gad7f974015f32db057dafada8b95641aa">dspi_master_slave_mode_t</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggad7f974015f32db057dafada8b95641aaa8330c6ad827da3c783df5805244fa7d9"></a>kDSPI_Master</em> </td><td class="fielddoc">
|
|
<p>DSPI peripheral operates in master mode. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggad7f974015f32db057dafada8b95641aaa2e075745386fd71bee2535606f29dd87"></a>kDSPI_Slave</em> </td><td class="fielddoc">
|
|
<p>DSPI peripheral operates in slave mode. </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="gae783895e2917abe07adbe27a253510a2"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#gae783895e2917abe07adbe27a253510a2">dspi_master_sample_point_t</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<p>This field is valid only when CPHA bit in CTAR register is 0. </p>
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggae783895e2917abe07adbe27a253510a2abbcf84bafbd94a63a9600647162b8d86"></a>kDSPI_SckToSin0Clock</em> </td><td class="fielddoc">
|
|
<p>0 system clocks between SCK edge and SIN sample. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggae783895e2917abe07adbe27a253510a2a61e5f5d7122c849c737513ae7c5c4c50"></a>kDSPI_SckToSin1Clock</em> </td><td class="fielddoc">
|
|
<p>1 system clock between SCK edge and SIN sample. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggae783895e2917abe07adbe27a253510a2a305d68c9446ca0866da7a2ace743ae4d"></a>kDSPI_SckToSin2Clock</em> </td><td class="fielddoc">
|
|
<p>2 system clocks between SCK edge and SIN sample. </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="ga36d77cff6cfa202e0ff3a05ab4c2a632"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga36d77cff6cfa202e0ff3a05ab4c2a632">dspi_which_pcs_t</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga36d77cff6cfa202e0ff3a05ab4c2a632a5c6297be9586ee874fa1a84a16d810b7"></a>kDSPI_Pcs0</em> </td><td class="fielddoc">
|
|
<p>Pcs[0]. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga36d77cff6cfa202e0ff3a05ab4c2a632a62d3c43292cebeed478a36bff2cd033a"></a>kDSPI_Pcs1</em> </td><td class="fielddoc">
|
|
<p>Pcs[1]. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga36d77cff6cfa202e0ff3a05ab4c2a632a625c90d5151e8458be6f89ace68f2fe2"></a>kDSPI_Pcs2</em> </td><td class="fielddoc">
|
|
<p>Pcs[2]. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga36d77cff6cfa202e0ff3a05ab4c2a632a7fae848c0f775a86562b90ecfd171cc8"></a>kDSPI_Pcs3</em> </td><td class="fielddoc">
|
|
<p>Pcs[3]. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga36d77cff6cfa202e0ff3a05ab4c2a632a0fd968cdbfd2e088987e309f49cb20f2"></a>kDSPI_Pcs4</em> </td><td class="fielddoc">
|
|
<p>Pcs[4]. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga36d77cff6cfa202e0ff3a05ab4c2a632a67653d39cbd675c9141bb014d4576a0b"></a>kDSPI_Pcs5</em> </td><td class="fielddoc">
|
|
<p>Pcs[5]. </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="gab466e73cb54b2c023459d43918c4197d"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#gab466e73cb54b2c023459d43918c4197d">dspi_pcs_polarity_config_t</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggab466e73cb54b2c023459d43918c4197da79a6807edd30a1230477ab26068060fd"></a>kDSPI_PcsActiveHigh</em> </td><td class="fielddoc">
|
|
<p>Pcs Active High (idles low). </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggab466e73cb54b2c023459d43918c4197daa678a5937bbb9975e3c014592c3d542c"></a>kDSPI_PcsActiveLow</em> </td><td class="fielddoc">
|
|
<p>Pcs Active Low (idles high). </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="gad23a66cefb04826de83504ad485f19a9"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#gad23a66cefb04826de83504ad485f19a9">_dspi_pcs_polarity</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggad23a66cefb04826de83504ad485f19a9ac731b21eefcc16342d2c606a12a00547"></a>kDSPI_Pcs0ActiveLow</em> </td><td class="fielddoc">
|
|
<p>Pcs0 Active Low (idles high). </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggad23a66cefb04826de83504ad485f19a9aa6ee5dca40cbe9bf03623cf986adbadd"></a>kDSPI_Pcs1ActiveLow</em> </td><td class="fielddoc">
|
|
<p>Pcs1 Active Low (idles high). </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggad23a66cefb04826de83504ad485f19a9a6fd76d22cb6c8f943ae397bb91ba68f4"></a>kDSPI_Pcs2ActiveLow</em> </td><td class="fielddoc">
|
|
<p>Pcs2 Active Low (idles high). </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggad23a66cefb04826de83504ad485f19a9a57e33d7e4195864f89db11d2f5e6cc4b"></a>kDSPI_Pcs3ActiveLow</em> </td><td class="fielddoc">
|
|
<p>Pcs3 Active Low (idles high). </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggad23a66cefb04826de83504ad485f19a9a15c201d8e7bd0bab1dd7117b73a111ec"></a>kDSPI_Pcs4ActiveLow</em> </td><td class="fielddoc">
|
|
<p>Pcs4 Active Low (idles high). </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggad23a66cefb04826de83504ad485f19a9a88e1e00a5a7755561358f004a5a1b1d4"></a>kDSPI_Pcs5ActiveLow</em> </td><td class="fielddoc">
|
|
<p>Pcs5 Active Low (idles high). </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="ggad23a66cefb04826de83504ad485f19a9adb2bef5058b4bf00533cc89f1928e2d1"></a>kDSPI_PcsAllActiveLow</em> </td><td class="fielddoc">
|
|
<p>Pcs0 to Pcs5 Active Low (idles high). </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="ga1e0a9074742794ef89f597d220296651"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga1e0a9074742794ef89f597d220296651">dspi_clock_polarity_t</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga1e0a9074742794ef89f597d220296651ab5279f36f0c6b1617aa937824806d71d"></a>kDSPI_ClockPolarityActiveHigh</em> </td><td class="fielddoc">
|
|
<p>CPOL=0. </p>
|
|
<p>Active-high DSPI clock (idles low). </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga1e0a9074742794ef89f597d220296651abcde58b8834e5cd1181b8b98aa4a10ef"></a>kDSPI_ClockPolarityActiveLow</em> </td><td class="fielddoc">
|
|
<p>CPOL=1. </p>
|
|
<p>Active-low DSPI clock (idles high). </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="ga4269ec144334dd60666a92e6fd2c1476"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga4269ec144334dd60666a92e6fd2c1476">dspi_clock_phase_t</a></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<table class="fieldtable">
|
|
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga4269ec144334dd60666a92e6fd2c1476a996e921abbf325ee9978a42681aee0d5"></a>kDSPI_ClockPhaseFirstEdge</em> </td><td class="fielddoc">
|
|
<p>CPHA=0. </p>
|
|
<p>Data is captured on the leading edge of the SCK and changed on the following edge. </p>
|
|
</td></tr>
|
|
<tr><td class="fieldname"><em><a class="anchor" id="gga4269ec144334dd60666a92e6fd2c1476a43ee643e847b3118e38da0a9811d97f9"></a>kDSPI_ClockPhaseSecondEdge</em> </td><td class="fielddoc">
|
|
<p>CPHA=1. </p>
|
|
<p>Data is changed on the leading edge of the SCK and captured on the following edge. </p>
|
|
</td></tr>
|
|
</table>
|
|
|
|
</div>
|
|
</div>
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<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga06fad8ae17b680f6dddfd798c9d3b30d">dspi_shift_direction_t</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga06fad8ae17b680f6dddfd798c9d3b30da8885a916a15d0b97ffd0f28d81242f6f"></a>kDSPI_MsbFirst</em> </td><td class="fielddoc">
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<p>Data transfers start with most significant bit. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga06fad8ae17b680f6dddfd798c9d3b30da76701314fa7dbd70e4011feb326b9050"></a>kDSPI_LsbFirst</em> </td><td class="fielddoc">
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<p>Data transfers start with least significant bit. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a class="anchor" id="ga1ca2fbee37b3cb046c075a7e765d64ed"></a>
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<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga1ca2fbee37b3cb046c075a7e765d64ed">dspi_delay_type_t</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga1ca2fbee37b3cb046c075a7e765d64eda71185ae0d4d9dd61acbc69bce93f33f5"></a>kDSPI_PcsToSck</em> </td><td class="fielddoc">
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<p>Pcs-to-SCK delay. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga1ca2fbee37b3cb046c075a7e765d64edaa2ce775b9575a3870ce82b8444b9d56c"></a>kDSPI_LastSckToPcs</em> </td><td class="fielddoc">
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<p>Last SCK edge to Pcs delay. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga1ca2fbee37b3cb046c075a7e765d64eda83ed3f05b8a61f94c0da066c1ded7a1e"></a>kDSPI_BetweenTransfer</em> </td><td class="fielddoc">
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<p>Delay between transfers. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a class="anchor" id="ga992d5562af4cf4c45371feb8c5c1a1bf"></a>
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<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga992d5562af4cf4c45371feb8c5c1a1bfadb2a4c8c9b722c6a1b8cbb03b17a6519"></a>kDSPI_Ctar0</em> </td><td class="fielddoc">
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<p>CTAR0 selection option for master or slave mode, note that CTAR0 and CTAR0_SLAVE are the same register address. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga992d5562af4cf4c45371feb8c5c1a1bfad6db3f5779fd74fdfa9bda2375573227"></a>kDSPI_Ctar1</em> </td><td class="fielddoc">
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<p>CTAR1 selection option for master mode only. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga992d5562af4cf4c45371feb8c5c1a1bfa406d09f42f5e009617a40f4c30cc10d9"></a>kDSPI_Ctar2</em> </td><td class="fielddoc">
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<p>CTAR2 selection option for master mode only , note that some device do not support CTAR2. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga992d5562af4cf4c45371feb8c5c1a1bfaf1df973bc8d89efbfb8d7bff51af0265"></a>kDSPI_Ctar3</em> </td><td class="fielddoc">
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<p>CTAR3 selection option for master mode only , note that some device do not support CTAR3. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga992d5562af4cf4c45371feb8c5c1a1bfa13960000166ae1cc18b19f5c4c9405ff"></a>kDSPI_Ctar4</em> </td><td class="fielddoc">
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<p>CTAR4 selection option for master mode only , note that some device do not support CTAR4. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga992d5562af4cf4c45371feb8c5c1a1bfad0b231829a94051ce913cd367135c1f2"></a>kDSPI_Ctar5</em> </td><td class="fielddoc">
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<p>CTAR5 selection option for master mode only , note that some device do not support CTAR5. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga992d5562af4cf4c45371feb8c5c1a1bfaa7bb6aaabeb65811e58af0460c38e373"></a>kDSPI_Ctar6</em> </td><td class="fielddoc">
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<p>CTAR6 selection option for master mode only , note that some device do not support CTAR6. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga992d5562af4cf4c45371feb8c5c1a1bfa6ae1a9c5243a507f36c3db1ef14c216e"></a>kDSPI_Ctar7</em> </td><td class="fielddoc">
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<p>CTAR7 selection option for master mode only , note that some device do not support CTAR7. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a class="anchor" id="gac74dfe19c844271a393314a4fd13792f"></a>
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<td class="memname">enum <a class="el" href="group__dspi__driver.html#gac74dfe19c844271a393314a4fd13792f">_dspi_transfer_config_flag_for_master</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792faf7ddf42278af30a1b81f10c4058ecddd"></a>kDSPI_MasterCtar0</em> </td><td class="fielddoc">
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<p>DSPI master transfer use CTAR0 setting. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa57508605f5d5fb0a2fb7eddfcdb89f12"></a>kDSPI_MasterCtar1</em> </td><td class="fielddoc">
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<p>DSPI master transfer use CTAR1 setting. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa6cf50df8fd75f5be1347efcaec8a68f4"></a>kDSPI_MasterCtar2</em> </td><td class="fielddoc">
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<p>DSPI master transfer use CTAR2 setting. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa70471fdf900dba881f4e742d303d307c"></a>kDSPI_MasterCtar3</em> </td><td class="fielddoc">
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<p>DSPI master transfer use CTAR3 setting. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792faad989e96bfed1f2fbb0fcc3adb99d04b"></a>kDSPI_MasterCtar4</em> </td><td class="fielddoc">
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<p>DSPI master transfer use CTAR4 setting. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa5c3dbe0ddb8e9f3f67496592ef3ec902"></a>kDSPI_MasterCtar5</em> </td><td class="fielddoc">
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<p>DSPI master transfer use CTAR5 setting. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa5e898da1cd4e093f048f947bc751b7fa"></a>kDSPI_MasterCtar6</em> </td><td class="fielddoc">
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<p>DSPI master transfer use CTAR6 setting. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa90cf553b9933d1e3d692469e0fa5ddc3"></a>kDSPI_MasterCtar7</em> </td><td class="fielddoc">
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<p>DSPI master transfer use CTAR7 setting. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fad51bd34d51062d900b07801e0fd193cc"></a>kDSPI_MasterPcs0</em> </td><td class="fielddoc">
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<p>DSPI master transfer use PCS0 signal. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fad07c95fafd30869cb6110d4ea3ed7ca1"></a>kDSPI_MasterPcs1</em> </td><td class="fielddoc">
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<p>DSPI master transfer use PCS1 signal. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa116fef8c0a72727a80e72e1d1d0d0ffc"></a>kDSPI_MasterPcs2</em> </td><td class="fielddoc">
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<p>DSPI master transfer use PCS2 signal. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa2266cc2ddbf05da3164fa6ad680facd9"></a>kDSPI_MasterPcs3</em> </td><td class="fielddoc">
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<p>DSPI master transfer use PCS3 signal. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa3b32f4a57a5aaaaf0064d7ec1373a154"></a>kDSPI_MasterPcs4</em> </td><td class="fielddoc">
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<p>DSPI master transfer use PCS4 signal. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa8047faff72926a57c0659f4147787353"></a>kDSPI_MasterPcs5</em> </td><td class="fielddoc">
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<p>DSPI master transfer use PCS5 signal. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa8309b1b52bbaa930bbcc3e2407f1a6f5"></a>kDSPI_MasterPcsContinuous</em> </td><td class="fielddoc">
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<p>Is PCS signal continuous. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggac74dfe19c844271a393314a4fd13792fa458df11cc493759474f31873cfa8d4c1"></a>kDSPI_MasterActiveAfterTransfer</em> </td><td class="fielddoc">
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<p>Is PCS signal active after last frame transfer. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a class="anchor" id="ga5070a73633ee72428adda72058f7fb5f"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga5070a73633ee72428adda72058f7fb5f">_dspi_transfer_config_flag_for_slave</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga5070a73633ee72428adda72058f7fb5fa6e63c217f9b392f78fb96ee039c991c8"></a>kDSPI_SlaveCtar0</em> </td><td class="fielddoc">
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<p>DSPI slave transfer use CTAR0 setting. </p>
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<p>DSPI slave can only use PCS0. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a class="anchor" id="ga97c65523863f89cddbf06691c678a7f9"></a>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">enum <a class="el" href="group__dspi__driver.html#ga97c65523863f89cddbf06691c678a7f9">_dspi_transfer_state</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga97c65523863f89cddbf06691c678a7f9ae739fb0dabff3a7cb72c39eef943a373"></a>kDSPI_Idle</em> </td><td class="fielddoc">
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<p>Nothing in the transmitter/receiver. </p>
|
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga97c65523863f89cddbf06691c678a7f9a4b636d65ab83d136e81ed31e30de4429"></a>kDSPI_Busy</em> </td><td class="fielddoc">
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<p>Transfer queue is not finished. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga97c65523863f89cddbf06691c678a7f9a6d94f11a50f542371683efe9ea22efb9"></a>kDSPI_Error</em> </td><td class="fielddoc">
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<p>Transfer error. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<h2 class="groupheader">Function Documentation</h2>
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<a class="anchor" id="gaadf23f732f4c1b61d6634bd17b1a36d7"></a>
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<div class="memitem">
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<td class="memname">void DSPI_MasterInit </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
|
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">const <a class="el" href="group__dspi__driver.html#structdspi__master__config__t">dspi_master_config_t</a> * </td>
|
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<td class="paramname"><em>masterConfig</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
|
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>srcClock_Hz</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function initializes the DSPI master configuration. An example use case is as follows: </p>
|
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#structdspi__master__config__t">dspi_master_config_t</a> masterConfig;</div>
|
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<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a822cafb9ccbaac368bdd456f004dd7f1">whichCtar</a> = <a class="code" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfadb2a4c8c9b722c6a1b8cbb03b17a6519">kDSPI_Ctar0</a>;</div>
|
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<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#abc9dde7dd3b924290ecd6180f7a7e0cb">baudRate</a> = 500000000;</div>
|
|
<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a935cc12276a643aac250e07b6fd26841">bitsPerFrame</a> = 8;</div>
|
|
<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a87112137c6b8b714d1700756557c86c9">cpol</a> = <a class="code" href="group__dspi__driver.html#gga1e0a9074742794ef89f597d220296651ab5279f36f0c6b1617aa937824806d71d">kDSPI_ClockPolarityActiveHigh</a>;</div>
|
|
<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a3649f0e62d8f5421366afb76792e957b">cpha</a> = <a class="code" href="group__dspi__driver.html#gga4269ec144334dd60666a92e6fd2c1476a996e921abbf325ee9978a42681aee0d5">kDSPI_ClockPhaseFirstEdge</a>;</div>
|
|
<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#aafbec5b2cc4cdec420381f29b32a04e8">direction</a> = <a class="code" href="group__dspi__driver.html#gga06fad8ae17b680f6dddfd798c9d3b30da8885a916a15d0b97ffd0f28d81242f6f">kDSPI_MsbFirst</a>;</div>
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|
<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a32c83fc580640a66049071dd9b672a1a">pcsToSckDelayInNanoSec</a> = 1000000000 / masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#abc9dde7dd3b924290ecd6180f7a7e0cb">baudRate</a> ;</div>
|
|
<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#af6e22013a735cf762e671973afbed487">lastSckToPcsDelayInNanoSec</a> = 1000000000 / masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#abc9dde7dd3b924290ecd6180f7a7e0cb">baudRate</a> ;</div>
|
|
<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a8d900155157617487c5089a91c41c638">betweenTransferDelayInNanoSec</a> = 1000000000 / masterConfig.<a class="code" href="group__dspi__driver.html#a31ffb9db13f0b3b9ac1cd6272674047b">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#abc9dde7dd3b924290ecd6180f7a7e0cb">baudRate</a> ;</div>
|
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<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a01111111bd757122f7874576e3b859e7">whichPcs</a> = <a class="code" href="group__dspi__driver.html#gga36d77cff6cfa202e0ff3a05ab4c2a632a5c6297be9586ee874fa1a84a16d810b7">kDSPI_Pcs0</a>;</div>
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<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a70b19520cae538f1860d355bacc4abca">pcsActiveHighOrLow</a> = <a class="code" href="group__dspi__driver.html#ggab466e73cb54b2c023459d43918c4197daa678a5937bbb9975e3c014592c3d542c">kDSPI_PcsActiveLow</a>;</div>
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<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a9fd922242d41c151599c4906c4d8d7f2">enableContinuousSCK</a> = <span class="keyword">false</span>;</div>
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<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#aa9a8bb9487711b83566ae0e04b386905">enableRxFifoOverWrite</a> = <span class="keyword">false</span>;</div>
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<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a86656569461eb376c1a7db424efb8916">enableModifiedTimingFormat</a> = <span class="keyword">false</span>;</div>
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<div class="line">* masterConfig.<a class="code" href="group__dspi__driver.html#a1827b5d3bf3ff28b7ce940bbae1a6d35">samplePoint</a> = <a class="code" href="group__dspi__driver.html#ggae783895e2917abe07adbe27a253510a2abbcf84bafbd94a63a9600647162b8d86">kDSPI_SckToSin0Clock</a>;</div>
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<div class="line">* <a class="code" href="group__dspi__driver.html#gaadf23f732f4c1b61d6634bd17b1a36d7">DSPI_MasterInit</a>(base, &masterConfig, srcClock_Hz);</div>
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<div class="line">* </div>
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</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">masterConfig</td><td>Pointer to structure <a class="el" href="group__dspi__driver.html#structdspi__master__config__t" title="DSPI master configuration structure. ">dspi_master_config_t</a>. </td></tr>
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<tr><td class="paramname">srcClock_Hz</td><td>Module source input clock in Hertz </td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void DSPI_MasterGetDefaultConfig </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__master__config__t">dspi_master_config_t</a> * </td>
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<td class="paramname"><em>masterConfig</em></td><td>)</td>
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<td></td>
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<p>The purpose of this API is to get the configuration structure initialized for the <a class="el" href="group__dspi__driver.html#gaadf23f732f4c1b61d6634bd17b1a36d7" title="Initializes the DSPI master. ">DSPI_MasterInit()</a>. User may use the initialized structure unchanged in <a class="el" href="group__dspi__driver.html#gaadf23f732f4c1b61d6634bd17b1a36d7" title="Initializes the DSPI master. ">DSPI_MasterInit()</a> or modify the structure before calling <a class="el" href="group__dspi__driver.html#gaadf23f732f4c1b61d6634bd17b1a36d7" title="Initializes the DSPI master. ">DSPI_MasterInit()</a>. Example: </p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#structdspi__master__config__t">dspi_master_config_t</a> masterConfig;</div>
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<div class="line">* <a class="code" href="group__dspi__driver.html#ga0061c90bc787dc1faffde79cb256e8a4">DSPI_MasterGetDefaultConfig</a>(&masterConfig);</div>
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<div class="line">* </div>
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</div><!-- fragment --> <dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">masterConfig</td><td>pointer to <a class="el" href="group__dspi__driver.html#structdspi__master__config__t" title="DSPI master configuration structure. ">dspi_master_config_t</a> structure </td></tr>
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<td class="memname">void DSPI_SlaveInit </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramtype">const <a class="el" href="group__dspi__driver.html#structdspi__slave__config__t">dspi_slave_config_t</a> * </td>
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<td class="paramname"><em>slaveConfig</em> </td>
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<td></td>
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<td>)</td>
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<p>This function initializes the DSPI slave configuration. An example use case is as follows: </p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#structdspi__slave__config__t">dspi_slave_config_t</a> slaveConfig;</div>
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<div class="line">* slaveConfig-><a class="code" href="group__dspi__driver.html#a7b488cbe0d44e605c74341b241aba6e8">whichCtar</a> = <a class="code" href="group__dspi__driver.html#gga992d5562af4cf4c45371feb8c5c1a1bfadb2a4c8c9b722c6a1b8cbb03b17a6519">kDSPI_Ctar0</a>;</div>
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<div class="line">* slaveConfig-><a class="code" href="group__dspi__driver.html#aa69a2a4dab7a6e026ee1e568418b18f7">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a3ddbe384d7b4c256ced99ea6671ed73d">bitsPerFrame</a> = 8;</div>
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<div class="line">* slaveConfig-><a class="code" href="group__dspi__driver.html#aa69a2a4dab7a6e026ee1e568418b18f7">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#abc3449874392a507f8ca15263119001e">cpol</a> = <a class="code" href="group__dspi__driver.html#gga1e0a9074742794ef89f597d220296651ab5279f36f0c6b1617aa937824806d71d">kDSPI_ClockPolarityActiveHigh</a>;</div>
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<div class="line">* slaveConfig-><a class="code" href="group__dspi__driver.html#aa69a2a4dab7a6e026ee1e568418b18f7">ctarConfig</a>.<a class="code" href="group__dspi__driver.html#a80127ee24970efe8ea1c8760bb647ce5">cpha</a> = <a class="code" href="group__dspi__driver.html#gga4269ec144334dd60666a92e6fd2c1476a996e921abbf325ee9978a42681aee0d5">kDSPI_ClockPhaseFirstEdge</a>;</div>
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<div class="line">* slaveConfig-><a class="code" href="group__dspi__driver.html#abd2c9b108ae18e0abd71fbb457d17d70">enableContinuousSCK</a> = <span class="keyword">false</span>;</div>
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<div class="line">* slaveConfig-><a class="code" href="group__dspi__driver.html#ad1db8c46797dbc50d5a3b2a915b8ce58">enableRxFifoOverWrite</a> = <span class="keyword">false</span>;</div>
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<div class="line">* slaveConfig-><a class="code" href="group__dspi__driver.html#a9a8cd1afddd8edca36c217d1f4e440ad">enableModifiedTimingFormat</a> = <span class="keyword">false</span>;</div>
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<div class="line">* slaveConfig-><a class="code" href="group__dspi__driver.html#a7771f990c0f85360232e144cb0f467f2">samplePoint</a> = <a class="code" href="group__dspi__driver.html#ggae783895e2917abe07adbe27a253510a2abbcf84bafbd94a63a9600647162b8d86">kDSPI_SckToSin0Clock</a>;</div>
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<div class="line">* <a class="code" href="group__dspi__driver.html#gacf6cecb6b73f02eaa448634a8d705851">DSPI_SlaveInit</a>(base, &slaveConfig);</div>
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<div class="line">* </div>
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</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">slaveConfig</td><td>Pointer to structure <a class="el" href="group__dspi__driver.html#structdspi__master__config__t" title="DSPI master configuration structure. ">dspi_master_config_t</a>. </td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void DSPI_SlaveGetDefaultConfig </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__slave__config__t">dspi_slave_config_t</a> * </td>
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<td class="paramname"><em>slaveConfig</em></td><td>)</td>
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<p>The purpose of this API is to get the configuration structure initialized for the <a class="el" href="group__dspi__driver.html#gacf6cecb6b73f02eaa448634a8d705851" title="DSPI slave configuration. ">DSPI_SlaveInit()</a>. User may use the initialized structure unchanged in <a class="el" href="group__dspi__driver.html#gacf6cecb6b73f02eaa448634a8d705851" title="DSPI slave configuration. ">DSPI_SlaveInit()</a>, or modify the structure before calling <a class="el" href="group__dspi__driver.html#gacf6cecb6b73f02eaa448634a8d705851" title="DSPI slave configuration. ">DSPI_SlaveInit()</a>. Example: </p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#structdspi__slave__config__t">dspi_slave_config_t</a> slaveConfig;</div>
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<div class="line">* <a class="code" href="group__dspi__driver.html#gad85a8d4e7bd2747103691a63ef9a67e1">DSPI_SlaveGetDefaultConfig</a>(&slaveConfig);</div>
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<div class="line">* </div>
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</div><!-- fragment --> <dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">slaveConfig</td><td>pointer to <a class="el" href="group__dspi__driver.html#structdspi__slave__config__t" title="DSPI slave configuration structure. ">dspi_slave_config_t</a> structure. </td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void DSPI_Deinit </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em></td><td>)</td>
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<p>Call this API to disable the DSPI clock. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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</dd>
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<td class="memname">static void DSPI_Enable </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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<td></td>
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<td>)</td>
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">enable</td><td>pass true to enable module, false to disable module. </td></tr>
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<td class="memname">static uint32_t DSPI_GetStatusFlags </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>The DSPI status(in SR register). </dd></dl>
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<td class="memname">static void DSPI_ClearStatusFlags </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<p>This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The function uses these bit positions in its algorithm to clear the desired flag state. Example usage: </p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#ga11454768ad4c96b65b298cccf1f0401c">DSPI_ClearStatusFlags</a>(base, <a class="code" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904faffc8e8711d9083470cddb0db647b75b0">kDSPI_TxCompleteFlag</a>|<a class="code" href="group__dspi__driver.html#gga2bfefaf6ba65ba464e764d1c918c904fae91c7a5cc2a90fa051c89f13bbb6d8ed">kDSPI_EndOfQueueFlag</a>);</div>
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<div class="line">* </div>
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</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">statusFlags</td><td>The status flag , used from type dspi_flags. </td></tr>
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<p>< The status flags are cleared by writing 1 (w1c). </p>
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<td class="memname">void DSPI_EnableInterrupts </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>mask</em> </td>
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<td>)</td>
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<p>This function configures the various interrupt masks of the DSPI. The parameters are base and an interrupt mask. Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.</p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#ga9b9e4c8ae54ea108952c80940e11b3a8">DSPI_EnableInterrupts</a>(base, <a class="code" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2ab2b1ba228fd75de23a2de7e56c1ee438">kDSPI_TxCompleteInterruptEnable</a> | <a class="code" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2a069483b28469fcbfa5890b04cd6439b3">kDSPI_EndOfQueueInterruptEnable</a> );</div>
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<div class="line">* </div>
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</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">mask</td><td>The interrupt mask, can use the enum _dspi_interrupt_enable. </td></tr>
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<td class="memname">static void DSPI_DisableInterrupts </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>mask</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#gabf5c4ec1216387b8c476853e45a9bfeb">DSPI_DisableInterrupts</a>(base, <a class="code" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2ab2b1ba228fd75de23a2de7e56c1ee438">kDSPI_TxCompleteInterruptEnable</a> | <a class="code" href="group__dspi__driver.html#ggaeb57298690a2f1a09d94d696c893c4b2a069483b28469fcbfa5890b04cd6439b3">kDSPI_EndOfQueueInterruptEnable</a> );</div>
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<div class="line">* </div>
|
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</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
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<tr><td class="paramname">mask</td><td>The interrupt mask, can use the enum _dspi_interrupt_enable. </td></tr>
|
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</table>
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</dd>
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</dl>
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<td class="memname">static void DSPI_EnableDMA </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>mask</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask. </p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#ga313d41fd54ca75781bb7596b319d4849">DSPI_EnableDMA</a>(base, <a class="code" href="group__dspi__driver.html#ggae3359796dc0680797b1f74b83fc0c0d9ae772dc49e5a28df00b817f9c6dab0749">kDSPI_TxDmaEnable</a> | <a class="code" href="group__dspi__driver.html#ggae3359796dc0680797b1f74b83fc0c0d9a15ec9c9897199d53a1b354ccce6d0445">kDSPI_RxDmaEnable</a>);</div>
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<div class="line">* </div>
|
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</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
<tr><td class="paramname">mask</td><td>The interrupt mask can use the enum dspi_dma_enable. </td></tr>
|
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</table>
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</dd>
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</dl>
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</div>
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<a class="anchor" id="ga543b12952cb5ac404ebbdaa572628c8e"></a>
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<td class="memname">static void DSPI_DisableDMA </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>mask</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask. </p>
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<div class="fragment"><div class="line">* SPI_DisableDMA(base, <a class="code" href="group__dspi__driver.html#ggae3359796dc0680797b1f74b83fc0c0d9ae772dc49e5a28df00b817f9c6dab0749">kDSPI_TxDmaEnable</a> | <a class="code" href="group__dspi__driver.html#ggae3359796dc0680797b1f74b83fc0c0d9a15ec9c9897199d53a1b354ccce6d0445">kDSPI_RxDmaEnable</a>);</div>
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<div class="line">* </div>
|
|
</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
<tr><td class="paramname">mask</td><td>The interrupt mask can use the enum dspi_dma_enable. </td></tr>
|
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</table>
|
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gad3e8a8107cfda29dbae45fc5166d63f3"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="mlabels-left">
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<td class="memname">static uint32_t DSPI_MasterGetTxRegisterAddress </td>
|
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<td>(</td>
|
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<td class="paramtype">SPI_Type * </td>
|
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<td class="paramname"><em>base</em></td><td>)</td>
|
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<td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section return"><dt>Returns</dt><dd>The DSPI master PUSHR data register address. </dd></dl>
|
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</div>
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</div>
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<a class="anchor" id="ga8912754715dfadde5473a419f7b8ff93"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="mlabels">
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<tr>
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<td class="mlabels-left">
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<table class="memname">
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<td class="memname">static uint32_t DSPI_SlaveGetTxRegisterAddress </td>
|
|
<td>(</td>
|
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<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em></td><td>)</td>
|
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<td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section return"><dt>Returns</dt><dd>The DSPI slave PUSHR data register address. </dd></dl>
|
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</div>
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</div>
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<a class="anchor" id="ga0d2bcb0a744852ab2701466a7fd974f6"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="mlabels-left">
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<td class="memname">static uint32_t DSPI_GetRxRegisterAddress </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em></td><td>)</td>
|
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<td></td>
|
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</tr>
|
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</table>
|
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</td>
|
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
|
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<p>This function gets the DSPI POPR data register address as this value is needed for the DMA operation.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section return"><dt>Returns</dt><dd>The DSPI POPR data register address. </dd></dl>
|
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|
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</div>
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</div>
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<a class="anchor" id="gac3e11f3876e81d7636a77fb268c2365a"></a>
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<div class="memitem">
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<tr>
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<td class="memname">static void DSPI_SetMasterSlaveMode </td>
|
|
<td>(</td>
|
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<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
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<td></td>
|
|
<td class="paramtype"><a class="el" href="group__dspi__driver.html#gad7f974015f32db057dafada8b95641aa">dspi_master_slave_mode_t</a> </td>
|
|
<td class="paramname"><em>mode</em> </td>
|
|
</tr>
|
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
<tr><td class="paramname">mode</td><td>Mode setting (master or slave) of type dspi_master_slave_mode_t. </td></tr>
|
|
</table>
|
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</dd>
|
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</dl>
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</div>
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</div>
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<a class="anchor" id="gae606c91960692b493d17d067c38d67b3"></a>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">static bool DSPI_IsMaster </td>
|
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<td>(</td>
|
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<td class="paramtype">SPI_Type * </td>
|
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<td class="paramname"><em>base</em></td><td>)</td>
|
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<td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section return"><dt>Returns</dt><dd>Returns true if the module is in master mode or false if the module is in slave mode. </dd></dl>
|
|
|
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</div>
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</div>
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<a class="anchor" id="gac3fb40ea05b407f5b335c0a47330e3a8"></a>
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<div class="memitem">
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<td class="memname">static void DSPI_StartTransfer </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em></td><td>)</td>
|
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<td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</table>
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</div><div class="memdoc">
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<p>This function sets the module to begin data transfer in either master or slave mode.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
</table>
|
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</dd>
|
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga09021ebd27d4ccf5d85398b5bbf12045"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="mlabels">
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<tr>
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<td class="mlabels-left">
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<table class="memname">
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<td class="memname">static void DSPI_StopTransfer </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em></td><td>)</td>
|
|
<td></td>
|
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</tr>
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</table>
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</td>
|
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<td class="mlabels-right">
|
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
|
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</div><div class="memdoc">
|
|
<p>This function stops data transfers in either master or slave mode.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
|
|
|
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</div>
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</div>
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<a class="anchor" id="gad9112153c575eeeb6af747d9e6396514"></a>
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<td class="memname">static void DSPI_SetFifoEnable </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">bool </td>
|
|
<td class="paramname"><em>enableTxFifo</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">bool </td>
|
|
<td class="paramname"><em>enableRxFifo</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
|
|
<td></td><td></td>
|
|
</tr>
|
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</table>
|
|
</td>
|
|
<td class="mlabels-right">
|
|
<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
|
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</tr>
|
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</table>
|
|
</div><div class="memdoc">
|
|
<p>This function allows the caller to disable/enable the Tx and Rx FIFOs (independently). Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO configuration. To enable, the caller must pass in a logic 1 (true).</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
<tr><td class="paramname">enableTxFifo</td><td>Disables (false) the TX FIFO, else enables (true) the TX FIFO </td></tr>
|
|
<tr><td class="paramname">enableRxFifo</td><td>Disables (false) the RX FIFO, else enables (true) the RX FIFO </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
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</div>
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</div>
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<a class="anchor" id="ga3cbb532b5bd6981f5cc0115f49a9ee9a"></a>
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<div class="memitem">
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<div class="memproto">
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<td class="mlabels-left">
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<table class="memname">
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<tr>
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<td class="memname">static void DSPI_FlushFifo </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">bool </td>
|
|
<td class="paramname"><em>flushTxFifo</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">bool </td>
|
|
<td class="paramname"><em>flushRxFifo</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
|
|
<td></td><td></td>
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">flushTxFifo</td><td>Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO </td></tr>
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<tr><td class="paramname">flushRxFifo</td><td>Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO </td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">static void DSPI_SetAllPcsPolarity </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>mask</em> </td>
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<td></td>
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<td>)</td>
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</td>
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</div><div class="memdoc">
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<p>For example, PCS0 and PCS1 set to active low and other PCS set to active high. Note that the number of PCSs is specific to the device. </p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#ga1c42d5efc75982041f4a66f4f1fc71a4">DSPI_SetAllPcsPolarity</a>(base, <a class="code" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9ac731b21eefcc16342d2c606a12a00547">kDSPI_Pcs0ActiveLow</a> | <a class="code" href="group__dspi__driver.html#ggad23a66cefb04826de83504ad485f19a9aa6ee5dca40cbe9bf03623cf986adbadd">kDSPI_Pcs1ActiveLow</a>);</div>
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</div><!-- fragment --> <dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">mask</td><td>The PCS polarity mask , can use the enum _dspi_pcs_polarity. </td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">uint32_t DSPI_MasterSetBaudRate </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> </td>
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<td class="paramname"><em>whichCtar</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>baudRate_Bps</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>srcClock_Hz</em> </td>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the caller also provide the frequency of the module source clock (in Hertz).</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">whichCtar</td><td>The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t </td></tr>
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<tr><td class="paramname">baudRate_Bps</td><td>The desired baud rate in bits per second </td></tr>
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<tr><td class="paramname">srcClock_Hz</td><td>Module source input clock in Hertz </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>The actual calculated baud rate </dd></dl>
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<td class="memname">void DSPI_MasterSetDelayScaler </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> </td>
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<td class="paramname"><em>whichCtar</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>prescaler</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>scaler</em>, </td>
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</tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#ga1ca2fbee37b3cb046c075a7e765d64ed">dspi_delay_type_t</a> </td>
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<td class="paramname"><em>whichDelay</em> </td>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT)and scalar (DT).</p>
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<p>These delay names are available in type dspi_delay_type_t.</p>
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<p>The user passes the delay to configure along with the prescaler and scaler value. This allows the user to directly set the prescaler/scaler values if they have pre-calculated them or if they simply wish to manually increment either value.</p>
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<dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
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<tr><td class="paramname">whichCtar</td><td>The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. </td></tr>
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<tr><td class="paramname">prescaler</td><td>The prescaler delay value (can be an integer 0, 1, 2, or 3). </td></tr>
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<tr><td class="paramname">scaler</td><td>The scaler delay value (can be any integer between 0 to 15). </td></tr>
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<tr><td class="paramname">whichDelay</td><td>The desired delay to configure, must be of type dspi_delay_type_t </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<td class="memname">uint32_t DSPI_MasterSetDelayTimes </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#ga992d5562af4cf4c45371feb8c5c1a1bf">dspi_ctar_selection_t</a> </td>
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<td class="paramname"><em>whichCtar</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#ga1ca2fbee37b3cb046c075a7e765d64ed">dspi_delay_type_t</a> </td>
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<td class="paramname"><em>whichDelay</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>srcClock_Hz</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>delayTimeInNanoSec</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>This function calculates the values for: PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or After SCK delay pre-scalar (PASC) and scalar (ASC), or Delay after transfer pre-scalar (PDT)and scalar (DT).</p>
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<p>These delay names are available in type dspi_delay_type_t.</p>
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<p>The user passes which delay they want to configure along with the desired delay value in nanoseconds. The function calculates the values needed for the prescaler and scaler and returning the actual calculated delay as an exact delay match may not be possible. In this case, the closest match is calculated without going below the desired delay value input. It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay input.</p>
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
|
<tr><td class="paramname">whichCtar</td><td>The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. </td></tr>
|
|
<tr><td class="paramname">whichDelay</td><td>The desired delay to configure, must be of type dspi_delay_type_t </td></tr>
|
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<tr><td class="paramname">srcClock_Hz</td><td>Module source input clock in Hertz </td></tr>
|
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<tr><td class="paramname">delayTimeInNanoSec</td><td>The desired delay value in nanoseconds. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>The actual calculated delay value. </dd></dl>
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</div>
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<a class="anchor" id="gabe0d615b273c4cb0eaf26d9679b73ad6"></a>
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<td class="memname">static void DSPI_MasterWriteData </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> * </td>
|
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<td class="paramname"><em>command</em>, </td>
|
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint16_t </td>
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<td class="paramname"><em>data</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</div><div class="memdoc">
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<p>In master mode, the 16-bit data is appended to the 16-bit command info. The command portion provides characteristics of the data such as the optional continuous chip select operation between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the transfer count (normally needed when sending the first frame of a data packet). This is an example: </p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> commandConfig;</div>
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<div class="line">* commandConfig.<a class="code" href="group__dspi__driver.html#a1b7521543b11fe504f32d7beb728c14d">isPcsContinuous</a> = <span class="keyword">true</span>;</div>
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<div class="line">* commandConfig.<a class="code" href="group__dspi__driver.html#a4cf94a2dd0b6fbab04b32349b68363b5">whichCtar</a> = kDSPICtar0;</div>
|
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<div class="line">* commandConfig.<a class="code" href="group__dspi__driver.html#aedc892927ff6ec53266a60b413684ace">whichPcs</a> = kDSPIPcs0;</div>
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<div class="line">* commandConfig.<a class="code" href="group__dspi__driver.html#aaf4b200e2ca05a92686ff5e158e3a61f">clearTransferCount</a> = <span class="keyword">false</span>;</div>
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<div class="line">* commandConfig.<a class="code" href="group__dspi__driver.html#a378b8b8a618355869de07b435ad52f82">isEndOfQueue</a> = <span class="keyword">false</span>;</div>
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<div class="line">* <a class="code" href="group__dspi__driver.html#gabe0d615b273c4cb0eaf26d9679b73ad6">DSPI_MasterWriteData</a>(base, &commandConfig, dataWord);</div>
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</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
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<tr><td class="paramname">command</td><td>Pointer to command structure. </td></tr>
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<tr><td class="paramname">data</td><td>The data word to be sent. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<a class="anchor" id="gad9f3df616e7284696af57cce8f49899e"></a>
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<td class="memname">void DSPI_GetDefaultDataCommandConfig </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> * </td>
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<td class="paramname"><em>command</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). User may use the initialized structure unchanged in DSPI_MasterWrite_xx() or modify the structure before calling DSPI_MasterWrite_xx(). Example: </p>
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<div class="fragment"><div class="line">* <a class="code" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> command;</div>
|
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<div class="line">* <a class="code" href="group__dspi__driver.html#gad9f3df616e7284696af57cce8f49899e">DSPI_GetDefaultDataCommandConfig</a>(&command);</div>
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<div class="line">* </div>
|
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</div><!-- fragment --> <dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
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<tr><td class="paramname">command</td><td>pointer to <a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t" title="DSPI master command date configuration used for SPIx_PUSHR. ">dspi_command_data_config_t</a> structure. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga70a0f7d7fe2fbce7993bbcc8c427b2b0"></a>
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<td class="memname">void DSPI_MasterWriteDataBlocking </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> * </td>
|
|
<td class="paramname"><em>command</em>, </td>
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</tr>
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<tr>
|
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<td class="paramkey"></td>
|
|
<td></td>
|
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<td class="paramtype">uint16_t </td>
|
|
<td class="paramname"><em>data</em> </td>
|
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</tr>
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<tr>
|
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>In master mode, the 16-bit data is appended to the 16-bit command info. The command portion provides characteristics of the data such as the optional continuous chip select operation between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the transfer count (normally needed when sending the first frame of a data packet). This is an example: </p>
|
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<div class="fragment"><div class="line">* dspi_command_config_t commandConfig;</div>
|
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<div class="line">* commandConfig.<a class="code" href="group__dspi__driver.html#a1b7521543b11fe504f32d7beb728c14d">isPcsContinuous</a> = <span class="keyword">true</span>;</div>
|
|
<div class="line">* commandConfig.whichCtar = kDSPICtar0;</div>
|
|
<div class="line">* commandConfig.whichPcs = kDSPIPcs1;</div>
|
|
<div class="line">* commandConfig.clearTransferCount = <span class="keyword">false</span>;</div>
|
|
<div class="line">* commandConfig.isEndOfQueue = <span class="keyword">false</span>;</div>
|
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<div class="line">* <a class="code" href="group__dspi__driver.html#ga70a0f7d7fe2fbce7993bbcc8c427b2b0">DSPI_MasterWriteDataBlocking</a>(base, &commandConfig, dataWord);</div>
|
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<div class="line">* </div>
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</div><!-- fragment --><p>Note that this function does not return until after the transmit is complete. Also note that the DSPI must be enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, receive data is available when transmit completes.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">command</td><td>Pointer to command structure. </td></tr>
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<tr><td class="paramname">data</td><td>The data word to be sent. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<td class="mlabels-left">
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<td class="memname">static uint32_t DSPI_MasterGetFormattedCommand </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__command__data__config__t">dspi_command_data_config_t</a> * </td>
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<td class="paramname"><em>command</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function allows the caller to pass in the data command structure and returns the command word formatted according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps improve performance in cases where the command structure is constant. For example, the user calls this function before starting a transfer to generate the command word. When they are ready to transmit the data, they OR this formatted command word with the desired data to transmit. This process increases transmit performance when compared to calling send functions such as DSPI_HAL_WriteDataMastermode which format the command word each time a data word is to be sent.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">command</td><td>Pointer to command structure. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>The command word formatted to the PUSHR data register bit field. </dd></dl>
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</div>
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<a class="anchor" id="ga0718581088422b572cb4494f26aad1f9"></a>
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<div class="memitem">
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<tr>
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<td class="memname">void DSPI_MasterWriteCommandDataBlocking </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>data</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>In this function, the user must append the 16-bit data to the 16-bit command info then provide the total 32-bit word as the data to send. The command portion provides characteristics of the data such as the optional continuous chip select operation between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the transfer count (normally needed when sending the first frame of a data packet). The user is responsible for appending this command with the data to send. This is an example: </p>
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<div class="fragment"><div class="line">* dataWord = <16-bit command> | <16-bit data>;</div>
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<div class="line">* DSPI_HAL_WriteCommandDataMastermodeBlocking(base, dataWord);</div>
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<div class="line">* </div>
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</div><!-- fragment --><p>Note that this function does not return until after the transmit is complete. Also note that the DSPI must be enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, the receive data is available when transmit completes.</p>
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<p>For a blocking polling transfer, see methods below. Option 1: uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); uint32_t data0 = command_to_send | data_need_to_send_0; uint32_t data1 = command_to_send | data_need_to_send_1; uint32_t data2 = command_to_send | data_need_to_send_2;</p>
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<p>DSPI_MasterWriteCommandDataBlocking(base,data0); DSPI_MasterWriteCommandDataBlocking(base,data1); DSPI_MasterWriteCommandDataBlocking(base,data2);</p>
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<p>Option 2: DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">data</td><td>The data word (command and data combined) to be sent </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<td class="mlabels-left">
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<td class="memname">static void DSPI_SlaveWriteData </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>data</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>In slave mode, up to 16-bit words may be written.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
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<tr><td class="paramname">data</td><td>The data to send. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gad7a98ccdb5dcd3ea9c282893b79cee79"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void DSPI_SlaveWriteDataBlocking </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>data</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data into data register, and finally waits until the data is transmitted.</p>
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
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<tr><td class="paramname">data</td><td>The data to send. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gaee93673062a6fb105dcf1e0541dd8b52"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="mlabels-left">
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<table class="memname">
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<tr>
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<td class="memname">static uint32_t DSPI_ReadData </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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</tr>
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</table>
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</div><div class="memdoc">
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral address. </td></tr>
|
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</table>
|
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>The data from the read data buffer. </dd></dl>
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</div>
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</div>
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<a class="anchor" id="ga63e04b92d99d795cf84df62379765a91"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="memname">void DSPI_MasterTransferCreateHandle </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
|
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</tr>
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<tr>
|
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<td class="paramkey"></td>
|
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<td></td>
|
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<td class="paramtype">dspi_master_handle_t * </td>
|
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<td class="paramname"><em>handle</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#gad191922bda6ac07f95f241a67eb52f48">dspi_master_transfer_callback_t</a> </td>
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<td class="paramname"><em>callback</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">void * </td>
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<td class="paramname"><em>userData</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function initializes the DSPI handle which can be used for other DSPI transactional APIs. Usually, for a specified DSPI instance, call this API once to get the initialized handle.</p>
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|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">handle</td><td>DSPI handle pointer to dspi_master_handle_t. </td></tr>
|
|
<tr><td class="paramname">callback</td><td>dspi callback. </td></tr>
|
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<tr><td class="paramname">userData</td><td>callback function parameter. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gab2d0aa3acb2acc3cc5413314d758628b"></a>
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<div class="memitem">
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<div class="memproto">
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<td class="memname">status_t DSPI_MasterTransferBlocking </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
|
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<td class="paramname"><em>base</em>, </td>
|
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</tr>
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<tr>
|
|
<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__transfer__t">dspi_transfer_t</a> * </td>
|
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<td class="paramname"><em>transfer</em> </td>
|
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function transfers data with polling. This is a blocking function, which does not return until all transfers have been completed.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">transfer</td><td>pointer to <a class="el" href="group__dspi__driver.html#structdspi__transfer__t" title="DSPI master/slave transfer structure. ">dspi_transfer_t</a> structure. </td></tr>
|
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</table>
|
|
</dd>
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</dl>
|
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<dl class="section return"><dt>Returns</dt><dd>status of status_t. </dd></dl>
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</div>
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</div>
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<a class="anchor" id="gad3dc7b85b448ce6e16e227d7bf3769d6"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">status_t DSPI_MasterTransferNonBlocking </td>
|
|
<td>(</td>
|
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<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">dspi_master_handle_t * </td>
|
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<td class="paramname"><em>handle</em>, </td>
|
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</tr>
|
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<tr>
|
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__transfer__t">dspi_transfer_t</a> * </td>
|
|
<td class="paramname"><em>transfer</em> </td>
|
|
</tr>
|
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<tr>
|
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all data have been transferred, the callback function is called.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">handle</td><td>pointer to dspi_master_handle_t structure which stores the transfer state. </td></tr>
|
|
<tr><td class="paramname">transfer</td><td>pointer to <a class="el" href="group__dspi__driver.html#structdspi__transfer__t" title="DSPI master/slave transfer structure. ">dspi_transfer_t</a> structure. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section return"><dt>Returns</dt><dd>status of status_t. </dd></dl>
|
|
|
|
</div>
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</div>
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<a class="anchor" id="gadaf98a7213c03f10d5820d363e827a73"></a>
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<div class="memitem">
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<td class="memname">status_t DSPI_MasterTransferGetCount </td>
|
|
<td>(</td>
|
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<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
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<td class="paramtype">dspi_master_handle_t * </td>
|
|
<td class="paramname"><em>handle</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">size_t * </td>
|
|
<td class="paramname"><em>count</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
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<td>)</td>
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<td></td><td></td>
|
|
</tr>
|
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</table>
|
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</div><div class="memdoc">
|
|
<p>This function gets the master transfer count.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">handle</td><td>pointer to dspi_master_handle_t structure which stores the transfer state. </td></tr>
|
|
<tr><td class="paramname">count</td><td>Number of bytes transferred so far by the non-blocking transaction. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section return"><dt>Returns</dt><dd>status of status_t. </dd></dl>
|
|
|
|
</div>
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</div>
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<a class="anchor" id="ga80633e998c10cb83685d6c64ecd33a55"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void DSPI_MasterTransferAbort </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">dspi_master_handle_t * </td>
|
|
<td class="paramname"><em>handle</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
|
|
<p>This function aborts a transfer using an interrupt.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">handle</td><td>pointer to dspi_master_handle_t structure which stores the transfer state. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
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</div>
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</div>
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<a class="anchor" id="ga195eed1bfdc0d21e7adb76a5d6d247dc"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
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<td class="memname">void DSPI_MasterTransferHandleIRQ </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">dspi_master_handle_t * </td>
|
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<td class="paramname"><em>handle</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function processes the DSPI transmit and receive IRQ.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
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<tr><td class="paramname">handle</td><td>pointer to dspi_master_handle_t structure which stores the transfer state. </td></tr>
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</table>
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</dd>
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</dl>
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<a class="anchor" id="gadc23691aa2c06ae9076a5f0b16f33a8c"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void DSPI_SlaveTransferCreateHandle </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">dspi_slave_handle_t * </td>
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<td class="paramname"><em>handle</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#ga0c9ef1b6a6d8034b5e47b8310f2d52dc">dspi_slave_transfer_callback_t</a> </td>
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<td class="paramname"><em>callback</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">void * </td>
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<td class="paramname"><em>userData</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a specified DSPI instance, call this API once to get the initialized handle.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">handle</td><td>DSPI handle pointer to dspi_slave_handle_t. </td></tr>
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<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
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<tr><td class="paramname">callback</td><td>DSPI callback. </td></tr>
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<tr><td class="paramname">userData</td><td>callback function parameter. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga81f85324750f75b8e7248846c88d99e7"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">status_t DSPI_SlaveTransferNonBlocking </td>
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<td>(</td>
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<td class="paramtype">SPI_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">dspi_slave_handle_t * </td>
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<td class="paramname"><em>handle</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__dspi__driver.html#structdspi__transfer__t">dspi_transfer_t</a> * </td>
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<td class="paramname"><em>transfer</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all data have been transferred, the callback function is called.</p>
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">handle</td><td>pointer to dspi_slave_handle_t structure which stores the transfer state. </td></tr>
|
|
<tr><td class="paramname">transfer</td><td>pointer to <a class="el" href="group__dspi__driver.html#structdspi__transfer__t" title="DSPI master/slave transfer structure. ">dspi_transfer_t</a> structure. </td></tr>
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</table>
|
|
</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>status of status_t. </dd></dl>
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</div>
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</div>
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<a class="anchor" id="ga4134bb536420951e8ecbe8edb987d199"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">status_t DSPI_SlaveTransferGetCount </td>
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|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">dspi_slave_handle_t * </td>
|
|
<td class="paramname"><em>handle</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
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<td></td>
|
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<td class="paramtype">size_t * </td>
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|
<td class="paramname"><em>count</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function gets the slave transfer count.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">handle</td><td>pointer to dspi_master_handle_t structure which stores the transfer state. </td></tr>
|
|
<tr><td class="paramname">count</td><td>Number of bytes transferred so far by the non-blocking transaction. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section return"><dt>Returns</dt><dd>status of status_t. </dd></dl>
|
|
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</div>
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</div>
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<a class="anchor" id="ga7e1be1f74fd8d372ce1af52c960d1361"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void DSPI_SlaveTransferAbort </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">dspi_slave_handle_t * </td>
|
|
<td class="paramname"><em>handle</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
|
|
<td></td><td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<p>This function aborts transfer using an interrupt.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">handle</td><td>pointer to dspi_slave_handle_t structure which stores the transfer state. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
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<a class="anchor" id="gade8288c503cc6c7af542cdc86947ecd3"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void DSPI_SlaveTransferHandleIRQ </td>
|
|
<td>(</td>
|
|
<td class="paramtype">SPI_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">dspi_slave_handle_t * </td>
|
|
<td class="paramname"><em>handle</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
|
|
<td></td><td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
<p>This function processes the DSPI transmit and receive IRQ.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>DSPI peripheral base address. </td></tr>
|
|
<tr><td class="paramname">handle</td><td>pointer to dspi_slave_handle_t structure which stores the transfer state. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
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