395 lines
16 KiB
ArmAsm
395 lines
16 KiB
ArmAsm
; * ---------------------------------------------------------------------------------------
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; * @file: startup_MKL03Z4.s
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; * @purpose: CMSIS Cortex-M0P Core Device Startup File
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; * MKL03Z4
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; * @version: 1.2
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; * @date: 2014-6-27
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; * @build: b151105
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; * ---------------------------------------------------------------------------------------
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; *
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; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
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; * All rights reserved.
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; *
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; * Redistribution and use in source and binary forms, with or without modification,
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; * are permitted provided that the following conditions are met:
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; *
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; * o Redistributions of source code must retain the above copyright notice, this list
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; * of conditions and the following disclaimer.
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; *
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; * o Redistributions in binary form must reproduce the above copyright notice, this
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; * list of conditions and the following disclaimer in the documentation and/or
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; * other materials provided with the distribution.
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; *
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; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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; * contributors may be used to endorse or promote products derived from this
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; * software without specific prior written permission.
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; *
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; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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; *
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ;NMI Handler
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DCD HardFault_Handler ;Hard Fault Handler
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD SVC_Handler ;SVCall Handler
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD PendSV_Handler ;PendSV Handler
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DCD SysTick_Handler ;SysTick Handler
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;External Interrupts
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DCD Reserved16_IRQHandler ;Reserved interrupt
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DCD Reserved17_IRQHandler ;Reserved interrupt
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DCD Reserved18_IRQHandler ;Reserved interrupt
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DCD Reserved19_IRQHandler ;Reserved interrupt
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DCD Reserved20_IRQHandler ;Reserved interrupt
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DCD FTFA_IRQHandler ;Command complete and read collision
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DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning
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DCD LLWU_IRQHandler ;Low leakage wakeup
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DCD I2C0_IRQHandler ;I2C0 interrupt
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DCD Reserved25_IRQHandler ;Reserved interrupt
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DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
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DCD Reserved27_IRQHandler ;Reserved interrupt
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DCD LPUART0_IRQHandler ;LPUART0 status and error
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DCD Reserved29_IRQHandler ;Reserved interrupt
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DCD Reserved30_IRQHandler ;Reserved interrupt
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DCD ADC0_IRQHandler ;ADC0 interrupt
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DCD CMP0_IRQHandler ;CMP0 interrupt
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DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
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DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
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DCD Reserved35_IRQHandler ;Reserved interrupt
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DCD RTC_IRQHandler ;RTC alarm
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DCD RTC_Seconds_IRQHandler ;RTC seconds
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DCD Reserved38_IRQHandler ;Reserved interrupt
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DCD Reserved39_IRQHandler ;Reserved interrupt
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DCD Reserved40_IRQHandler ;Reserved interrupt
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DCD Reserved41_IRQHandler ;Reserved interrupt
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DCD Reserved42_IRQHandler ;Reserved interrupt
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DCD Reserved43_IRQHandler ;Reserved interrupt
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DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
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DCD Reserved45_IRQHandler ;Reserved interrupt
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DCD PORTA_IRQHandler ;PORTA Pin detect
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DCD PORTB_IRQHandler ;PORTB Pin detect
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict access to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
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; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
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; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
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; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
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; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
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; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
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; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
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; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program Flash Region Protect Register 0
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT0
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
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; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
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; <o.1> BOOTPIN_OPT
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; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
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; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
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; <o.2> NMI_DIS
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; <0=> NMI interrupts are always blocked
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; <1=> NMI_b pin/interrupts reset default to enabled
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; <o.3> RESET_PIN_CFG
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; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
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; <1=> RESET_b pin is dedicated
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; <o.4> LPBOOT1
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
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; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
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; <o.5> FAST_INIT
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; <0=> Slower initialization
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; <1=> Fast Initialization
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; <o.6..7> BOOTSRC_SEL
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; <0=> Boot from Flash
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; <2=> Boot from ROM
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; <3=> Boot from ROM
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; <i> Boot source selection
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FOPT EQU 0x3D
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
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; <i> Flash Security
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; <o.2..3> FSLACC
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; <2=> Freescale factory access denied
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; <3=> Freescale factory access granted
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; <i> Freescale Failure Analysis Access Code
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; <o.4..5> MEEN
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; <2=> Mass erase is disabled
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; <3=> Mass erase is enabled
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; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
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; <i> Backdoor Key Security Enable
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FSEC EQU 0xFE
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; </h>
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA FlashConfig, DATA, READONLY
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__FlashConfig
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
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DCB FSEC , FOPT , 0xFF , 0xFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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IF :LNOT::DEF:RAM_TARGET
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REQUIRE FlashConfig
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ENDIF
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CPSID I ; Mask interrupts
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LDR R0, =0xE000ED08
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LDR R1, =__Vectors
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STR R1, [R0]
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LDR R0, =SystemInit
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BLX R0
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CPSIE i ; Unmask interrupts
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler\
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PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler\
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PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler\
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PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler\
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PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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I2C0_IRQHandler\
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PROC
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EXPORT I2C0_IRQHandler [WEAK]
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LDR R0, =I2C0_DriverIRQHandler
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BX R0
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ENDP
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SPI0_IRQHandler\
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PROC
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EXPORT SPI0_IRQHandler [WEAK]
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LDR R0, =SPI0_DriverIRQHandler
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BX R0
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ENDP
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LPUART0_IRQHandler\
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PROC
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EXPORT LPUART0_IRQHandler [WEAK]
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LDR R0, =LPUART0_DriverIRQHandler
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BX R0
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ENDP
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Default_Handler\
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PROC
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EXPORT Reserved16_IRQHandler [WEAK]
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EXPORT Reserved17_IRQHandler [WEAK]
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EXPORT Reserved18_IRQHandler [WEAK]
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EXPORT Reserved19_IRQHandler [WEAK]
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EXPORT Reserved20_IRQHandler [WEAK]
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EXPORT FTFA_IRQHandler [WEAK]
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EXPORT PMC_IRQHandler [WEAK]
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EXPORT LLWU_IRQHandler [WEAK]
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EXPORT I2C0_DriverIRQHandler [WEAK]
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EXPORT Reserved25_IRQHandler [WEAK]
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EXPORT SPI0_DriverIRQHandler [WEAK]
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EXPORT Reserved27_IRQHandler [WEAK]
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EXPORT LPUART0_DriverIRQHandler [WEAK]
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EXPORT Reserved29_IRQHandler [WEAK]
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EXPORT Reserved30_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT CMP0_IRQHandler [WEAK]
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EXPORT TPM0_IRQHandler [WEAK]
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EXPORT TPM1_IRQHandler [WEAK]
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EXPORT Reserved35_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT RTC_Seconds_IRQHandler [WEAK]
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EXPORT Reserved38_IRQHandler [WEAK]
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EXPORT Reserved39_IRQHandler [WEAK]
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EXPORT Reserved40_IRQHandler [WEAK]
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EXPORT Reserved41_IRQHandler [WEAK]
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EXPORT Reserved42_IRQHandler [WEAK]
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EXPORT Reserved43_IRQHandler [WEAK]
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EXPORT LPTMR0_IRQHandler [WEAK]
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EXPORT Reserved45_IRQHandler [WEAK]
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EXPORT PORTA_IRQHandler [WEAK]
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EXPORT PORTB_IRQHandler [WEAK]
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EXPORT DefaultISR [WEAK]
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Reserved16_IRQHandler
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Reserved17_IRQHandler
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Reserved18_IRQHandler
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Reserved19_IRQHandler
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Reserved20_IRQHandler
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FTFA_IRQHandler
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PMC_IRQHandler
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LLWU_IRQHandler
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I2C0_DriverIRQHandler
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Reserved25_IRQHandler
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SPI0_DriverIRQHandler
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Reserved27_IRQHandler
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LPUART0_DriverIRQHandler
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Reserved29_IRQHandler
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Reserved30_IRQHandler
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ADC0_IRQHandler
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CMP0_IRQHandler
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TPM0_IRQHandler
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TPM1_IRQHandler
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Reserved35_IRQHandler
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RTC_IRQHandler
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RTC_Seconds_IRQHandler
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Reserved38_IRQHandler
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Reserved39_IRQHandler
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Reserved40_IRQHandler
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Reserved41_IRQHandler
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Reserved42_IRQHandler
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Reserved43_IRQHandler
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LPTMR0_IRQHandler
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Reserved45_IRQHandler
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PORTA_IRQHandler
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PORTB_IRQHandler
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DefaultISR
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LDR R0, =DefaultISR
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BX R0
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ENDP
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ALIGN
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END
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