951 lines
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951 lines
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<a href="#enum-members">Enumerations</a> </div>
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<div class="headertitle">
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<div class="title">SDRAMC: Synchronous DRAM Controller Driver</div> </div>
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</div><!--header-->
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<div class="contents">
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
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<p>The KSDK provides a peripheral driver for the Synchronous DRAM Controller block of Kinetis devices.</p>
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<p>The SDRAM controller commands include the initialize MRS command, precharge command, enter/exit self-refresh command, and enable/disable auto-refresh command. Use the <a class="el" href="group__sdramc.html#ga50a3326a3324ec23921b55a83788d629" title="Sends the SDRAM command. ">SDRAMC_SendCommand()</a> to send these commands to SDRAM to initialize it. The <a class="el" href="group__sdramc.html#ga5299b643d34f8b98d656aedb05481a27" title="Enables/disables the write protection. ">SDRAMC_EnableWriteProtect()</a> is provided to enable/disable the write protection. The <a class="el" href="group__sdramc.html#ga38496a12d54ef805a5802b00617db261" title="Enables/disables the operation valid. ">SDRAMC_EnableOperateValid()</a> is provided to enable/disable the operation valid.</p>
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<h1><a class="anchor" id="SDRAMCTpyUC"></a>
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Typical use case</h1>
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<p>This example shows how to use the SDRAM Controller driver to initialize the external 16 bit port-size 8-column SDRAM chip. Initialize the SDRAM controller and run the initialization sequence. The external SDRAM is initialized and the SDRAM read and write is available.</p>
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<p>First, initialize the SDRAM Controller. </p>
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<div class="fragment"><div class="line"><a class="code" href="group__sdramc.html#structsdramc__config__t">sdramc_config_t</a> config;</div>
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<div class="line">uint32_t clockSrc;</div>
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<div class="line"></div>
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<div class="line"><span class="comment">// SDRAM refresh timing configuration.</span></div>
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<div class="line">clockSrc = <a class="code" href="group__mcglite.html#ga53acae220d651789bb505c53c73ecf2b">CLOCK_GetFreq</a>(<a class="code" href="group__mcglite.html#ggaf74854e9bcee544d7646c5bafdc00bd3a5d1ee238337b6aa2486a42feabdd5133">kCLOCK_BusClk</a>);</div>
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<div class="line"><a class="code" href="group__sdramc.html#structsdramc__refresh__config__t">sdramc_refresh_config_t</a> refConfig =</div>
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<div class="line">{</div>
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<div class="line"> <a class="code" href="group__sdramc.html#gga60386afe3f3f702f02a990626df913e1af23bd012b4da435853cb10e9af855b47">kSDRAMC_RefreshThreeClocks</a>,</div>
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<div class="line"> 15625, <span class="comment">// SDRAM: 4096 rows/ 64ms.</span></div>
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<div class="line"> clockSrc,</div>
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<div class="line">};</div>
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<div class="line"><span class="comment">// SDRAM controller configuration.</span></div>
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<div class="line"><a class="code" href="group__sdramc.html#structsdramc__blockctl__config__t">sdramc_blockctl_config_t</a> ctlConfig =</div>
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<div class="line">{</div>
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<div class="line"> <a class="code" href="group__sdramc.html#gga9eb1e63a96bbd0b8c04c77dbc1221a38a554d56a199529755bed2e67bab27fe0c">kSDRAMC_Block0</a>,</div>
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<div class="line"> <a class="code" href="group__sdramc.html#gga80927a542163775f51782964391d9774a9031089fca5f2e885506d3241c827479">kSDRAMC_PortSize16Bit</a>,</div>
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<div class="line"> <a class="code" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62ca3a28222a7225a079c6a68acaaaf7b824">kSDRAMC_Commandbit19</a>,</div>
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<div class="line"> <a class="code" href="group__sdramc.html#ggafb945fc0cf4edc1735242c5dd0724ae9a9a31b288eb5d0c9ad4bf676272baf263">kSDRAMC_LatencyOne</a>,</div>
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<div class="line"> SDRAM_START_ADDRESS,</div>
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<div class="line"> 0x7c0000,</div>
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<div class="line">};</div>
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<div class="line"></div>
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<div class="line">config.<a class="code" href="group__sdramc.html#ab3be5ccfa2f6a0f86bc82545fe3a2af5">refreshConfig</a> = &refConfig;</div>
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<div class="line">config.<a class="code" href="group__sdramc.html#af027f5cd8e842233c8ccd2f256be8d42">blockConfig</a> = &ctlConfig;</div>
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<div class="line">config.<a class="code" href="group__sdramc.html#a4455ff23450c2be6c5ae2647cacdb095">numBlockConfig</a> = 1;</div>
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<div class="line"></div>
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<div class="line"><span class="comment">// SDRAM controller initialization.</span></div>
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<div class="line"><a class="code" href="group__sdramc.html#ga1507ca3630a0e845eeea249712e00667">SDRAMC_Init</a>(base, &config);</div>
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</div><!-- fragment --><p>Then, run the initialization sequence.</p>
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<div class="fragment"><div class="line"><span class="comment">// Issues a PALL command.</span></div>
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<div class="line"><a class="code" href="group__sdramc.html#ga50a3326a3324ec23921b55a83788d629">SDRAMC_SendCommand</a>(base, whichBlock, <a class="code" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410a265cb88f41d8d1ffcd9d711a13c86dc9">kSDRAMC_PrechargeCommand</a>);</div>
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<div class="line"></div>
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<div class="line"><span class="comment">// Accesses an SDRAM location.</span></div>
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<div class="line"> (uint8_t *)(SDRAM_START_ADDRESS) = SDRAM_COMMAND_ACCESSVALUE;</div>
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<div class="line"></div>
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<div class="line"><span class="comment">// Enables the refresh.</span></div>
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<div class="line"><a class="code" href="group__sdramc.html#ga50a3326a3324ec23921b55a83788d629">SDRAMC_SendCommand</a>(base, whichBlock, <a class="code" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410a32915b269abd30cd8d977870a4c468aa">kSDRAMC_AutoRefreshEnableCommand</a>);</div>
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<div class="line"></div>
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<div class="line"><span class="comment">// Waits for 8 refresh cycles less than one microsecond.</span></div>
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<div class="line">delay;</div>
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<div class="line"></div>
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<div class="line"><span class="comment">// Issues the MSR command.</span></div>
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<div class="line"><a class="code" href="group__sdramc.html#ga50a3326a3324ec23921b55a83788d629">SDRAMC_SendCommand</a>(base, whichBlock, <a class="code" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410a83b7ead8cb88d656d9560002e73337f1">kSDRAMC_ImrsCommand</a>);</div>
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<div class="line"></div>
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<div class="line"><span class="comment">// Puts the correct value on the SDRAM address bus for the SDRAM mode register.</span></div>
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<div class="line">addr = ....;</div>
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<div class="line"></div>
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<div class="line"><span class="comment">// Set MRS register.</span></div>
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<div class="line">mrsAddr = (uint8_t *)(SDRAM_START_ADDRESS + addr);</div>
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<div class="line"> mrsAddr = SDRAM_COMMAND_ACCESSVALUE;</div>
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</div><!-- fragment --> <table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="files"></a>
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Files</h2></td></tr>
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<tr class="memitem:fsl__sdramc_8h"><td class="memItemLeft" align="right" valign="top">file  </td><td class="memItemRight" valign="bottom"><a class="el" href="fsl__sdramc_8h.html">fsl_sdramc.h</a></td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
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Data Structures</h2></td></tr>
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<tr class="memitem:structsdramc__blockctl__config__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#structsdramc__blockctl__config__t">sdramc_blockctl_config_t</a></td></tr>
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<tr class="memdesc:structsdramc__blockctl__config__t"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM controller block control configuration structure. <a href="group__sdramc.html#structsdramc__blockctl__config__t">More...</a><br/></td></tr>
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<tr class="separator:structsdramc__blockctl__config__t"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structsdramc__refresh__config__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#structsdramc__refresh__config__t">sdramc_refresh_config_t</a></td></tr>
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<tr class="memdesc:structsdramc__refresh__config__t"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM controller refresh timing configuration structure. <a href="group__sdramc.html#structsdramc__refresh__config__t">More...</a><br/></td></tr>
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<tr class="separator:structsdramc__refresh__config__t"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structsdramc__config__t"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#structsdramc__config__t">sdramc_config_t</a></td></tr>
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<tr class="memdesc:structsdramc__config__t"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM controller configuration structure. <a href="group__sdramc.html#structsdramc__config__t">More...</a><br/></td></tr>
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<tr class="separator:structsdramc__config__t"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
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Enumerations</h2></td></tr>
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<tr class="memitem:ga60386afe3f3f702f02a990626df913e1"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga60386afe3f3f702f02a990626df913e1">sdramc_refresh_time_t</a> { <br/>
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  <a class="el" href="group__sdramc.html#gga60386afe3f3f702f02a990626df913e1af23bd012b4da435853cb10e9af855b47">kSDRAMC_RefreshThreeClocks</a> = 0x0U,
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<br/>
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  <a class="el" href="group__sdramc.html#gga60386afe3f3f702f02a990626df913e1a3537c844cc50fc534bb965f750b67af9">kSDRAMC_RefreshSixClocks</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga60386afe3f3f702f02a990626df913e1affe38236605f745e97589d42c2998fec">kSDRAMC_RefreshNineClocks</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga60386afe3f3f702f02a990626df913e1"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM controller auto-refresh timing. <a href="group__sdramc.html#ga60386afe3f3f702f02a990626df913e1">More...</a><br/></td></tr>
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<tr class="separator:ga60386afe3f3f702f02a990626df913e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb945fc0cf4edc1735242c5dd0724ae9"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#gafb945fc0cf4edc1735242c5dd0724ae9">sdramc_latency_t</a> { <br/>
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  <a class="el" href="group__sdramc.html#ggafb945fc0cf4edc1735242c5dd0724ae9a509101cf1372c3b3acd0e44f5d70dae9">kSDRAMC_LatencyZero</a> = 0x0U,
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<br/>
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  <a class="el" href="group__sdramc.html#ggafb945fc0cf4edc1735242c5dd0724ae9a9a31b288eb5d0c9ad4bf676272baf263">kSDRAMC_LatencyOne</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#ggafb945fc0cf4edc1735242c5dd0724ae9ad46037aae023a3c0d289d530f4147582">kSDRAMC_LatencyTwo</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#ggafb945fc0cf4edc1735242c5dd0724ae9aaf6bffe284f801e8825650e25372440a">kSDRAMC_LatencyThree</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:gafb945fc0cf4edc1735242c5dd0724ae9"><td class="mdescLeft"> </td><td class="mdescRight">Setting latency for SDRAM controller timing specifications. <a href="group__sdramc.html#gafb945fc0cf4edc1735242c5dd0724ae9">More...</a><br/></td></tr>
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<tr class="separator:gafb945fc0cf4edc1735242c5dd0724ae9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga277ebf8d251aac6eab5f5c42ac3fc62c"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga277ebf8d251aac6eab5f5c42ac3fc62c">sdramc_command_bit_location_t</a> { <br/>
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  <a class="el" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62caa1f02ffa89fd71e65cb1b8d93f024321">kSDRAMC_Commandbit17</a> = 0x0U,
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<br/>
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  <a class="el" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62cac9626db0f578cbc458d88efa3aca408d">kSDRAMC_Commandbit18</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62ca3a28222a7225a079c6a68acaaaf7b824">kSDRAMC_Commandbit19</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62ca187784b6b1c3187d1a98e889190ddc72">kSDRAMC_Commandbit20</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62ca01cf89687fed60650285baae6bd84d86">kSDRAMC_Commandbit21</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62ca3e46ee2f9754e4ce91bade45814e2bb2">kSDRAMC_Commandbit22</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62ca0898bebf5d86219a2a5a50c0516611c8">kSDRAMC_Commandbit23</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62ca6377116dae563d047642e38d969bd0ba">kSDRAMC_Commandbit24</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga277ebf8d251aac6eab5f5c42ac3fc62c"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM controller command bit location. <a href="group__sdramc.html#ga277ebf8d251aac6eab5f5c42ac3fc62c">More...</a><br/></td></tr>
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<tr class="separator:ga277ebf8d251aac6eab5f5c42ac3fc62c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga050eba54b4afc87d1b6db93cdc873410"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga050eba54b4afc87d1b6db93cdc873410">sdramc_command_t</a> { <br/>
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  <a class="el" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410a83b7ead8cb88d656d9560002e73337f1">kSDRAMC_ImrsCommand</a> = 0x0U,
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<br/>
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  <a class="el" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410a265cb88f41d8d1ffcd9d711a13c86dc9">kSDRAMC_PrechargeCommand</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410a1209e4378f6ee807fb3ce8a84249a869">kSDRAMC_SelfrefreshEnterCommand</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410a07d5f11028dabd2cb13a95d2ae9439fa">kSDRAMC_SelfrefreshExitCommand</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410a32915b269abd30cd8d977870a4c468aa">kSDRAMC_AutoRefreshEnableCommand</a>,
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<br/>
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  <a class="el" href="group__sdramc.html#gga050eba54b4afc87d1b6db93cdc873410adb1b58e25ce88a85633ec6c758638ef5">kSDRAMC_AutoRefreshDisableCommand</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga050eba54b4afc87d1b6db93cdc873410"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM controller command. <a href="group__sdramc.html#ga050eba54b4afc87d1b6db93cdc873410">More...</a><br/></td></tr>
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<tr class="separator:ga050eba54b4afc87d1b6db93cdc873410"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80927a542163775f51782964391d9774"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga80927a542163775f51782964391d9774">sdramc_port_size_t</a> { <br/>
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  <a class="el" href="group__sdramc.html#gga80927a542163775f51782964391d9774a9e3c35908943baa76841f86e093cd37b">kSDRAMC_PortSize32Bit</a> = 0x0U,
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  <a class="el" href="group__sdramc.html#gga80927a542163775f51782964391d9774a563462b471bacb3b5c35dbeec7b72f5f">kSDRAMC_PortSize8Bit</a>,
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  <a class="el" href="group__sdramc.html#gga80927a542163775f51782964391d9774a9031089fca5f2e885506d3241c827479">kSDRAMC_PortSize16Bit</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga80927a542163775f51782964391d9774"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM port size. <a href="group__sdramc.html#ga80927a542163775f51782964391d9774">More...</a><br/></td></tr>
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<tr class="separator:ga80927a542163775f51782964391d9774"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9eb1e63a96bbd0b8c04c77dbc1221a38"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> { <br/>
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  <a class="el" href="group__sdramc.html#gga9eb1e63a96bbd0b8c04c77dbc1221a38a554d56a199529755bed2e67bab27fe0c">kSDRAMC_Block0</a> = 0x0U,
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  <a class="el" href="group__sdramc.html#gga9eb1e63a96bbd0b8c04c77dbc1221a38aac169b7b72c468b2429ce68ddac27d5a">kSDRAMC_Block1</a>
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}</td></tr>
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<tr class="memdesc:ga9eb1e63a96bbd0b8c04c77dbc1221a38"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM controller block selection. <a href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">More...</a><br/></td></tr>
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<tr class="separator:ga9eb1e63a96bbd0b8c04c77dbc1221a38"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Driver version</h2></td></tr>
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<tr class="memitem:gae7beb4b84c2ad29a34bc56ad2496981e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#gae7beb4b84c2ad29a34bc56ad2496981e">FSL_SDRAMC_DRIVER_VERSION</a>   (<a class="el" href="group__flash__driver.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 0, 0))</td></tr>
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<tr class="memdesc:gae7beb4b84c2ad29a34bc56ad2496981e"><td class="mdescLeft"> </td><td class="mdescRight">SDRAMC driver version 2.0.0. <a href="#gae7beb4b84c2ad29a34bc56ad2496981e">More...</a><br/></td></tr>
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<tr class="separator:gae7beb4b84c2ad29a34bc56ad2496981e"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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SDRAM Controller Initialization and De-initialization</h2></td></tr>
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<tr class="memitem:ga1507ca3630a0e845eeea249712e00667"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga1507ca3630a0e845eeea249712e00667">SDRAMC_Init</a> (SDRAM_Type *base, <a class="el" href="group__sdramc.html#structsdramc__config__t">sdramc_config_t</a> *configure)</td></tr>
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<tr class="memdesc:ga1507ca3630a0e845eeea249712e00667"><td class="mdescLeft"> </td><td class="mdescRight">Initializes the SDRAM controller. <a href="#ga1507ca3630a0e845eeea249712e00667">More...</a><br/></td></tr>
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<tr class="separator:ga1507ca3630a0e845eeea249712e00667"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43aadfcec0591fdcc5de2e3190b3bb0d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga43aadfcec0591fdcc5de2e3190b3bb0d">SDRAMC_Deinit</a> (SDRAM_Type *base)</td></tr>
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<tr class="memdesc:ga43aadfcec0591fdcc5de2e3190b3bb0d"><td class="mdescLeft"> </td><td class="mdescRight">Deinitializes the SDRAM controller module and gates the clock. <a href="#ga43aadfcec0591fdcc5de2e3190b3bb0d">More...</a><br/></td></tr>
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<tr class="separator:ga43aadfcec0591fdcc5de2e3190b3bb0d"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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SDRAM Controller Basic Operation</h2></td></tr>
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<tr class="memitem:ga50a3326a3324ec23921b55a83788d629"><td class="memItemLeft" align="right" valign="top">status_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga50a3326a3324ec23921b55a83788d629">SDRAMC_SendCommand</a> (SDRAM_Type *base, <a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> block, <a class="el" href="group__sdramc.html#ga050eba54b4afc87d1b6db93cdc873410">sdramc_command_t</a> command)</td></tr>
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<tr class="memdesc:ga50a3326a3324ec23921b55a83788d629"><td class="mdescLeft"> </td><td class="mdescRight">Sends the SDRAM command. <a href="#ga50a3326a3324ec23921b55a83788d629">More...</a><br/></td></tr>
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<tr class="separator:ga50a3326a3324ec23921b55a83788d629"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5299b643d34f8b98d656aedb05481a27"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga5299b643d34f8b98d656aedb05481a27">SDRAMC_EnableWriteProtect</a> (SDRAM_Type *base, <a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> block, bool enable)</td></tr>
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<tr class="memdesc:ga5299b643d34f8b98d656aedb05481a27"><td class="mdescLeft"> </td><td class="mdescRight">Enables/disables the write protection. <a href="#ga5299b643d34f8b98d656aedb05481a27">More...</a><br/></td></tr>
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<tr class="separator:ga5299b643d34f8b98d656aedb05481a27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga38496a12d54ef805a5802b00617db261"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ga38496a12d54ef805a5802b00617db261">SDRAMC_EnableOperateValid</a> (SDRAM_Type *base, <a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> block, bool enable)</td></tr>
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<tr class="memdesc:ga38496a12d54ef805a5802b00617db261"><td class="mdescLeft"> </td><td class="mdescRight">Enables/disables the operation valid. <a href="#ga38496a12d54ef805a5802b00617db261">More...</a><br/></td></tr>
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<tr class="separator:ga38496a12d54ef805a5802b00617db261"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<hr/><h2 class="groupheader">Data Structure Documentation</h2>
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<a name="structsdramc__blockctl__config__t" id="structsdramc__blockctl__config__t"></a>
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<div class="memitem">
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<td class="memname">struct sdramc_blockctl_config_t</td>
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<div class="textblock"></div><table class="memberdecls">
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:a74761b33f800579c3a20ca9c78f357c7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#a74761b33f800579c3a20ca9c78f357c7">block</a></td></tr>
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<tr class="memdesc:a74761b33f800579c3a20ca9c78f357c7"><td class="mdescLeft"> </td><td class="mdescRight">The block number. <a href="#a74761b33f800579c3a20ca9c78f357c7">More...</a><br/></td></tr>
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<tr class="separator:a74761b33f800579c3a20ca9c78f357c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a34869df7f62ea5db5a9a7d38f7eadf87"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sdramc.html#ga80927a542163775f51782964391d9774">sdramc_port_size_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#a34869df7f62ea5db5a9a7d38f7eadf87">portSize</a></td></tr>
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<tr class="memdesc:a34869df7f62ea5db5a9a7d38f7eadf87"><td class="mdescLeft"> </td><td class="mdescRight">The port size of the associated SDRAM block. <a href="#a34869df7f62ea5db5a9a7d38f7eadf87">More...</a><br/></td></tr>
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<tr class="separator:a34869df7f62ea5db5a9a7d38f7eadf87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb47879cacae9b6ecdccee03c734da4b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sdramc.html#ga277ebf8d251aac6eab5f5c42ac3fc62c">sdramc_command_bit_location_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#adb47879cacae9b6ecdccee03c734da4b">location</a></td></tr>
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<tr class="memdesc:adb47879cacae9b6ecdccee03c734da4b"><td class="mdescLeft"> </td><td class="mdescRight">The command bit location. <a href="#adb47879cacae9b6ecdccee03c734da4b">More...</a><br/></td></tr>
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<tr class="separator:adb47879cacae9b6ecdccee03c734da4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afc3c673532c14837867d7cabecd97b03"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sdramc.html#gafb945fc0cf4edc1735242c5dd0724ae9">sdramc_latency_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#afc3c673532c14837867d7cabecd97b03">latency</a></td></tr>
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<tr class="memdesc:afc3c673532c14837867d7cabecd97b03"><td class="mdescLeft"> </td><td class="mdescRight">The latency for some timing specifications. <a href="#afc3c673532c14837867d7cabecd97b03">More...</a><br/></td></tr>
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<tr class="separator:afc3c673532c14837867d7cabecd97b03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a295fb68fb342f8a9696de1ac1a4fd67d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#a295fb68fb342f8a9696de1ac1a4fd67d">address</a></td></tr>
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<tr class="memdesc:a295fb68fb342f8a9696de1ac1a4fd67d"><td class="mdescLeft"> </td><td class="mdescRight">The base address of the SDRAM block. <a href="#a295fb68fb342f8a9696de1ac1a4fd67d">More...</a><br/></td></tr>
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<tr class="separator:a295fb68fb342f8a9696de1ac1a4fd67d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad8d57f01dc537eade6ee05aa05d25e8c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ad8d57f01dc537eade6ee05aa05d25e8c">addressMask</a></td></tr>
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<tr class="memdesc:ad8d57f01dc537eade6ee05aa05d25e8c"><td class="mdescLeft"> </td><td class="mdescRight">The base address mask of the SDRAM block. <a href="#ad8d57f01dc537eade6ee05aa05d25e8c">More...</a><br/></td></tr>
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<h4 class="groupheader">Field Documentation</h4>
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<a class="anchor" id="a74761b33f800579c3a20ca9c78f357c7"></a>
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<td class="memname"><a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> sdramc_blockctl_config_t::block</td>
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<a class="anchor" id="a34869df7f62ea5db5a9a7d38f7eadf87"></a>
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<td class="memname"><a class="el" href="group__sdramc.html#ga80927a542163775f51782964391d9774">sdramc_port_size_t</a> sdramc_blockctl_config_t::portSize</td>
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<a class="anchor" id="adb47879cacae9b6ecdccee03c734da4b"></a>
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<td class="memname"><a class="el" href="group__sdramc.html#ga277ebf8d251aac6eab5f5c42ac3fc62c">sdramc_command_bit_location_t</a> sdramc_blockctl_config_t::location</td>
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<a class="anchor" id="afc3c673532c14837867d7cabecd97b03"></a>
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<td class="memname"><a class="el" href="group__sdramc.html#gafb945fc0cf4edc1735242c5dd0724ae9">sdramc_latency_t</a> sdramc_blockctl_config_t::latency</td>
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<a class="anchor" id="a295fb68fb342f8a9696de1ac1a4fd67d"></a>
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<td class="memname">uint32_t sdramc_blockctl_config_t::address</td>
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<a class="anchor" id="ad8d57f01dc537eade6ee05aa05d25e8c"></a>
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<td class="memname">uint32_t sdramc_blockctl_config_t::addressMask</td>
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<a name="structsdramc__refresh__config__t" id="structsdramc__refresh__config__t"></a>
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<td class="memname">struct sdramc_refresh_config_t</td>
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<div class="textblock"></div><table class="memberdecls">
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:ad290e97c817b4d52c220417228429902"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sdramc.html#ga60386afe3f3f702f02a990626df913e1">sdramc_refresh_time_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ad290e97c817b4d52c220417228429902">refreshTime</a></td></tr>
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<tr class="memdesc:ad290e97c817b4d52c220417228429902"><td class="mdescLeft"> </td><td class="mdescRight">Trc:The number of bus clocks inserted between a REF and next ACTIVE command. <a href="#ad290e97c817b4d52c220417228429902">More...</a><br/></td></tr>
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<tr class="separator:ad290e97c817b4d52c220417228429902"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acf4832db4f72003ead0936eb1fa553b6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#acf4832db4f72003ead0936eb1fa553b6">sdramRefreshRow</a></td></tr>
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<tr class="memdesc:acf4832db4f72003ead0936eb1fa553b6"><td class="mdescLeft"> </td><td class="mdescRight">The SDRAM refresh time each row: ns/row. <a href="#acf4832db4f72003ead0936eb1fa553b6">More...</a><br/></td></tr>
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<tr class="separator:acf4832db4f72003ead0936eb1fa553b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a80a5ac19a70c2b66c78ebcc9f99623de"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#a80a5ac19a70c2b66c78ebcc9f99623de">busClock_Hz</a></td></tr>
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<tr class="memdesc:a80a5ac19a70c2b66c78ebcc9f99623de"><td class="mdescLeft"> </td><td class="mdescRight">The bus clock for SDRAMC. <a href="#a80a5ac19a70c2b66c78ebcc9f99623de">More...</a><br/></td></tr>
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</table>
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<h4 class="groupheader">Field Documentation</h4>
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<td class="memname"><a class="el" href="group__sdramc.html#ga60386afe3f3f702f02a990626df913e1">sdramc_refresh_time_t</a> sdramc_refresh_config_t::refreshTime</td>
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<td class="memname">uint32_t sdramc_refresh_config_t::sdramRefreshRow</td>
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<td class="memname">uint32_t sdramc_refresh_config_t::busClock_Hz</td>
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<a name="structsdramc__config__t" id="structsdramc__config__t"></a>
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<td class="memname">struct sdramc_config_t</td>
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<div class="textblock"><p>Defines a configure structure and uses the SDRAMC_Configure() function to make necessary initializations. </p>
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</div><table class="memberdecls">
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<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
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<tr class="memitem:ab3be5ccfa2f6a0f86bc82545fe3a2af5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sdramc.html#structsdramc__refresh__config__t">sdramc_refresh_config_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#ab3be5ccfa2f6a0f86bc82545fe3a2af5">refreshConfig</a></td></tr>
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<tr class="memdesc:ab3be5ccfa2f6a0f86bc82545fe3a2af5"><td class="mdescLeft"> </td><td class="mdescRight">Refresh timing configure structure pointer. <a href="#ab3be5ccfa2f6a0f86bc82545fe3a2af5">More...</a><br/></td></tr>
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<tr class="separator:ab3be5ccfa2f6a0f86bc82545fe3a2af5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af027f5cd8e842233c8ccd2f256be8d42"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sdramc.html#structsdramc__blockctl__config__t">sdramc_blockctl_config_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#af027f5cd8e842233c8ccd2f256be8d42">blockConfig</a></td></tr>
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<tr class="memdesc:af027f5cd8e842233c8ccd2f256be8d42"><td class="mdescLeft"> </td><td class="mdescRight">Block configure structure pointer. <a href="#af027f5cd8e842233c8ccd2f256be8d42">More...</a><br/></td></tr>
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<tr class="separator:af027f5cd8e842233c8ccd2f256be8d42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4455ff23450c2be6c5ae2647cacdb095"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sdramc.html#a4455ff23450c2be6c5ae2647cacdb095">numBlockConfig</a></td></tr>
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<tr class="memdesc:a4455ff23450c2be6c5ae2647cacdb095"><td class="mdescLeft"> </td><td class="mdescRight">SDRAM block numbers for configuration. <a href="#a4455ff23450c2be6c5ae2647cacdb095">More...</a><br/></td></tr>
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<tr class="separator:a4455ff23450c2be6c5ae2647cacdb095"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<h4 class="groupheader">Field Documentation</h4>
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<a class="anchor" id="ab3be5ccfa2f6a0f86bc82545fe3a2af5"></a>
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<td class="memname"><a class="el" href="group__sdramc.html#structsdramc__refresh__config__t">sdramc_refresh_config_t</a>* sdramc_config_t::refreshConfig</td>
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<td class="memname"><a class="el" href="group__sdramc.html#structsdramc__blockctl__config__t">sdramc_blockctl_config_t</a>* sdramc_config_t::blockConfig</td>
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<p>If both SDRAM blocks are used, use the two continuous blockConfig. </p>
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<td class="memname">uint8_t sdramc_config_t::numBlockConfig</td>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define FSL_SDRAMC_DRIVER_VERSION   (<a class="el" href="group__flash__driver.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 0, 0))</td>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<a class="anchor" id="ga60386afe3f3f702f02a990626df913e1"></a>
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<td class="memname">enum <a class="el" href="group__sdramc.html#ga60386afe3f3f702f02a990626df913e1">sdramc_refresh_time_t</a></td>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga60386afe3f3f702f02a990626df913e1af23bd012b4da435853cb10e9af855b47"></a>kSDRAMC_RefreshThreeClocks</em> </td><td class="fielddoc">
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<p>The refresh timing with three bus clocks. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga60386afe3f3f702f02a990626df913e1a3537c844cc50fc534bb965f750b67af9"></a>kSDRAMC_RefreshSixClocks</em> </td><td class="fielddoc">
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<p>The refresh timing with six bus clocks. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga60386afe3f3f702f02a990626df913e1affe38236605f745e97589d42c2998fec"></a>kSDRAMC_RefreshNineClocks</em> </td><td class="fielddoc">
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<p>The refresh timing with nine bus clocks. </p>
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<td class="memname">enum <a class="el" href="group__sdramc.html#gafb945fc0cf4edc1735242c5dd0724ae9">sdramc_latency_t</a></td>
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<p>The latency setting will affects the following SDRAM timing specifications:</p>
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<ul>
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<li>trcd: SRAS assertion to SCAS assertion <br/>
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</li>
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<li>tcasl: SCAS assertion to data out <br/>
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</li>
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<li>tras: ACTV command to Precharge command <br/>
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</li>
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<li>trp: Precharge command to ACTV command <br/>
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</li>
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<li>trwl, trdl: Last data input to Precharge command <br/>
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</li>
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<li>tep: Last data out to Precharge command <br/>
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the details of the latency setting and timing specifications are shown on the following table list: <br/>
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latency trcd: tcasl tras trp trwl,trdl tep <br/>
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0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock <br/>
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1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock <br/>
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2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock <br/>
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3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock <br/>
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</li>
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</ul>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggafb945fc0cf4edc1735242c5dd0724ae9a509101cf1372c3b3acd0e44f5d70dae9"></a>kSDRAMC_LatencyZero</em> </td><td class="fielddoc">
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<p>Latency 0. </p>
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<tr><td class="fieldname"><em><a class="anchor" id="ggafb945fc0cf4edc1735242c5dd0724ae9a9a31b288eb5d0c9ad4bf676272baf263"></a>kSDRAMC_LatencyOne</em> </td><td class="fielddoc">
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<p>Latency 1. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggafb945fc0cf4edc1735242c5dd0724ae9ad46037aae023a3c0d289d530f4147582"></a>kSDRAMC_LatencyTwo</em> </td><td class="fielddoc">
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<p>Latency 2. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="ggafb945fc0cf4edc1735242c5dd0724ae9aaf6bffe284f801e8825650e25372440a"></a>kSDRAMC_LatencyThree</em> </td><td class="fielddoc">
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<p>Latency 3. </p>
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<td class="memname">enum <a class="el" href="group__sdramc.html#ga277ebf8d251aac6eab5f5c42ac3fc62c">sdramc_command_bit_location_t</a></td>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga277ebf8d251aac6eab5f5c42ac3fc62caa1f02ffa89fd71e65cb1b8d93f024321"></a>kSDRAMC_Commandbit17</em> </td><td class="fielddoc">
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<p>Command bit location is bit 17. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga277ebf8d251aac6eab5f5c42ac3fc62cac9626db0f578cbc458d88efa3aca408d"></a>kSDRAMC_Commandbit18</em> </td><td class="fielddoc">
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<p>Command bit location is bit 18. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga277ebf8d251aac6eab5f5c42ac3fc62ca3a28222a7225a079c6a68acaaaf7b824"></a>kSDRAMC_Commandbit19</em> </td><td class="fielddoc">
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<p>Command bit location is bit 19. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga277ebf8d251aac6eab5f5c42ac3fc62ca187784b6b1c3187d1a98e889190ddc72"></a>kSDRAMC_Commandbit20</em> </td><td class="fielddoc">
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<p>Command bit location is bit 20. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga277ebf8d251aac6eab5f5c42ac3fc62ca01cf89687fed60650285baae6bd84d86"></a>kSDRAMC_Commandbit21</em> </td><td class="fielddoc">
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<p>Command bit location is bit 21. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga277ebf8d251aac6eab5f5c42ac3fc62ca3e46ee2f9754e4ce91bade45814e2bb2"></a>kSDRAMC_Commandbit22</em> </td><td class="fielddoc">
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<p>Command bit location is bit 22. </p>
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<tr><td class="fieldname"><em><a class="anchor" id="gga277ebf8d251aac6eab5f5c42ac3fc62ca0898bebf5d86219a2a5a50c0516611c8"></a>kSDRAMC_Commandbit23</em> </td><td class="fielddoc">
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<p>Command bit location is bit 23. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga277ebf8d251aac6eab5f5c42ac3fc62ca6377116dae563d047642e38d969bd0ba"></a>kSDRAMC_Commandbit24</em> </td><td class="fielddoc">
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<p>Command bit location is bit 24. </p>
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</table>
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<td class="memname">enum <a class="el" href="group__sdramc.html#ga050eba54b4afc87d1b6db93cdc873410">sdramc_command_t</a></td>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga050eba54b4afc87d1b6db93cdc873410a83b7ead8cb88d656d9560002e73337f1"></a>kSDRAMC_ImrsCommand</em> </td><td class="fielddoc">
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<p>Initiate MRS command. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga050eba54b4afc87d1b6db93cdc873410a265cb88f41d8d1ffcd9d711a13c86dc9"></a>kSDRAMC_PrechargeCommand</em> </td><td class="fielddoc">
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<p>Initiate precharge command. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga050eba54b4afc87d1b6db93cdc873410a1209e4378f6ee807fb3ce8a84249a869"></a>kSDRAMC_SelfrefreshEnterCommand</em> </td><td class="fielddoc">
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<p>Enter self-refresh command. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga050eba54b4afc87d1b6db93cdc873410a07d5f11028dabd2cb13a95d2ae9439fa"></a>kSDRAMC_SelfrefreshExitCommand</em> </td><td class="fielddoc">
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<p>Exit self-refresh command. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga050eba54b4afc87d1b6db93cdc873410a32915b269abd30cd8d977870a4c468aa"></a>kSDRAMC_AutoRefreshEnableCommand</em> </td><td class="fielddoc">
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<p>Enable Auto refresh command. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga050eba54b4afc87d1b6db93cdc873410adb1b58e25ce88a85633ec6c758638ef5"></a>kSDRAMC_AutoRefreshDisableCommand</em> </td><td class="fielddoc">
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<p>Disable Auto refresh command. </p>
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<td class="memname">enum <a class="el" href="group__sdramc.html#ga80927a542163775f51782964391d9774">sdramc_port_size_t</a></td>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga80927a542163775f51782964391d9774a9e3c35908943baa76841f86e093cd37b"></a>kSDRAMC_PortSize32Bit</em> </td><td class="fielddoc">
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<p>32-Bit port size. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga80927a542163775f51782964391d9774a563462b471bacb3b5c35dbeec7b72f5f"></a>kSDRAMC_PortSize8Bit</em> </td><td class="fielddoc">
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<p>8-Bit port size. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga80927a542163775f51782964391d9774a9031089fca5f2e885506d3241c827479"></a>kSDRAMC_PortSize16Bit</em> </td><td class="fielddoc">
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<p>16-Bit port size. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<td class="memname">enum <a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga9eb1e63a96bbd0b8c04c77dbc1221a38a554d56a199529755bed2e67bab27fe0c"></a>kSDRAMC_Block0</em> </td><td class="fielddoc">
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<p>Select SDRAM block 0. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga9eb1e63a96bbd0b8c04c77dbc1221a38aac169b7b72c468b2429ce68ddac27d5a"></a>kSDRAMC_Block1</em> </td><td class="fielddoc">
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<p>Select SDRAM block 1. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<h2 class="groupheader">Function Documentation</h2>
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<a class="anchor" id="ga1507ca3630a0e845eeea249712e00667"></a>
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<td class="memname">void SDRAMC_Init </td>
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<td>(</td>
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<td class="paramtype">SDRAM_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__sdramc.html#structsdramc__config__t">sdramc_config_t</a> * </td>
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<td class="paramname"><em>configure</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>This function ungates the SDRAM controller clock and initializes the SDRAM controller. This function must be called before calling any other SDRAM controller driver functions. Example </p>
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<div class="fragment"><div class="line"><a class="code" href="group__sdramc.html#structsdramc__refresh__config__t">sdramc_refresh_config_t</a> refreshConfig;</div>
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<div class="line"><a class="code" href="group__sdramc.html#structsdramc__blockctl__config__t">sdramc_blockctl_config_t</a> blockConfig;</div>
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<div class="line"><a class="code" href="group__sdramc.html#structsdramc__config__t">sdramc_config_t</a> config;</div>
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<div class="line"></div>
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<div class="line">refreshConfig.<a class="code" href="group__sdramc.html#ad290e97c817b4d52c220417228429902">refreshTime</a> = kSDRAM_RefreshThreeClocks;</div>
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<div class="line">refreshConfig.<a class="code" href="group__sdramc.html#acf4832db4f72003ead0936eb1fa553b6">sdramRefreshRow</a> = 15625;</div>
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<div class="line">refreshConfig.busClock = 60000000;</div>
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<div class="line"></div>
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<div class="line">blockConfig.<a class="code" href="group__sdramc.html#a74761b33f800579c3a20ca9c78f357c7">block</a> = <a class="code" href="group__sdramc.html#gga9eb1e63a96bbd0b8c04c77dbc1221a38a554d56a199529755bed2e67bab27fe0c">kSDRAMC_Block0</a>;</div>
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<div class="line">blockConfig.<a class="code" href="group__sdramc.html#a34869df7f62ea5db5a9a7d38f7eadf87">portSize</a> = <a class="code" href="group__sdramc.html#gga80927a542163775f51782964391d9774a9031089fca5f2e885506d3241c827479">kSDRAMC_PortSize16Bit</a>;</div>
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<div class="line">blockConfig.<a class="code" href="group__sdramc.html#adb47879cacae9b6ecdccee03c734da4b">location</a> = <a class="code" href="group__sdramc.html#gga277ebf8d251aac6eab5f5c42ac3fc62ca3a28222a7225a079c6a68acaaaf7b824">kSDRAMC_Commandbit19</a>;</div>
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<div class="line">blockConfig.<a class="code" href="group__sdramc.html#afc3c673532c14837867d7cabecd97b03">latency</a> = <a class="code" href="group__sdramc.html#gga60386afe3f3f702f02a990626df913e1af23bd012b4da435853cb10e9af855b47">kSDRAMC_RefreshThreeClocks</a>;</div>
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<div class="line">blockConfig.<a class="code" href="group__sdramc.html#a295fb68fb342f8a9696de1ac1a4fd67d">address</a> = SDRAM_START_ADDRESS;</div>
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<div class="line">blockConfig.<a class="code" href="group__sdramc.html#ad8d57f01dc537eade6ee05aa05d25e8c">addressMask</a> = 0x7c0000;</div>
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<div class="line"></div>
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<div class="line">config.<a class="code" href="group__sdramc.html#ab3be5ccfa2f6a0f86bc82545fe3a2af5">refreshConfig</a> = &refreshConfig,</div>
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<div class="line">config.<a class="code" href="group__sdramc.html#af027f5cd8e842233c8ccd2f256be8d42">blockConfig</a> = &blockConfig,</div>
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<div class="line">config.totalBlocks = 1;</div>
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<div class="line"></div>
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<div class="line"><a class="code" href="group__sdramc.html#ga1507ca3630a0e845eeea249712e00667">SDRAMC_Init</a>(SDRAM, &config);</div>
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</div><!-- fragment --><dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>SDRAM controller peripheral base address. </td></tr>
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<tr><td class="paramname">configure</td><td>The SDRAM configuration structure pointer. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga43aadfcec0591fdcc5de2e3190b3bb0d"></a>
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<td class="memname">void SDRAMC_Deinit </td>
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<td>(</td>
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<td class="paramtype">SDRAM_Type * </td>
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<td class="paramname"><em>base</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>This function gates the SDRAM controller clock. As a result, the SDRAM controller module doesn't work after calling this function.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>SDRAM controller peripheral base address. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<td class="memname">status_t SDRAMC_SendCommand </td>
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<td>(</td>
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<td class="paramtype">SDRAM_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> </td>
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<td class="paramname"><em>block</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="group__sdramc.html#ga050eba54b4afc87d1b6db93cdc873410">sdramc_command_t</a> </td>
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<td class="paramname"><em>command</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>This function sends the command to SDRAM. There are precharge command, initialize MRS command, auto-refresh enable/disable command, and self-refresh enter/exit commands. Note the self-refresh enter/exit commands are all blocks setting and "block" are ignored. Ensure to set the right "block" when send other commands.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>SDRAM controller peripheral base address. </td></tr>
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<tr><td class="paramname">block</td><td>The block selection. </td></tr>
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<tr><td class="paramname">command</td><td>The SDRAM command, see "sdramc_command_t". kSDRAMC_ImrsCommand - Initialize MRS command <br/>
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kSDRAMC_PrechargeCommand - Initialize precharge command <br/>
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kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command <br/>
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kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command <br/>
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kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command <br/>
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kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>Command execution status. All commands except the "initialize MRS command" and "precharge command" return kStatus_Success directly. For "initialize MRS command" and "precharge command" return kStatus_Success when the command success else return kStatus_Fail. </dd></dl>
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<td class="mlabels-left">
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<td class="memname">static void SDRAMC_EnableWriteProtect </td>
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<td>(</td>
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<td class="paramtype">SDRAM_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramtype"><a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> </td>
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<td class="paramname"><em>block</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>SDRAM peripheral base address. </td></tr>
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<tr><td class="paramname">block</td><td>The block which is selected. </td></tr>
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<tr><td class="paramname">enable</td><td>True enable write protection, false disable write protection. </td></tr>
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</table>
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</dd>
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<td class="memname">static void SDRAMC_EnableOperateValid </td>
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<td>(</td>
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<td class="paramtype">SDRAM_Type * </td>
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<td class="paramtype"><a class="el" href="group__sdramc.html#ga9eb1e63a96bbd0b8c04c77dbc1221a38">sdramc_block_selection_t</a> </td>
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<td class="paramname"><em>block</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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<td>)</td>
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</td>
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>SDRAM peripheral base address. </td></tr>
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<tr><td class="paramname">block</td><td>The block which is selected. </td></tr>
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<tr><td class="paramname">enable</td><td>True enable the operation valid, false disable the operation valid. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div><!-- contents -->
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