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<div class="title">LMEM: Local Memory Controller Cache Control Driver</div> </div>
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<div class="contents">
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
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<p>The KSDK provides a peripheral driver for the Local Memory Controller Cache Controller module of Kinetis devices.</p>
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<h1><a class="anchor" id="LMEMDescrip"></a>
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Descriptions</h1>
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<p>The LMEM Cache peripheral driver allows the user to enable/disable the cache and to perform cache maintenance operations such as invalidate, push, and clear. These maintenance operations may be performed on the Processor Code (PC) bus or Both Processor Code (PC) and Processor System (PS) bus.</p>
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<p>The Kinetis devices contain a Processor Code (PC) bus and a Processor System (PS) bus: The Processor Code (PC) bus - a 32-bit address space bus with low-order addresses (0x0000_0000 through 0x1FFF_FFFF) used normally for code access. The Processor System (PS) bus - a 32-bit address space bus with high-order addresses (0x2000_0000 through 0xFFFF_FFFF) used normally for data accesses.</p>
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<p>Some Kinetic MCU devices have caches available for the PC bus and PS bus, others may only have a PC bus cache, while some do not have PC or PS caches at all. See the appropriate Kinetis reference manual for cache availability.</p>
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<p>Cache maintenance operations:</p>
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<div> <table class="doxtable">
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<tr>
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<td colspan="1" align="center" bgcolor="#2E9AFE">command </td><td colspan="1" align="center" bgcolor="#2E9AFE">description </td></tr>
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<tr>
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<th align="center">Invalidate </th><td align="left">Unconditionally clear valid and modify bits of a cache entry. </td></tr>
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<tr>
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<th align="center">Push </th><td align="left">Push a cache entry if it is valid and modified, then clear the modify bit. If entry is not valid or not modified, leave as is. A cache push is synonymous with a cache flush. </td></tr>
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<tr>
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<th align="center">Clear </th><td align="left">Push a cache entry if it is valid and modified, then clear the valid and modify bits. If entry is not valid or not modified, clear the valid bit. </td></tr>
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</table>
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</div><p>The above cache maintenance operations may be performed on the entire cache or on a line-basis. The peripheral driver API names distinguish between the two using the terms "All" or Line".</p>
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<h1><a class="anchor" id="LMEMCacheFunGrps"></a>
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Function groups</h1>
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<h2><a class="anchor" id="LMEMCodeBusCacheControl"></a>
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Local Memory Processor Code Bus Cache Control</h2>
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<p>The invalidate command can be performed on the entire cache, one line and multiple lines by calling <a class="el" href="group__lmem__cache.html#ga181ac89141e61050cfc032efaf45b2c2" title="Invalidates the processor code bus cache. ">LMEM_CodeCacheInvalidateAll()</a>, <a class="el" href="group__lmem__cache.html#ga750774c1b0e082ee3f405207941f7cf6" title="Invalidates a specific line in the processor code bus cache. ">LMEM_CodeCacheInvalidateLine()</a>, and <a class="el" href="group__lmem__cache.html#gab98f2c4473e833fbbf357ccffec3ff1f" title="Invalidates multiple lines in the processor code bus cache. ">LMEM_CodeCacheInvalidateMultiLines()</a>.</p>
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<p>The push command can be performed on the entire cache, one line and multiple lines by calling <a class="el" href="group__lmem__cache.html#ga230b22ba46c4d5c60ae37c9cc201b40d" title="Pushes all modified lines in the processor code bus cache. ">LMEM_CodeCachePushAll()</a>, <a class="el" href="group__lmem__cache.html#ga5058349ee0774fc2af503986ea65e798" title="Pushes a specific modified line in the processor code bus cache. ">LMEM_CodeCachePushLine()</a>, and <a class="el" href="group__lmem__cache.html#ga2c3d306975555463b581746b7fbfd86b" title="Pushes multiple modified lines in the processor code bus cache. ">LMEM_CodeCachePushMultiLines()</a>.</p>
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<p>The clear command can be performed on the entire cache, one line and multiple lines by calling <a class="el" href="group__lmem__cache.html#ga3768011d4d7ac9b228eae28fae8f8989" title="Clears the processor code bus cache. ">LMEM_CodeCacheClearAll()</a>, <a class="el" href="group__lmem__cache.html#gae90ade5b09656d898f5a3a1edec8864c" title="Clears a specific line in the processor code bus cache. ">LMEM_CodeCacheClearLine()</a>, and <a class="el" href="group__lmem__cache.html#gacabe403fb94aa540a676333355f85fc0" title="Clears multiple lines in the processor code bus cache. ">LMEM_CodeCacheClearMultiLines()</a>.</p>
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<p>Note that the parameter "address" must be supplied which indicates the physical address of the line you wish to perform the one line cache maintenance operation. In addition, the length the number of bytes should be supplied for multiple lines operation. The function determines if the length meets or exceeds 1/2 the cache size because the cache contains 2 WAYs, half of the cache is in WAY0 and the other half in WAY1 and if so, performs a cache maintenance "all" operation which is faster than performing the cache maintenance on a line-basis.</p>
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<p>Cache Demotion: Cache region demotion - Demoting the cache mode reduces the cache function applied to a memory region from write-back to write-through to non-cacheable. The cache region demote function checks to see if the requested cache mode is higher than or equal to the current cache mode, and if so, returns an error. After a region is demoted, its cache mode can only be raised by a reset, which returns it to its default state. To demote a cache region, call the <a class="el" href="group__lmem__cache.html#ga8e2d695e7cd7c103eed501176e12770b" title="Demotes the cache mode of a region in processor code bus cache. ">LMEM_CodeCacheDemoteRegion()</a>.</p>
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<p>Note that the address region assignment of the 16 subregions is device-specific and is detailed in the Chip Configuration section of the SoC Kinetis reference manual. The LMEM provides typedef enums for each of the 16 regions, starting with "kLMEM_CacheRegion0" and ending with "kLMEM_CacheRegion15". The parameter cacheMode is of type lmem_cache_mode_t. This provides typedef enums for each of the cache modes, such as "kLMEM_CacheNonCacheable", "kLMEM_CacheWriteThrough", and "kLMEM_CacheWriteBack".</p>
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<p>Cache Enable and Disable: The cache enable function enables the PC bus cache and the write buffer. However, before enabling these, the function first performs an invalidate all. The user should call <a class="el" href="group__lmem__cache.html#ga9fd3f219c41f48b2dcf83cb8c84ca5df" title="Enables/disables the processor code bus cache. ">LMEM_EnableCodeCache()</a> to enable a particular bus cache.</p>
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<h2><a class="anchor" id="LMEMSysBusCacheControl"></a>
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Local Memory Processor System Bus Cache Control</h2>
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<p>The invalidate command can be performed on the entire cache, one line and multiple lines by calling LMEM_SystemCacheInvalidateAll(), LMEM_SystemCacheInvalidateLine(), and LMEM_SystemCacheInvalidateMultiLines().</p>
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<p>The push command can be performed on the entire cache, one line and multiple lines by calling LMEM_SystemCachePushAll(), LMEM_SystemCachePushLine(), and LMEM_SystemCachePushMultiLines().</p>
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<p>The clear command can be performed on the entire cache, one line and multiple lines by calling LMEM_SystemCacheClearAll(), LMEM_SystemCacheClearLine(), and LMEM_SystemCacheClearMultiLines().</p>
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<p>Note that the parameter "address" must be supplied, which indicates the physical address of the line you wish to perform the one line cache maintenance operation. In addition, the length the number of bytes should be supplied for multiple lines operation. The function determines if the length meets or exceeds 1/2 the cache size because the cache contains 2 WAYs, half of the cache is in WAY0 and the other half in WAY1 and if so, performs a cache maintenance "all" operation which is faster than performing the cache maintenance on a line-basis.</p>
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<p>Cache Demotion: Cache region demotion - Demoting the cache mode reduces the cache function applied to a memory region from write-back to write-through to non-cacheable. The cache region demote function checks to see if the requested cache mode is higher than or equal to the current cache mode, and if so, returns an error. After a region is demoted, its cache mode can only be raised by a reset, which returns it to its default state. To demote a cache region, call the LMEM_SystemCacheDemoteRegion().</p>
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<p>Note that the address region assignment of the 16 subregions is device-specific and is detailed in the Chip Configuration section of the Kinetis SoC reference manual. The LMEM provides typedef enums for each of the 16 regions, starting with "kLMEM_CacheRegion0" and ending with "kLMEM_CacheRegion15". The parameter cacheMode is of type lmem_cache_mode_t. This provides typedef enums for each of the cache modes, such as "kLMEM_CacheNonCacheable", "kLMEM_CacheWriteThrough", and "kLMEM_CacheWriteBack".</p>
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<p>Cache Enable and Disable: The cache enable function enables the PS bus cache and the write buffer. However, before enabling these, the function first performs an invalidate all. The user should call LMEM_EnableSystemCache() to enable a particular bus cache. </p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="files"></a>
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Files</h2></td></tr>
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<tr class="memitem:fsl__lmem__cache_8h"><td class="memItemLeft" align="right" valign="top">file  </td><td class="memItemRight" valign="bottom"><a class="el" href="fsl__lmem__cache_8h.html">fsl_lmem_cache.h</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:gab15785d98d8873207f708e46aab35306"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#gab15785d98d8873207f708e46aab35306">LMEM_CACHE_LINE_SIZE</a>   (0x10U)</td></tr>
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<tr class="memdesc:gab15785d98d8873207f708e46aab35306"><td class="mdescLeft"> </td><td class="mdescRight">Cache line is 16-bytes. <a href="#gab15785d98d8873207f708e46aab35306">More...</a><br/></td></tr>
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<tr class="separator:gab15785d98d8873207f708e46aab35306"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga915a068b47d97bfc70628571bc24e777"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga915a068b47d97bfc70628571bc24e777">LMEM_CACHE_SIZE_ONEWAY</a>   (4096U)</td></tr>
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<tr class="memdesc:ga915a068b47d97bfc70628571bc24e777"><td class="mdescLeft"> </td><td class="mdescRight">Cache size is 4K-bytes one way. <a href="#ga915a068b47d97bfc70628571bc24e777">More...</a><br/></td></tr>
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<tr class="separator:ga915a068b47d97bfc70628571bc24e777"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
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Enumerations</h2></td></tr>
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<tr class="memitem:ga09096baa68dd9ae3de591d60f6011996"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga09096baa68dd9ae3de591d60f6011996">lmem_cache_mode_t</a> { <br/>
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  <a class="el" href="group__lmem__cache.html#gga09096baa68dd9ae3de591d60f6011996a2fcebcb37f55c9d2c561cf329eb96626">kLMEM_NonCacheable</a> = 0x0U,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga09096baa68dd9ae3de591d60f6011996a8eb97a4de64ce57df954c0b9b0f4adef">kLMEM_CacheWriteThrough</a> = 0x2U,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga09096baa68dd9ae3de591d60f6011996a112b9b26738baa2a1084f0c2ba3c58ba">kLMEM_CacheWriteBack</a> = 0x3U
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<br/>
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}</td></tr>
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<tr class="memdesc:ga09096baa68dd9ae3de591d60f6011996"><td class="mdescLeft"> </td><td class="mdescRight">LMEM cache mode options. <a href="group__lmem__cache.html#ga09096baa68dd9ae3de591d60f6011996">More...</a><br/></td></tr>
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<tr class="separator:ga09096baa68dd9ae3de591d60f6011996"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6f44b818849af333fa61b68897e14c03"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga6f44b818849af333fa61b68897e14c03">lmem_cache_region_t</a> { <br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03ad74a9d9517cd0c6d862c3a1c14489e18">kLMEM_CacheRegion15</a> = 0U,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a56bd9b2fe99926baff82935df81787cd">kLMEM_CacheRegion14</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03ae2c8c655a5c07d27d4fe70650923af5b">kLMEM_CacheRegion13</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a832180ee865a178f0b640cb06d4650d0">kLMEM_CacheRegion12</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a4b577a123c3d5e2b18577b05bd5e8beb">kLMEM_CacheRegion11</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03ab8406d7e02c4ba1d8cad30f3088f774e">kLMEM_CacheRegion10</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03aa403544c05bc15ae353def2bcd971ed0">kLMEM_CacheRegion9</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a66100f2291290ba55d2640126bcac726">kLMEM_CacheRegion8</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a88c1ae1c31a41e5d32a93b473dd3f78e">kLMEM_CacheRegion7</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03aec2370cd20f3c949e6c00322cb4b2f39">kLMEM_CacheRegion6</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a2ade4fc2a2fd54cc56eb86fb99824fbe">kLMEM_CacheRegion5</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a05f125c196a9d463595ec374434c28b9">kLMEM_CacheRegion4</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a2b7d1f4f13cea7c270b800cb2750a40a">kLMEM_CacheRegion3</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03ac4cb8c10e4687c303875ec47eb6b8077">kLMEM_CacheRegion2</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03aa97121954dcdfe6578962fba835a9446">kLMEM_CacheRegion1</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga6f44b818849af333fa61b68897e14c03a8ad55d0c458ea05794481674cdee91f8">kLMEM_CacheRegion0</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga6f44b818849af333fa61b68897e14c03"><td class="mdescLeft"> </td><td class="mdescRight">LMEM cache regions. <a href="group__lmem__cache.html#ga6f44b818849af333fa61b68897e14c03">More...</a><br/></td></tr>
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<tr class="separator:ga6f44b818849af333fa61b68897e14c03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43186bf9e2770c987a52838fbe727a7a"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga43186bf9e2770c987a52838fbe727a7a">lmem_cache_line_command_t</a> { <br/>
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  <a class="el" href="group__lmem__cache.html#gga43186bf9e2770c987a52838fbe727a7aaf10fa0c0605c816d948169575dcb0aeb">kLMEM_CacheLineSearchReadOrWrite</a> = 0U,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga43186bf9e2770c987a52838fbe727a7aaf3447098ecfdb6906516e874a7cdc443">kLMEM_CacheLineInvalidate</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga43186bf9e2770c987a52838fbe727a7aae35d06abf37513e3aad8a827db6b608b">kLMEM_CacheLinePush</a>,
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<br/>
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  <a class="el" href="group__lmem__cache.html#gga43186bf9e2770c987a52838fbe727a7aaf4b898e3fc67d1fa137d018f3cac903f">kLMEM_CacheLineClear</a>
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<br/>
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}</td></tr>
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<tr class="memdesc:ga43186bf9e2770c987a52838fbe727a7a"><td class="mdescLeft"> </td><td class="mdescRight">LMEM cache line command. <a href="group__lmem__cache.html#ga43186bf9e2770c987a52838fbe727a7a">More...</a><br/></td></tr>
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<tr class="separator:ga43186bf9e2770c987a52838fbe727a7a"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Driver version</h2></td></tr>
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<tr class="memitem:ga96be95568443eb9f88a9bbc7bf27e5e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga96be95568443eb9f88a9bbc7bf27e5e1">FSL_LMEM_DRIVER_VERSION</a>   (<a class="el" href="group__flash__driver.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 0, 0))</td></tr>
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<tr class="memdesc:ga96be95568443eb9f88a9bbc7bf27e5e1"><td class="mdescLeft"> </td><td class="mdescRight">LMEM controller driver version 2.0.0. <a href="#ga96be95568443eb9f88a9bbc7bf27e5e1">More...</a><br/></td></tr>
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<tr class="separator:ga96be95568443eb9f88a9bbc7bf27e5e1"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Local Memory Processor Code Bus Cache Control</h2></td></tr>
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<tr class="memitem:ga9fd3f219c41f48b2dcf83cb8c84ca5df"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga9fd3f219c41f48b2dcf83cb8c84ca5df">LMEM_EnableCodeCache</a> (LMEM_Type *base, bool enable)</td></tr>
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<tr class="memdesc:ga9fd3f219c41f48b2dcf83cb8c84ca5df"><td class="mdescLeft"> </td><td class="mdescRight">Enables/disables the processor code bus cache. <a href="#ga9fd3f219c41f48b2dcf83cb8c84ca5df">More...</a><br/></td></tr>
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<tr class="separator:ga9fd3f219c41f48b2dcf83cb8c84ca5df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga181ac89141e61050cfc032efaf45b2c2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga181ac89141e61050cfc032efaf45b2c2">LMEM_CodeCacheInvalidateAll</a> (LMEM_Type *base)</td></tr>
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<tr class="memdesc:ga181ac89141e61050cfc032efaf45b2c2"><td class="mdescLeft"> </td><td class="mdescRight">Invalidates the processor code bus cache. <a href="#ga181ac89141e61050cfc032efaf45b2c2">More...</a><br/></td></tr>
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<tr class="separator:ga181ac89141e61050cfc032efaf45b2c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga230b22ba46c4d5c60ae37c9cc201b40d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga230b22ba46c4d5c60ae37c9cc201b40d">LMEM_CodeCachePushAll</a> (LMEM_Type *base)</td></tr>
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<tr class="memdesc:ga230b22ba46c4d5c60ae37c9cc201b40d"><td class="mdescLeft"> </td><td class="mdescRight">Pushes all modified lines in the processor code bus cache. <a href="#ga230b22ba46c4d5c60ae37c9cc201b40d">More...</a><br/></td></tr>
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<tr class="separator:ga230b22ba46c4d5c60ae37c9cc201b40d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3768011d4d7ac9b228eae28fae8f8989"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga3768011d4d7ac9b228eae28fae8f8989">LMEM_CodeCacheClearAll</a> (LMEM_Type *base)</td></tr>
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<tr class="memdesc:ga3768011d4d7ac9b228eae28fae8f8989"><td class="mdescLeft"> </td><td class="mdescRight">Clears the processor code bus cache. <a href="#ga3768011d4d7ac9b228eae28fae8f8989">More...</a><br/></td></tr>
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<tr class="separator:ga3768011d4d7ac9b228eae28fae8f8989"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga750774c1b0e082ee3f405207941f7cf6"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga750774c1b0e082ee3f405207941f7cf6">LMEM_CodeCacheInvalidateLine</a> (LMEM_Type *base, uint32_t address)</td></tr>
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<tr class="memdesc:ga750774c1b0e082ee3f405207941f7cf6"><td class="mdescLeft"> </td><td class="mdescRight">Invalidates a specific line in the processor code bus cache. <a href="#ga750774c1b0e082ee3f405207941f7cf6">More...</a><br/></td></tr>
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<tr class="separator:ga750774c1b0e082ee3f405207941f7cf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab98f2c4473e833fbbf357ccffec3ff1f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#gab98f2c4473e833fbbf357ccffec3ff1f">LMEM_CodeCacheInvalidateMultiLines</a> (LMEM_Type *base, uint32_t address, uint32_t length)</td></tr>
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<tr class="memdesc:gab98f2c4473e833fbbf357ccffec3ff1f"><td class="mdescLeft"> </td><td class="mdescRight">Invalidates multiple lines in the processor code bus cache. <a href="#gab98f2c4473e833fbbf357ccffec3ff1f">More...</a><br/></td></tr>
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<tr class="separator:gab98f2c4473e833fbbf357ccffec3ff1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5058349ee0774fc2af503986ea65e798"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga5058349ee0774fc2af503986ea65e798">LMEM_CodeCachePushLine</a> (LMEM_Type *base, uint32_t address)</td></tr>
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<tr class="memdesc:ga5058349ee0774fc2af503986ea65e798"><td class="mdescLeft"> </td><td class="mdescRight">Pushes a specific modified line in the processor code bus cache. <a href="#ga5058349ee0774fc2af503986ea65e798">More...</a><br/></td></tr>
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<tr class="separator:ga5058349ee0774fc2af503986ea65e798"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2c3d306975555463b581746b7fbfd86b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga2c3d306975555463b581746b7fbfd86b">LMEM_CodeCachePushMultiLines</a> (LMEM_Type *base, uint32_t address, uint32_t length)</td></tr>
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<tr class="memdesc:ga2c3d306975555463b581746b7fbfd86b"><td class="mdescLeft"> </td><td class="mdescRight">Pushes multiple modified lines in the processor code bus cache. <a href="#ga2c3d306975555463b581746b7fbfd86b">More...</a><br/></td></tr>
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<tr class="separator:ga2c3d306975555463b581746b7fbfd86b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae90ade5b09656d898f5a3a1edec8864c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#gae90ade5b09656d898f5a3a1edec8864c">LMEM_CodeCacheClearLine</a> (LMEM_Type *base, uint32_t address)</td></tr>
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<tr class="memdesc:gae90ade5b09656d898f5a3a1edec8864c"><td class="mdescLeft"> </td><td class="mdescRight">Clears a specific line in the processor code bus cache. <a href="#gae90ade5b09656d898f5a3a1edec8864c">More...</a><br/></td></tr>
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<tr class="separator:gae90ade5b09656d898f5a3a1edec8864c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacabe403fb94aa540a676333355f85fc0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#gacabe403fb94aa540a676333355f85fc0">LMEM_CodeCacheClearMultiLines</a> (LMEM_Type *base, uint32_t address, uint32_t length)</td></tr>
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<tr class="memdesc:gacabe403fb94aa540a676333355f85fc0"><td class="mdescLeft"> </td><td class="mdescRight">Clears multiple lines in the processor code bus cache. <a href="#gacabe403fb94aa540a676333355f85fc0">More...</a><br/></td></tr>
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<tr class="separator:gacabe403fb94aa540a676333355f85fc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8e2d695e7cd7c103eed501176e12770b"><td class="memItemLeft" align="right" valign="top">status_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__lmem__cache.html#ga8e2d695e7cd7c103eed501176e12770b">LMEM_CodeCacheDemoteRegion</a> (LMEM_Type *base, <a class="el" href="group__lmem__cache.html#ga6f44b818849af333fa61b68897e14c03">lmem_cache_region_t</a> region, <a class="el" href="group__lmem__cache.html#ga09096baa68dd9ae3de591d60f6011996">lmem_cache_mode_t</a> cacheMode)</td></tr>
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<tr class="memdesc:ga8e2d695e7cd7c103eed501176e12770b"><td class="mdescLeft"> </td><td class="mdescRight">Demotes the cache mode of a region in processor code bus cache. <a href="#ga8e2d695e7cd7c103eed501176e12770b">More...</a><br/></td></tr>
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<tr class="separator:ga8e2d695e7cd7c103eed501176e12770b"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<a class="anchor" id="ga96be95568443eb9f88a9bbc7bf27e5e1"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define FSL_LMEM_DRIVER_VERSION   (<a class="el" href="group__flash__driver.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 0, 0))</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="gab15785d98d8873207f708e46aab35306"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define LMEM_CACHE_LINE_SIZE   (0x10U)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="ga915a068b47d97bfc70628571bc24e777"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define LMEM_CACHE_SIZE_ONEWAY   (4096U)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<a class="anchor" id="ga09096baa68dd9ae3de591d60f6011996"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="group__lmem__cache.html#ga09096baa68dd9ae3de591d60f6011996">lmem_cache_mode_t</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga09096baa68dd9ae3de591d60f6011996a2fcebcb37f55c9d2c561cf329eb96626"></a>kLMEM_NonCacheable</em> </td><td class="fielddoc">
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<p>CACHE mode: non-cacheable. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga09096baa68dd9ae3de591d60f6011996a8eb97a4de64ce57df954c0b9b0f4adef"></a>kLMEM_CacheWriteThrough</em> </td><td class="fielddoc">
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<p>CACHE mode: write-through. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga09096baa68dd9ae3de591d60f6011996a112b9b26738baa2a1084f0c2ba3c58ba"></a>kLMEM_CacheWriteBack</em> </td><td class="fielddoc">
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<p>CACHE mode: write-back. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a class="anchor" id="ga6f44b818849af333fa61b68897e14c03"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="group__lmem__cache.html#ga6f44b818849af333fa61b68897e14c03">lmem_cache_region_t</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03ad74a9d9517cd0c6d862c3a1c14489e18"></a>kLMEM_CacheRegion15</em> </td><td class="fielddoc">
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<p>Cache Region 15. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a56bd9b2fe99926baff82935df81787cd"></a>kLMEM_CacheRegion14</em> </td><td class="fielddoc">
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<p>Cache Region 14. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03ae2c8c655a5c07d27d4fe70650923af5b"></a>kLMEM_CacheRegion13</em> </td><td class="fielddoc">
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<p>Cache Region 13. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a832180ee865a178f0b640cb06d4650d0"></a>kLMEM_CacheRegion12</em> </td><td class="fielddoc">
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<p>Cache Region 12. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a4b577a123c3d5e2b18577b05bd5e8beb"></a>kLMEM_CacheRegion11</em> </td><td class="fielddoc">
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<p>Cache Region 11. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03ab8406d7e02c4ba1d8cad30f3088f774e"></a>kLMEM_CacheRegion10</em> </td><td class="fielddoc">
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<p>Cache Region 10. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03aa403544c05bc15ae353def2bcd971ed0"></a>kLMEM_CacheRegion9</em> </td><td class="fielddoc">
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<p>Cache Region 9. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a66100f2291290ba55d2640126bcac726"></a>kLMEM_CacheRegion8</em> </td><td class="fielddoc">
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<p>Cache Region 8. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a88c1ae1c31a41e5d32a93b473dd3f78e"></a>kLMEM_CacheRegion7</em> </td><td class="fielddoc">
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<p>Cache Region 7. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03aec2370cd20f3c949e6c00322cb4b2f39"></a>kLMEM_CacheRegion6</em> </td><td class="fielddoc">
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<p>Cache Region 6. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a2ade4fc2a2fd54cc56eb86fb99824fbe"></a>kLMEM_CacheRegion5</em> </td><td class="fielddoc">
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<p>Cache Region 5. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a05f125c196a9d463595ec374434c28b9"></a>kLMEM_CacheRegion4</em> </td><td class="fielddoc">
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<p>Cache Region 4. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a2b7d1f4f13cea7c270b800cb2750a40a"></a>kLMEM_CacheRegion3</em> </td><td class="fielddoc">
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<p>Cache Region 3. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03ac4cb8c10e4687c303875ec47eb6b8077"></a>kLMEM_CacheRegion2</em> </td><td class="fielddoc">
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<p>Cache Region 2. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03aa97121954dcdfe6578962fba835a9446"></a>kLMEM_CacheRegion1</em> </td><td class="fielddoc">
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<p>Cache Region 1. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga6f44b818849af333fa61b68897e14c03a8ad55d0c458ea05794481674cdee91f8"></a>kLMEM_CacheRegion0</em> </td><td class="fielddoc">
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<p>Cache Region 0. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a class="anchor" id="ga43186bf9e2770c987a52838fbe727a7a"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="group__lmem__cache.html#ga43186bf9e2770c987a52838fbe727a7a">lmem_cache_line_command_t</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga43186bf9e2770c987a52838fbe727a7aaf10fa0c0605c816d948169575dcb0aeb"></a>kLMEM_CacheLineSearchReadOrWrite</em> </td><td class="fielddoc">
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<p>Cache line search and read or write. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga43186bf9e2770c987a52838fbe727a7aaf3447098ecfdb6906516e874a7cdc443"></a>kLMEM_CacheLineInvalidate</em> </td><td class="fielddoc">
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<p>Cache line invalidate. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga43186bf9e2770c987a52838fbe727a7aae35d06abf37513e3aad8a827db6b608b"></a>kLMEM_CacheLinePush</em> </td><td class="fielddoc">
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<p>Cache line push. </p>
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</td></tr>
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<tr><td class="fieldname"><em><a class="anchor" id="gga43186bf9e2770c987a52838fbe727a7aaf4b898e3fc67d1fa137d018f3cac903f"></a>kLMEM_CacheLineClear</em> </td><td class="fielddoc">
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<p>Cache line clear. </p>
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</td></tr>
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</table>
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</div>
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</div>
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<h2 class="groupheader">Function Documentation</h2>
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<a class="anchor" id="ga9fd3f219c41f48b2dcf83cb8c84ca5df"></a>
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<td class="memname">void LMEM_EnableCodeCache </td>
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<td>(</td>
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<td class="paramtype">LMEM_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function enables/disables the cache. The function first invalidates the entire cache and then enables/disable both the cache and write buffers.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
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<tr><td class="paramname">enable</td><td>The enable or disable flag. true - enable the code cache. false - disable the code cache. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga181ac89141e61050cfc032efaf45b2c2"></a>
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<div class="memitem">
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<table class="memname">
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<td class="memname">void LMEM_CodeCacheInvalidateAll </td>
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<td>(</td>
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<td class="paramtype">LMEM_Type * </td>
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<td class="paramname"><em>base</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function invalidates the cache both ways, which means that it unconditionally clears valid bits and modifies bits of a cache entry.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga230b22ba46c4d5c60ae37c9cc201b40d"></a>
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<div class="memitem">
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<td class="memname">void LMEM_CodeCachePushAll </td>
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<td>(</td>
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<td class="paramtype">LMEM_Type * </td>
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<td class="paramname"><em>base</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function pushes all modified lines in both ways in the entire cache. It pushes a cache entry if it is valid and modified and clears the modified bit. If the entry is not valid or not modified, leave as is. This action does not clear the valid bit. A cache push is synonymous with a cache flush.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga3768011d4d7ac9b228eae28fae8f8989"></a>
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<td class="memname">void LMEM_CodeCacheClearAll </td>
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<td>(</td>
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<td class="paramtype">LMEM_Type * </td>
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<td class="paramname"><em>base</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function clears the entire cache and pushes (flushes) and invalidates the operation. Clear - Pushes a cache entry if it is valid and modified, then clears the valid and modified bits. If the entry is not valid or not modified, clear the valid bit.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga750774c1b0e082ee3f405207941f7cf6"></a>
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<td class="memname">void LMEM_CodeCacheInvalidateLine </td>
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<td>(</td>
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<td class="paramtype">LMEM_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function invalidates a specific line in the cache based on the physical address passed in by the user. Invalidate - Unconditionally clears valid and modified bits of a cache entry.</p>
|
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<dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
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<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
|
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<tr><td class="paramname">address</td><td>The physical address of the cache line. Should be 16-byte aligned address. If not, it is changed to the 16-byte aligned memory address. </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gab98f2c4473e833fbbf357ccffec3ff1f"></a>
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<td class="memname">void LMEM_CodeCacheInvalidateMultiLines </td>
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<td>(</td>
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<td class="paramtype">LMEM_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>length</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function invalidates multiple lines in the cache based on the physical address and length in bytes passed in by the user. If the function detects that the length meets or exceeds half the cache. Then the function performs an entire cache invalidate function, which is more efficient than invalidating the cache line-by-line. The need to check half the total amount of cache is due to the fact that the cache consists of two ways and that line commands based on the physical address searches both ways. Invalidate - Unconditionally clear valid and modified bits of a cache entry.</p>
|
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
|
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<tr><td class="paramname">address</td><td>The physical address of the cache line. Should be 16-byte aligned address. If not, it is changed to the 16-byte aligned memory address. </td></tr>
|
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<tr><td class="paramname">length</td><td>The length in bytes of the total amount of cache lines. </td></tr>
|
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga5058349ee0774fc2af503986ea65e798"></a>
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<div class="memitem">
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<tr>
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<td class="memname">void LMEM_CodeCachePushLine </td>
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<td>(</td>
|
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<td class="paramtype">LMEM_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
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<tr>
|
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<td class="paramkey"></td>
|
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<td></td>
|
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<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>address</em> </td>
|
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</tr>
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<tr>
|
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>This function pushes a specific modified line based on the physical address passed in by the user. Push - Push a cache entry if it is valid and modified, then clear the modified bit. If the entry is not valid or not modified, leave as is. This action does not clear the valid bit. A cache push is synonymous with a cache flush.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
|
|
<tr><td class="paramname">address</td><td>The physical address of the cache line. Should be 16-byte aligned address. If not, it is changed to the 16-byte aligned memory address. </td></tr>
|
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga2c3d306975555463b581746b7fbfd86b"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void LMEM_CodeCachePushMultiLines </td>
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<td>(</td>
|
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<td class="paramtype">LMEM_Type * </td>
|
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<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>address</em>, </td>
|
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</tr>
|
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<tr>
|
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<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>length</em> </td>
|
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</tr>
|
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<tr>
|
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<td></td>
|
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<td>)</td>
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<td></td><td></td>
|
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</tr>
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</table>
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</div><div class="memdoc">
|
|
<p>This function pushes multiple modified lines in the cache based on the physical address and length in bytes passed in by the user. If the function detects that the length meets or exceeds half of the cache, the function performs an cache push function, which is more efficient than pushing the modified lines in the cache line-by-line. The need to check half the total amount of cache is due to the fact that the cache consists of two ways and that line commands based on the physical address searches both ways. Push - Push a cache entry if it is valid and modified, then clear the modified bit. If the entry is not valid or not modified, leave as is. This action does not clear the valid bit. A cache push is synonymous with a cache flush.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
|
|
<tr><td class="paramname">address</td><td>The physical address of the cache line. Should be 16-byte aligned address. If not, it is changed to the 16-byte aligned memory address. </td></tr>
|
|
<tr><td class="paramname">length</td><td>The length in bytes of the total amount of cache lines. </td></tr>
|
|
</table>
|
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gae90ade5b09656d898f5a3a1edec8864c"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="memname">void LMEM_CodeCacheClearLine </td>
|
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<td>(</td>
|
|
<td class="paramtype">LMEM_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
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<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>address</em> </td>
|
|
</tr>
|
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<tr>
|
|
<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
|
|
<p>This function clears a specific line based on the physical address passed in by the user. Clear - Push a cache entry if it is valid and modified, then clear the valid and modify bits. If entry not valid or not modified, clear the valid bit.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
|
|
<tr><td class="paramname">address</td><td>The physical address of the cache line. Should be 16-byte aligned address. If not, it is changed to the 16-byte aligned memory address. </td></tr>
|
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gacabe403fb94aa540a676333355f85fc0"></a>
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<div class="memproto">
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<tr>
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<td class="memname">void LMEM_CodeCacheClearMultiLines </td>
|
|
<td>(</td>
|
|
<td class="paramtype">LMEM_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>address</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>length</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
|
|
<p>This function clears multiple lines in the cache based on the physical address and length in bytes passed in by the user. If the function detects that the length meets or exceeds half the total amount of cache, the function performs a cache clear function which is more efficient than clearing the lines in the cache line-by-line. The need to check half the total amount of cache is due to the fact that the cache consists of two ways and that line commands based on the physical address searches both ways. Clear - Push a cache entry if it is valid and modified, then clear the valid and modify bits. If entry not valid or not modified, clear the valid bit.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
|
|
<tr><td class="paramname">address</td><td>The physical address of the cache line. Should be 16-byte aligned address. If not, it is changed to the 16-byte aligned memory address. </td></tr>
|
|
<tr><td class="paramname">length</td><td>The length in bytes of the total amount of cache lines. </td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
|
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|
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</div>
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</div>
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<a class="anchor" id="ga8e2d695e7cd7c103eed501176e12770b"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="memname">status_t LMEM_CodeCacheDemoteRegion </td>
|
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<td>(</td>
|
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<td class="paramtype">LMEM_Type * </td>
|
|
<td class="paramname"><em>base</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
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<td></td>
|
|
<td class="paramtype"><a class="el" href="group__lmem__cache.html#ga6f44b818849af333fa61b68897e14c03">lmem_cache_region_t</a> </td>
|
|
<td class="paramname"><em>region</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype"><a class="el" href="group__lmem__cache.html#ga09096baa68dd9ae3de591d60f6011996">lmem_cache_mode_t</a> </td>
|
|
<td class="paramname"><em>cacheMode</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
|
|
<p>This function allows the user to demote the cache mode of a region within the device's memory map. Demoting the cache mode reduces the cache function applied to a memory region from write-back to write-through to non-cacheable. The function checks to see if the requested cache mode is higher than or equal to the current cache mode, and if so, returns an error. After a region is demoted, its cache mode can only be raised by a reset, which returns it to its default state which is the highest cache configure for each region. To maintain cache coherency, changes to the cache mode should be completed while the address space being changed is not being accessed or the cache is disabled. Before a cache mode change, this function completes a cache clear all command to push and invalidate any cache entries that may have changed.</p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">base</td><td>LMEM peripheral base address. </td></tr>
|
|
<tr><td class="paramname">region</td><td>The desired region to demote of type lmem_cache_region_t. </td></tr>
|
|
<tr><td class="paramname">cacheMode</td><td>The new, demoted cache mode of type lmem_cache_mode_t. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section return"><dt>Returns</dt><dd>The execution result. kStatus_Success The cache demote operation is successful. kStatus_Fail The cache demote operation is failure. </dd></dl>
|
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|
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</div>
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