908 lines
40 KiB
ArmAsm
908 lines
40 KiB
ArmAsm
; * ---------------------------------------------------------------------------------------
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; * @file: startup_MK22F51212.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File
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; * MK22F51212
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; * @version: 2.9
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; * @date: 2016-3-21
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; * @build: b160321
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; * ---------------------------------------------------------------------------------------
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; *
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; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.
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; * All rights reserved.
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; *
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; * Redistribution and use in source and binary forms, with or without modification,
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; * are permitted provided that the following conditions are met:
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; *
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; * o Redistributions of source code must retain the above copyright notice, this list
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; * of conditions and the following disclaimer.
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; *
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; * o Redistributions in binary form must reproduce the above copyright notice, this
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; * list of conditions and the following disclaimer in the documentation and/or
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; * other materials provided with the distribution.
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; *
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; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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; * contributors may be used to endorse or promote products derived from this
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; * software without specific prior written permission.
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; *
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; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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; *
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ;NMI Handler
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DCD HardFault_Handler ;Hard Fault Handler
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DCD MemManage_Handler ;MPU Fault Handler
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DCD BusFault_Handler ;Bus Fault Handler
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DCD UsageFault_Handler ;Usage Fault Handler
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD SVC_Handler ;SVCall Handler
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DCD DebugMon_Handler ;Debug Monitor Handler
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DCD 0 ;Reserved
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DCD PendSV_Handler ;PendSV Handler
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DCD SysTick_Handler ;SysTick Handler
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;External Interrupts
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DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete
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DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete
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DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete
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DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete
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DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete
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DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete
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DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete
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DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete
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DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete
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DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete
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DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete
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DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete
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DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete
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DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete
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DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete
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DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete
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DCD DMA_Error_IRQHandler ;DMA Error Interrupt
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DCD MCM_IRQHandler ;Normal Interrupt
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DCD FTF_IRQHandler ;FTFA Command complete interrupt
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DCD Read_Collision_IRQHandler ;Read Collision Interrupt
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DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning
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DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit
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DCD WDOG_EWM_IRQHandler ;WDOG Interrupt
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DCD RNG_IRQHandler ;RNG Interrupt
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DCD I2C0_IRQHandler ;I2C0 interrupt
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DCD I2C1_IRQHandler ;I2C1 interrupt
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DCD SPI0_IRQHandler ;SPI0 Interrupt
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DCD SPI1_IRQHandler ;SPI1 Interrupt
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DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt
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DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt
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DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt
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DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt
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DCD UART0_ERR_IRQHandler ;UART0 Error interrupt
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DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt
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DCD UART1_ERR_IRQHandler ;UART1 Error interrupt
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DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt
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DCD UART2_ERR_IRQHandler ;UART2 Error interrupt
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DCD Reserved53_IRQHandler ;Reserved interrupt 53
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DCD Reserved54_IRQHandler ;Reserved interrupt 54
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DCD ADC0_IRQHandler ;ADC0 interrupt
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DCD CMP0_IRQHandler ;CMP0 interrupt
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DCD CMP1_IRQHandler ;CMP1 interrupt
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DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt
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DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt
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DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt
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DCD Reserved61_IRQHandler ;Reserved interrupt 61
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DCD RTC_IRQHandler ;RTC interrupt
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DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt
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DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt
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DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt
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DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt
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DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt
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DCD PDB0_IRQHandler ;PDB0 Interrupt
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DCD USB0_IRQHandler ;USB0 interrupt
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DCD Reserved70_IRQHandler ;Reserved interrupt 70
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DCD Reserved71_IRQHandler ;Reserved interrupt 71
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DCD DAC0_IRQHandler ;DAC0 interrupt
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DCD MCG_IRQHandler ;MCG Interrupt
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DCD LPTMR0_IRQHandler ;LPTimer interrupt
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DCD PORTA_IRQHandler ;Port A interrupt
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DCD PORTB_IRQHandler ;Port B interrupt
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DCD PORTC_IRQHandler ;Port C interrupt
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DCD PORTD_IRQHandler ;Port D interrupt
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DCD PORTE_IRQHandler ;Port E interrupt
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DCD SWI_IRQHandler ;Software interrupt
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DCD Reserved81_IRQHandler ;Reserved interrupt 81
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DCD Reserved82_IRQHandler ;Reserved interrupt 82
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DCD Reserved83_IRQHandler ;Reserved interrupt 83
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DCD Reserved84_IRQHandler ;Reserved interrupt 84
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DCD Reserved85_IRQHandler ;Reserved interrupt 85
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DCD Reserved86_IRQHandler ;Reserved interrupt 86
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DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt
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DCD DAC1_IRQHandler ;DAC1 interrupt
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DCD ADC1_IRQHandler ;ADC1 interrupt
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DCD Reserved90_IRQHandler ;Reserved Interrupt 90
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DCD Reserved91_IRQHandler ;Reserved Interrupt 91
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DCD Reserved92_IRQHandler ;Reserved Interrupt 92
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DCD Reserved93_IRQHandler ;Reserved Interrupt 93
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DCD Reserved94_IRQHandler ;Reserved Interrupt 94
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DCD Reserved95_IRQHandler ;Reserved Interrupt 95
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DCD Reserved96_IRQHandler ;Reserved Interrupt 96
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DCD Reserved97_IRQHandler ;Reserved Interrupt 97
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DCD Reserved98_IRQHandler ;Reserved Interrupt 98
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DCD Reserved99_IRQHandler ;Reserved Interrupt 99
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DCD Reserved100_IRQHandler ;Reserved Interrupt 100
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DCD Reserved101_IRQHandler ;Reserved Interrupt 101
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DCD DefaultISR ;102
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DCD DefaultISR ;103
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DCD DefaultISR ;104
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DCD DefaultISR ;105
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DCD DefaultISR ;106
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DCD DefaultISR ;107
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DCD DefaultISR ;108
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DCD DefaultISR ;109
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DCD DefaultISR ;110
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DCD DefaultISR ;111
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DCD DefaultISR ;112
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DCD DefaultISR ;113
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DCD DefaultISR ;114
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DCD DefaultISR ;115
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DCD DefaultISR ;116
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DCD DefaultISR ;117
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DCD DefaultISR ;118
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DCD DefaultISR ;119
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DCD DefaultISR ;120
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DCD DefaultISR ;121
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DCD DefaultISR ;122
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DCD DefaultISR ;123
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DCD DefaultISR ;124
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DCD DefaultISR ;125
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DCD DefaultISR ;126
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DCD DefaultISR ;127
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DCD DefaultISR ;128
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DCD DefaultISR ;129
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DCD DefaultISR ;130
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DCD DefaultISR ;131
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DCD DefaultISR ;132
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DCD DefaultISR ;133
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DCD DefaultISR ;134
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DCD DefaultISR ;135
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DCD DefaultISR ;136
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DCD DefaultISR ;137
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DCD DefaultISR ;138
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DCD DefaultISR ;139
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DCD DefaultISR ;140
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DCD DefaultISR ;141
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DCD DefaultISR ;142
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DCD DefaultISR ;143
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DCD DefaultISR ;144
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DCD DefaultISR ;145
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DCD DefaultISR ;146
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DCD DefaultISR ;147
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DCD DefaultISR ;148
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DCD DefaultISR ;149
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DCD DefaultISR ;150
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DCD DefaultISR ;151
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DCD DefaultISR ;152
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DCD DefaultISR ;153
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DCD DefaultISR ;154
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DCD DefaultISR ;155
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DCD DefaultISR ;156
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DCD DefaultISR ;157
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DCD DefaultISR ;158
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DCD DefaultISR ;159
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DCD DefaultISR ;160
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DCD DefaultISR ;161
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DCD DefaultISR ;162
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DCD DefaultISR ;163
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DCD DefaultISR ;164
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DCD DefaultISR ;165
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DCD DefaultISR ;166
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DCD DefaultISR ;167
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DCD DefaultISR ;168
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DCD DefaultISR ;169
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DCD DefaultISR ;170
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DCD DefaultISR ;171
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DCD DefaultISR ;172
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DCD DefaultISR ;173
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DCD DefaultISR ;174
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DCD DefaultISR ;175
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DCD DefaultISR ;176
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DCD DefaultISR ;177
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DCD DefaultISR ;178
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DCD DefaultISR ;179
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DCD DefaultISR ;180
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DCD DefaultISR ;181
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DCD DefaultISR ;182
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DCD DefaultISR ;183
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DCD DefaultISR ;184
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DCD DefaultISR ;185
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DCD DefaultISR ;186
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DCD DefaultISR ;187
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DCD DefaultISR ;188
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DCD DefaultISR ;189
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DCD DefaultISR ;190
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DCD DefaultISR ;191
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DCD DefaultISR ;192
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DCD DefaultISR ;193
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DCD DefaultISR ;194
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DCD DefaultISR ;195
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DCD DefaultISR ;196
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DCD DefaultISR ;197
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DCD DefaultISR ;198
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DCD DefaultISR ;199
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DCD DefaultISR ;200
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DCD DefaultISR ;201
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DCD DefaultISR ;202
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DCD DefaultISR ;203
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DCD DefaultISR ;204
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DCD DefaultISR ;205
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DCD DefaultISR ;206
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DCD DefaultISR ;207
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DCD DefaultISR ;208
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DCD DefaultISR ;209
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DCD DefaultISR ;210
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DCD DefaultISR ;211
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DCD DefaultISR ;212
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DCD DefaultISR ;213
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DCD DefaultISR ;214
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DCD DefaultISR ;215
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DCD DefaultISR ;216
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DCD DefaultISR ;217
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DCD DefaultISR ;218
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DCD DefaultISR ;219
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DCD DefaultISR ;220
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DCD DefaultISR ;221
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DCD DefaultISR ;222
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DCD DefaultISR ;223
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DCD DefaultISR ;224
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DCD DefaultISR ;225
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DCD DefaultISR ;226
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DCD DefaultISR ;227
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DCD DefaultISR ;228
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DCD DefaultISR ;229
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DCD DefaultISR ;230
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DCD DefaultISR ;231
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DCD DefaultISR ;232
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DCD DefaultISR ;233
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DCD DefaultISR ;234
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DCD DefaultISR ;235
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DCD DefaultISR ;236
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DCD DefaultISR ;237
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DCD DefaultISR ;238
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DCD DefaultISR ;239
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DCD DefaultISR ;240
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DCD DefaultISR ;241
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DCD DefaultISR ;242
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DCD DefaultISR ;243
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DCD DefaultISR ;244
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DCD DefaultISR ;245
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DCD DefaultISR ;246
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DCD DefaultISR ;247
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DCD DefaultISR ;248
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DCD DefaultISR ;249
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DCD DefaultISR ;250
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DCD DefaultISR ;251
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DCD DefaultISR ;252
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DCD DefaultISR ;253
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DCD DefaultISR ;254
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DCD 0xFFFFFFFF ; Reserved for user TRIM value
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict access to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
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; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
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; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
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; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
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; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
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; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
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; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
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; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program Flash Region Protect Register 0
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT
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; <0=> Low-power boot
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; <1=> Normal boot
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; <o.1> EZPORT_DIS
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; <0=> EzPort operation is disabled
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; <1=> EzPort operation is enabled
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; <o.2> NMI_DIS
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; <0=> NMI interrupts are always blocked
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; <1=> NMI_b pin/interrupts reset default to enabled
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; <o.5> FAST_INIT
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; <0=> Slower initialization
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; <1=> Fast Initialization
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FOPT EQU 0xFF
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
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; <i> Flash Security
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; <o.2..3> FSLACC
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; <2=> Freescale factory access denied
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; <3=> Freescale factory access granted
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; <i> Freescale Failure Analysis Access Code
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; <o.4..5> MEEN
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; <2=> Mass erase is disabled
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; <3=> Mass erase is enabled
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; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
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; <i> Backdoor Key Security Enable
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FSEC EQU 0xFE
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; </h>
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA FlashConfig, DATA, READONLY
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__FlashConfig
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
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DCB FSEC , FOPT , 0xFF , 0xFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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IF :LNOT::DEF:RAM_TARGET
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REQUIRE FlashConfig
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ENDIF
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CPSID I ; Mask interrupts
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LDR R0, =0xE000ED08
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LDR R1, =__Vectors
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STR R1, [R0]
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LDR R0, =SystemInit
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BLX R0
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CPSIE i ; Unmask interrupts
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler\
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PROC
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EXPORT NMI_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
HardFault_Handler\
|
|
PROC
|
|
EXPORT HardFault_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
MemManage_Handler\
|
|
PROC
|
|
EXPORT MemManage_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
BusFault_Handler\
|
|
PROC
|
|
EXPORT BusFault_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
UsageFault_Handler\
|
|
PROC
|
|
EXPORT UsageFault_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
SVC_Handler\
|
|
PROC
|
|
EXPORT SVC_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
DebugMon_Handler\
|
|
PROC
|
|
EXPORT DebugMon_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
PendSV_Handler\
|
|
PROC
|
|
EXPORT PendSV_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
SysTick_Handler\
|
|
PROC
|
|
EXPORT SysTick_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
DMA0_IRQHandler\
|
|
PROC
|
|
EXPORT DMA0_IRQHandler [WEAK]
|
|
LDR R0, =DMA0_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA1_IRQHandler\
|
|
PROC
|
|
EXPORT DMA1_IRQHandler [WEAK]
|
|
LDR R0, =DMA1_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA2_IRQHandler\
|
|
PROC
|
|
EXPORT DMA2_IRQHandler [WEAK]
|
|
LDR R0, =DMA2_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA3_IRQHandler\
|
|
PROC
|
|
EXPORT DMA3_IRQHandler [WEAK]
|
|
LDR R0, =DMA3_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA4_IRQHandler\
|
|
PROC
|
|
EXPORT DMA4_IRQHandler [WEAK]
|
|
LDR R0, =DMA4_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA5_IRQHandler\
|
|
PROC
|
|
EXPORT DMA5_IRQHandler [WEAK]
|
|
LDR R0, =DMA5_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA6_IRQHandler\
|
|
PROC
|
|
EXPORT DMA6_IRQHandler [WEAK]
|
|
LDR R0, =DMA6_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA7_IRQHandler\
|
|
PROC
|
|
EXPORT DMA7_IRQHandler [WEAK]
|
|
LDR R0, =DMA7_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA8_IRQHandler\
|
|
PROC
|
|
EXPORT DMA8_IRQHandler [WEAK]
|
|
LDR R0, =DMA8_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA9_IRQHandler\
|
|
PROC
|
|
EXPORT DMA9_IRQHandler [WEAK]
|
|
LDR R0, =DMA9_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA10_IRQHandler\
|
|
PROC
|
|
EXPORT DMA10_IRQHandler [WEAK]
|
|
LDR R0, =DMA10_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA11_IRQHandler\
|
|
PROC
|
|
EXPORT DMA11_IRQHandler [WEAK]
|
|
LDR R0, =DMA11_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA12_IRQHandler\
|
|
PROC
|
|
EXPORT DMA12_IRQHandler [WEAK]
|
|
LDR R0, =DMA12_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA13_IRQHandler\
|
|
PROC
|
|
EXPORT DMA13_IRQHandler [WEAK]
|
|
LDR R0, =DMA13_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA14_IRQHandler\
|
|
PROC
|
|
EXPORT DMA14_IRQHandler [WEAK]
|
|
LDR R0, =DMA14_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA15_IRQHandler\
|
|
PROC
|
|
EXPORT DMA15_IRQHandler [WEAK]
|
|
LDR R0, =DMA15_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
DMA_Error_IRQHandler\
|
|
PROC
|
|
EXPORT DMA_Error_IRQHandler [WEAK]
|
|
LDR R0, =DMA_Error_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
I2C0_IRQHandler\
|
|
PROC
|
|
EXPORT I2C0_IRQHandler [WEAK]
|
|
LDR R0, =I2C0_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
I2C1_IRQHandler\
|
|
PROC
|
|
EXPORT I2C1_IRQHandler [WEAK]
|
|
LDR R0, =I2C1_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
SPI0_IRQHandler\
|
|
PROC
|
|
EXPORT SPI0_IRQHandler [WEAK]
|
|
LDR R0, =SPI0_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
SPI1_IRQHandler\
|
|
PROC
|
|
EXPORT SPI1_IRQHandler [WEAK]
|
|
LDR R0, =SPI1_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
I2S0_Tx_IRQHandler\
|
|
PROC
|
|
EXPORT I2S0_Tx_IRQHandler [WEAK]
|
|
LDR R0, =I2S0_Tx_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
I2S0_Rx_IRQHandler\
|
|
PROC
|
|
EXPORT I2S0_Rx_IRQHandler [WEAK]
|
|
LDR R0, =I2S0_Rx_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
LPUART0_IRQHandler\
|
|
PROC
|
|
EXPORT LPUART0_IRQHandler [WEAK]
|
|
LDR R0, =LPUART0_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
UART0_RX_TX_IRQHandler\
|
|
PROC
|
|
EXPORT UART0_RX_TX_IRQHandler [WEAK]
|
|
LDR R0, =UART0_RX_TX_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
UART0_ERR_IRQHandler\
|
|
PROC
|
|
EXPORT UART0_ERR_IRQHandler [WEAK]
|
|
LDR R0, =UART0_ERR_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
UART1_RX_TX_IRQHandler\
|
|
PROC
|
|
EXPORT UART1_RX_TX_IRQHandler [WEAK]
|
|
LDR R0, =UART1_RX_TX_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
UART1_ERR_IRQHandler\
|
|
PROC
|
|
EXPORT UART1_ERR_IRQHandler [WEAK]
|
|
LDR R0, =UART1_ERR_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
UART2_RX_TX_IRQHandler\
|
|
PROC
|
|
EXPORT UART2_RX_TX_IRQHandler [WEAK]
|
|
LDR R0, =UART2_RX_TX_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
UART2_ERR_IRQHandler\
|
|
PROC
|
|
EXPORT UART2_ERR_IRQHandler [WEAK]
|
|
LDR R0, =UART2_ERR_DriverIRQHandler
|
|
BX R0
|
|
ENDP
|
|
|
|
Default_Handler\
|
|
PROC
|
|
EXPORT DMA0_DriverIRQHandler [WEAK]
|
|
EXPORT DMA1_DriverIRQHandler [WEAK]
|
|
EXPORT DMA2_DriverIRQHandler [WEAK]
|
|
EXPORT DMA3_DriverIRQHandler [WEAK]
|
|
EXPORT DMA4_DriverIRQHandler [WEAK]
|
|
EXPORT DMA5_DriverIRQHandler [WEAK]
|
|
EXPORT DMA6_DriverIRQHandler [WEAK]
|
|
EXPORT DMA7_DriverIRQHandler [WEAK]
|
|
EXPORT DMA8_DriverIRQHandler [WEAK]
|
|
EXPORT DMA9_DriverIRQHandler [WEAK]
|
|
EXPORT DMA10_DriverIRQHandler [WEAK]
|
|
EXPORT DMA11_DriverIRQHandler [WEAK]
|
|
EXPORT DMA12_DriverIRQHandler [WEAK]
|
|
EXPORT DMA13_DriverIRQHandler [WEAK]
|
|
EXPORT DMA14_DriverIRQHandler [WEAK]
|
|
EXPORT DMA15_DriverIRQHandler [WEAK]
|
|
EXPORT DMA_Error_DriverIRQHandler [WEAK]
|
|
EXPORT MCM_IRQHandler [WEAK]
|
|
EXPORT FTF_IRQHandler [WEAK]
|
|
EXPORT Read_Collision_IRQHandler [WEAK]
|
|
EXPORT LVD_LVW_IRQHandler [WEAK]
|
|
EXPORT LLWU_IRQHandler [WEAK]
|
|
EXPORT WDOG_EWM_IRQHandler [WEAK]
|
|
EXPORT RNG_IRQHandler [WEAK]
|
|
EXPORT I2C0_DriverIRQHandler [WEAK]
|
|
EXPORT I2C1_DriverIRQHandler [WEAK]
|
|
EXPORT SPI0_DriverIRQHandler [WEAK]
|
|
EXPORT SPI1_DriverIRQHandler [WEAK]
|
|
EXPORT I2S0_Tx_DriverIRQHandler [WEAK]
|
|
EXPORT I2S0_Rx_DriverIRQHandler [WEAK]
|
|
EXPORT LPUART0_DriverIRQHandler [WEAK]
|
|
EXPORT UART0_RX_TX_DriverIRQHandler [WEAK]
|
|
EXPORT UART0_ERR_DriverIRQHandler [WEAK]
|
|
EXPORT UART1_RX_TX_DriverIRQHandler [WEAK]
|
|
EXPORT UART1_ERR_DriverIRQHandler [WEAK]
|
|
EXPORT UART2_RX_TX_DriverIRQHandler [WEAK]
|
|
EXPORT UART2_ERR_DriverIRQHandler [WEAK]
|
|
EXPORT Reserved53_IRQHandler [WEAK]
|
|
EXPORT Reserved54_IRQHandler [WEAK]
|
|
EXPORT ADC0_IRQHandler [WEAK]
|
|
EXPORT CMP0_IRQHandler [WEAK]
|
|
EXPORT CMP1_IRQHandler [WEAK]
|
|
EXPORT FTM0_IRQHandler [WEAK]
|
|
EXPORT FTM1_IRQHandler [WEAK]
|
|
EXPORT FTM2_IRQHandler [WEAK]
|
|
EXPORT Reserved61_IRQHandler [WEAK]
|
|
EXPORT RTC_IRQHandler [WEAK]
|
|
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
|
EXPORT PIT0_IRQHandler [WEAK]
|
|
EXPORT PIT1_IRQHandler [WEAK]
|
|
EXPORT PIT2_IRQHandler [WEAK]
|
|
EXPORT PIT3_IRQHandler [WEAK]
|
|
EXPORT PDB0_IRQHandler [WEAK]
|
|
EXPORT USB0_IRQHandler [WEAK]
|
|
EXPORT Reserved70_IRQHandler [WEAK]
|
|
EXPORT Reserved71_IRQHandler [WEAK]
|
|
EXPORT DAC0_IRQHandler [WEAK]
|
|
EXPORT MCG_IRQHandler [WEAK]
|
|
EXPORT LPTMR0_IRQHandler [WEAK]
|
|
EXPORT PORTA_IRQHandler [WEAK]
|
|
EXPORT PORTB_IRQHandler [WEAK]
|
|
EXPORT PORTC_IRQHandler [WEAK]
|
|
EXPORT PORTD_IRQHandler [WEAK]
|
|
EXPORT PORTE_IRQHandler [WEAK]
|
|
EXPORT SWI_IRQHandler [WEAK]
|
|
EXPORT Reserved81_IRQHandler [WEAK]
|
|
EXPORT Reserved82_IRQHandler [WEAK]
|
|
EXPORT Reserved83_IRQHandler [WEAK]
|
|
EXPORT Reserved84_IRQHandler [WEAK]
|
|
EXPORT Reserved85_IRQHandler [WEAK]
|
|
EXPORT Reserved86_IRQHandler [WEAK]
|
|
EXPORT FTM3_IRQHandler [WEAK]
|
|
EXPORT DAC1_IRQHandler [WEAK]
|
|
EXPORT ADC1_IRQHandler [WEAK]
|
|
EXPORT Reserved90_IRQHandler [WEAK]
|
|
EXPORT Reserved91_IRQHandler [WEAK]
|
|
EXPORT Reserved92_IRQHandler [WEAK]
|
|
EXPORT Reserved93_IRQHandler [WEAK]
|
|
EXPORT Reserved94_IRQHandler [WEAK]
|
|
EXPORT Reserved95_IRQHandler [WEAK]
|
|
EXPORT Reserved96_IRQHandler [WEAK]
|
|
EXPORT Reserved97_IRQHandler [WEAK]
|
|
EXPORT Reserved98_IRQHandler [WEAK]
|
|
EXPORT Reserved99_IRQHandler [WEAK]
|
|
EXPORT Reserved100_IRQHandler [WEAK]
|
|
EXPORT Reserved101_IRQHandler [WEAK]
|
|
EXPORT DefaultISR [WEAK]
|
|
DMA0_DriverIRQHandler
|
|
DMA1_DriverIRQHandler
|
|
DMA2_DriverIRQHandler
|
|
DMA3_DriverIRQHandler
|
|
DMA4_DriverIRQHandler
|
|
DMA5_DriverIRQHandler
|
|
DMA6_DriverIRQHandler
|
|
DMA7_DriverIRQHandler
|
|
DMA8_DriverIRQHandler
|
|
DMA9_DriverIRQHandler
|
|
DMA10_DriverIRQHandler
|
|
DMA11_DriverIRQHandler
|
|
DMA12_DriverIRQHandler
|
|
DMA13_DriverIRQHandler
|
|
DMA14_DriverIRQHandler
|
|
DMA15_DriverIRQHandler
|
|
DMA_Error_DriverIRQHandler
|
|
MCM_IRQHandler
|
|
FTF_IRQHandler
|
|
Read_Collision_IRQHandler
|
|
LVD_LVW_IRQHandler
|
|
LLWU_IRQHandler
|
|
WDOG_EWM_IRQHandler
|
|
RNG_IRQHandler
|
|
I2C0_DriverIRQHandler
|
|
I2C1_DriverIRQHandler
|
|
SPI0_DriverIRQHandler
|
|
SPI1_DriverIRQHandler
|
|
I2S0_Tx_DriverIRQHandler
|
|
I2S0_Rx_DriverIRQHandler
|
|
LPUART0_DriverIRQHandler
|
|
UART0_RX_TX_DriverIRQHandler
|
|
UART0_ERR_DriverIRQHandler
|
|
UART1_RX_TX_DriverIRQHandler
|
|
UART1_ERR_DriverIRQHandler
|
|
UART2_RX_TX_DriverIRQHandler
|
|
UART2_ERR_DriverIRQHandler
|
|
Reserved53_IRQHandler
|
|
Reserved54_IRQHandler
|
|
ADC0_IRQHandler
|
|
CMP0_IRQHandler
|
|
CMP1_IRQHandler
|
|
FTM0_IRQHandler
|
|
FTM1_IRQHandler
|
|
FTM2_IRQHandler
|
|
Reserved61_IRQHandler
|
|
RTC_IRQHandler
|
|
RTC_Seconds_IRQHandler
|
|
PIT0_IRQHandler
|
|
PIT1_IRQHandler
|
|
PIT2_IRQHandler
|
|
PIT3_IRQHandler
|
|
PDB0_IRQHandler
|
|
USB0_IRQHandler
|
|
Reserved70_IRQHandler
|
|
Reserved71_IRQHandler
|
|
DAC0_IRQHandler
|
|
MCG_IRQHandler
|
|
LPTMR0_IRQHandler
|
|
PORTA_IRQHandler
|
|
PORTB_IRQHandler
|
|
PORTC_IRQHandler
|
|
PORTD_IRQHandler
|
|
PORTE_IRQHandler
|
|
SWI_IRQHandler
|
|
Reserved81_IRQHandler
|
|
Reserved82_IRQHandler
|
|
Reserved83_IRQHandler
|
|
Reserved84_IRQHandler
|
|
Reserved85_IRQHandler
|
|
Reserved86_IRQHandler
|
|
FTM3_IRQHandler
|
|
DAC1_IRQHandler
|
|
ADC1_IRQHandler
|
|
Reserved90_IRQHandler
|
|
Reserved91_IRQHandler
|
|
Reserved92_IRQHandler
|
|
Reserved93_IRQHandler
|
|
Reserved94_IRQHandler
|
|
Reserved95_IRQHandler
|
|
Reserved96_IRQHandler
|
|
Reserved97_IRQHandler
|
|
Reserved98_IRQHandler
|
|
Reserved99_IRQHandler
|
|
Reserved100_IRQHandler
|
|
Reserved101_IRQHandler
|
|
DefaultISR
|
|
B DefaultISR
|
|
ENDP
|
|
ALIGN
|
|
|
|
|
|
END
|